Yun-Chen Lo

18 papers A* 5A 1C 2Journal 4Unranked 6
YearRankTypeTitle / Venue / Authors
2025 A* conf
P-DAC: Power-Efficient Photonic Accelerators for LLM Inference.
DAC
Wen-Tse Chang, Chun-Feng Wu, Yun-Chen Lo
2024 J jnl
A Nonvolatile AI-Edge Processor With SLC-MLC Hybrid ReRAM Compute-in-Memory Macro Using Current-Voltage-Hybrid Readout Scheme.
IEEE J. Solid State Circuits
Hung-Hsi Hsu, Tai-Hao Wen, Wei-Hsing Huang, Win-San Khwa, Yun-Chen Lo, Chuan-Jia Jhang, Yu-Hsiang Chin, Yu-Chiao Chen, Chung-Chuan Lo, Ren-Shuo Liu, Kea-Tiong Tang, Chih-Cheng Hsieh, Yu-Der Chih, Tsung-Yung Jonathan Chang, Meng-Fan Chang
2024 J jnl
ISSA: Architecting CNN Accelerators Using Input-Skippable, Set-Associative Computing-in-Memory.
IEEE Trans. Computers
Yun-Chen Lo, Jun-Shen Wu, Chia-Chun Wang, Yu-Chih Tsai, Chih-Chen Yeh, Wen-Chien Ting, Ren-Shuo Liu
2024 J jnl
Nanoscaling Floating-Point (NxFP): NanoMantissa, Adaptive Microexponents, and Code Recycling for Direct-Cast Compression of Large Language Models.
CoRR
Yun-Chen Lo, Gu-Yeon Wei, David Brooks
2023 — conf
A Nonvolatile Al-Edge Processor with 4MB SLC-MLC Hybrid-Mode ReRAM Compute-in-Memory Macro and 51.4-251TOPS/W.
ISSCC
Wei-Hsing Huang, Tai-Hao Wen, Je-Min Hung, Win-San Khwa, Yun-Chen Lo, Chuan-Jia Jhang, Hung-Hsi Hsu, Yu-Hsiang Chin, Yu-Chiao Chen, Chung-Chuan Lo, Ren-Shuo Liu, Kea-Tiong Tang, Chih-Cheng Hsieh, Yu-Der Chih, Tsung-Yung Jonathan Chang, Meng-Fan Chang
2023 C conf
BICEP: Exploiting Bitline Inversion for Efficient Operation-Unit-Based Compute-in-Memory Architecture: No Retraining Needed!
ICCD
Yun-Chen Lo, Chia-Chun Wang, Ren-Shuo Liu
2023 A* conf
Bit-Serial Cache: Exploiting Input Bit Vector Repetition to Accelerate Bit-Serial Inference.
DAC
Yun-Chen Lo, Ren-Shuo Liu
2023 A* conf
Block and Subword-Scaling Floating-Point (BSFP) : An Efficient Non-Uniform Quantization For Low Precision Inference.
ICLR
Yun-Chen Lo, Tse-Kuang Lee, Ren-Shuo Liu
2023 A* conf
Bucket Getter: A Bucket-based Processing Engine for Low-bit Block Floating Point (BFP) DNNs.
MICRO
Yun-Chen Lo, Ren-Shuo Liu
2023 C conf
Exploiting and Enhancing Computation Latency Variability for High-Performance Time-Domain Computing-in-Memory Neural Network Accelerators.
ICCD
Chia-Chun Wang, Yun-Chen Lo, Jun-Shen Wu, Yu-Chih Tsai, Chia-Cheng Chang, Tsen-Wei Hsu, Min-Wei Chu, Chuan-Yao Lai, Ren-Shuo Liu
2023 J jnl
LV: Latency-Versatile Floating-Point Engine for High-Performance Deep Neural Networks.
IEEE Comput. Archit. Lett.
Yun-Chen Lo, Yu-Chih Tsai, Ren-Shuo Liu
2023 A* conf
Morphable CIM: Improving Operation Intensity and Depthwise Capability for SRAM-CIM Architecture.
DAC
Yun-Chen Lo, Ren-Shuo Liu
2022 A conf
ISSA: Input-Skippable, Set-Associative Computing-in-Memory (SA-CIM) Architecture for Neural Network Accelerators.
ICCAD
Yun-Chen Lo, Chih-Chen Yeh, Jun-Shen Wu, Chia-Chun Wang, Yu-Chih Tsai, Wen-Chien Ting, Ren-Shuo Liu
2021 — conf
Interference-Free Design Methodology for Paper-Based Digital Microfluidic Biochips.
ASP-DAC
Yun-Chen Lo, Bing Li, Sooyong Park, Kwanwoo Shin, Tsung-Yi Ho
2020 — conf
15.4 A 22nm 2Mb ReRAM Compute-in-Memory Macro with 121-28TOPS/W for Multibit MAC Computing for Tiny AI Edge Devices.
ISSCC
Cheng-Xin Xue, Tsung-Yuan Huang, Je-Syu Liu, Ting-Wei Chang, Hui-Yao Kao, Jing-Hong Wang, Ta-Wei Liu, Shih-Ying Wei, Sheng-Po Huang, Wei-Chen Wei, Yi-Ren Chen, Tzu-Hsiang Hsu, Yen-Kai Chen, Yun-Chen Lo, Tai-Hsing Wen, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Meng-Fan Chang
2020 — conf
15.5 A 28nm 64Kb 6T SRAM Computing-in-Memory Macro with 8b MAC Operation for AI Edge Chips.
ISSCC
Xin Si, Yung-Ning Tu, Wei-Hsing Huang, Jian-Wei Su, Pei-Jung Lu, Jing-Hong Wang, Ta-Wei Liu, Ssu-Yen Wu, Ruhui Liu, Yen-Chi Chou, Zhixiao Zhang, Syuan-Hao Sie, Wei-Chen Wei, Yun-Chen Lo, Tai-Hsing Wen, Tzu-Hsiang Hsu, Yen-Kai Chen, William Shih, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Nan-Chun Lien, Wei-Chiang Shih, Yajuan He, Qiang Li, Meng-Fan Chang
2019 — conf
Physically Tightly Coupled, Logically Loosely Coupled, Near-Memory BNN Accelerator (PTLL-BNN).
ESSCIRC
Yun-Chen Lo, Yu-Chun Kuo, Yun-Sheng Chang, Jian-Hao Huang, Jun-Shen Wu, Wen-Chien Ting, Tai-Hsing Wen, Ren-Shuo Liu
2018 — conf
DrowsyNet: Convolutional neural networks with runtime power-accuracy tunability using inference-stage dropout.
VLSI-DAT
Ren-Shuo Liu, Yun-Chen Lo, Yuan-Chun Luo, Chih-Yu Shen, Cheng-Ju Lee