Yukiya Miura - RankMe

62 papers A 5B 7C 7Misc 1Journal 16Unranked 26

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	An Evolutionary Framework for Automatic Optimization Benchmark Generation via Large Language Models. CoRR Yuhiro Ono, Tomohiro Harada, Yukiya Miura
2026	J	`jnl`	Exploration of deep reinforcement learning method for cooperative control of connected automated vehicles at a roundabout. Artif. Life Robotics Reo Nakaya, Tomohiro Harada, Yukiya Miura, Kiyohiko Hattori, Johei Matsuoka
2025	B	`conf`	How Reliable is Validation Accuracy for Estimating Surrogate Model Generalization in Surrogate-Assisted Evolutionary Algorithms? SMC Yuki Hanawa, Tomohiro Harada, Yukiya Miura
2025	J	`jnl`	Impact of Surrogate Model Accuracy on Performance and Model Management Strategy in Surrogate-Assisted Evolutionary Algorithms. CoRR Yuki Hanawa, Tomohiro Harada, Yukiya Miura
2025	J	`jnl`	Impact of surrogate model accuracy on performance and model management strategy in surrogate-assisted evolutionary algorithms. Array Yuki Hanawa, Tomohiro Harada, Yukiya Miura
2025	—	`conf`	Large Language Model Driven Evolutionary Optimization Benchmark Generation Algorithm. GECCO Companion Yuhiro Ono, Tomohiro Harada, Yukiya Miura
2024	B	`conf`	Analysis of the Impact of Prediction Accuracy on Search Performance in Surrogate-assisted Evolutionary Algorithms. CEC Yuki Hanawa, Tomohiro Harada, Yukiya Miura
2024	B	`conf`	Cooperative Autonomous Driving Control among Vehicles of Different Sizes Using Deep Reinforcement Learning. IJCNN Akito Takenaka, Tomohiro Harada, Yukiya Miura, Kiyohiko Hattori, Johei Matuoka
2023	—	`conf`	Emergence of Cooperative Automated Driving Control at Roundabouts Using Deep Reinforcement Learning. SICE Reo Nakaya, Tomohiro Harada, Yukiya Miura, Kiyohiko Hattori, Johei Matsuoka
2023	—	`conf`	Hybrid Rocket Engine Design Using Pairwise Ranking Surrogate-assisted Differential Evolution. GECCO Companion Hitomi Kano, Tomohiro Harada, Yukiya Miura, Masahiro Kanazaki
2022	—	`conf`	Differential Evolution Using Surrogate Model Based on Pairwise Ranking Estimation for Constrained Optimization Problems. SCIS/ISIS Hitomi Kano, Tomohiro Harada, Yukiya Miura
2022	—	`conf`	Improving Data Sampling Efficiency of Sensitivity Analysis Based on Bilevel Multi-objective Evolutionary Algorithm. SCIS/ISIS Takuya Hakoishi, Tomohiro Harada, Yukiya Miura
2021	C	`conf`	A Method for Measuring Process Variations in the FPGA Chip Considering the Effect of Wire Delay. IOLTS Yukiya Miura, Shingo Tsutsumi
2020	Misc	`conf`	Innovative Test Practices in Asia. VTS Takeshi Iwasaki, Masao Aso, Haruji Futami, Satoshi Matsunaga, Yousuke Miyake, Takaaki Kato, Seiji Kajihara, Yukiya Miura, Smith Lai, Gavin Hung, Harry H. Chen, Haruo Kobayashi, Kazumi Hatayama
2020	C	`conf`	On-Chip Delay Measurement for Degradation Detection And Its Evaluation under Accelerated Life Test. IOLTS Yousuke Miyake, Takaaki Kato, Seiji Kajihara, Masao Aso, Haruji Futami, Satoshi Matsunaga, Yukiya Miura
2020	C	`conf`	Soft Error Tolerance of Power-Supply-Noise Hardened Latches. IOLTS Yukiya Miura, Yuya Kinoshita
2019	C	`conf`	Development of FF Circuits for Measures Against Power Supply Noise. IOLTS Yukiya Miura, Miyuki Inoue, Yuya Kinoshita
2017	C	`conf`	Simulation-based analysis of FF behavior in presence of power supply noise. IOLTS Yukiya Miura, Takuya Yamamoto
2016	J	`jnl`	Temperature and Voltage Measurement for Field Test Using an Aging-Tolerant Monitor. IEEE Trans. Very Large Scale Integr. Syst. Yousuke Miyake, Yasuo Sato, Seiji Kajihara, Yukiya Miura
2015	B	`conf`	LSI aging estimation using ring oscillators. ETS Yukiya Miura, Tatsunori Ikeda
2014	C	`conf`	A noise-tolerant master-slave flip-flop. IOLTS Yukiya Miura, Yoshihiro Ohkawa
2014	—	`conf`	An On-Chip Digital Environment Monitor for Field Test. ATS Seiji Kajihara, Yousuke Miyake, Yasuo Sato, Yukiya Miura
2014	—	`conf`	Temperature and Voltage Estimation Using Ring-Oscillator-Based Monitor for Field Test. ATS Yousuke Miyake, Yasuo Sato, Seiji Kajihara, Yukiya Miura
2012	A	`conf`	DART: Dependable VLSI test architecture and its implementation. ITC Yasuo Sato, Seiji Kajihara, Tomokazu Yoneda, Kazumi Hatayama, Michiko Inoue, Yukiya Miura, Satosni Untake, Takumi Hasegawa, Motoyuki Sato, Kotaro Shimamura
2012	—	`conf`	Dual Edge Triggered Flip-Flops for Noise Blocking and Application to Signal Delay Detection. Asian Test Symposium Yoshihiro Ohkawa, Yukiya Miura
2012	B	`conf`	On-chip temperature and voltage measurement for field testing. ETS Yukiya Miura, Yasuo Sato, Yousuke Miyake, Seiji Kajihara
2011	—	`conf`	A supply current testable register string DAC of decoder type. ISCIT Masaki Hashizume, Yutaka Hata, Hiroyuki Yotsuyanagi, Yukiya Miura
2011	B	`conf`	Dual Edge Triggered Flip-Flops for Noise Aware Design. ETS Yukiya Miura
2010	B	`conf`	On estimation of NBTI-Induced delay degradation. ETS Mitsumasa Noda, Seiji Kajihara, Yasuo Sato, Kohei Miyase, Xiaoqing Wen, Yukiya Miura
2008	J	`jnl`	Adaptive Fault Diagnosis of Analog Circuits by Operation-Region Model and J. Electron. Test. Yukiya Miura, Jiro Kato
2008	—	`conf`	Diagnosis of Analog Circuits by Using Multiple Transistors and Data Sampling. DFT Yukiya Miura, Jiro Kato
2008	J	`jnl`	Ramp Voltage Testing for Detecting Interconnect Open Faults. IEICE Trans. Inf. Syst. Yukiya Miura
2007	—	`conf`	Current Testable Design of Resistor String DACs. ATS Masaki Hashizume, Yutaka Hata, Tomomi Nishida, Hiroyuki Yotsuyanagi, Yukiya Miura
2007	A	`conf`	Dependable clock distribution for crosstalk aware design. ITC Yukiya Miura
2006	—	`conf`	A BIC Sensor Capable of Adjusting IDDQ Limit in Tests. ATS Masato Nakanishi, Masaki Hashizume, Hiroyuki Yotsuyanagi, Yukiya Miura
2006	—	`conf`	Current Testable Design of Resistor String DACs. DELTA Masaki Hashizume, Tomomi Nishida, Hiroyuki Yotsuyanagi, Takeomi Tamesada, Yukiya Miura
2006	—	`conf`	Detection of Interconnect Open Faults with Unknown Values by Ramp Voltage Application. ATS Yukiya Miura
2006	—	`conf`	Fault Diagnosis of Analog Circuits Based on Adaptive Test and Output Characteristics. DFT Yukiya Miura, Jiro Kato
2006	J	`jnl`	Proposal of Fault Diagnosis of Analog Circuits by Combining Operation-Region Model and J. Electron. Test. Yukiya Miura
2005	—	`conf`	Characteristics of Fault Diagnosis for Analog Circuits Based on Preset Test. DFT Yukiya Miura
2004	J	`jnl`	Analysis and Testing of Bridging Faults in CMOS Synchronous Sequential Circuits. IEICE Trans. Inf. Syst. Yukiya Miura
2004	—	`conf`	Fault Diagnosis of Analog Circuits by Operation-Region Model and X-Y Zoning Method. DFT Yukiya Miura
2003	—	`conf`	A BIST Circuit for IDDQ Tests. Asian Test Symposium Masaki Hashizume, Teppei Takeda, Hiroyuki Yotsuyanagi, Takeomi Tamesada, Yukiya Miura, Kozo Kinoshita
2003	—	`conf`	Analysis and Testing of Analog and Mixed-Signal Circuits by an Operation-Region Model: A Case Study of Application and Implementation. DFT Yukiya Miura, Daisuke Kato
2002	J	`jnl`	Behavior Analysis of Internal Feedback Bridging Faults in CMOS Circuits. J. Electron. Test. Yukiya Miura, Shuichi Seno
2001	—	`conf`	IDDQ Sensing Technique for High Speed IDDQ Testing. Asian Test Symposium Teppei Takeda, Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi, Yukiya Miura, Kozo Kinoshita
2001	—	`conf`	Internal feedback bridging faults in combinational CMOS circuits: analysis and testing. ETW Yukiya Miura, Shuichi Seno
2001	—	`conf`	Proposal of an Operation-Region Model for Analyzing Analog and Mixed-Signal Circuits. LATW Yukiya Miura
2000	—	`conf`	Simulation of resistive bridging fault to minimize the presence of intermediate voltage and oscillation in CMOS circuits. Asian Test Symposium Arabi Keshk, Yukiya Miura, Kozo Kinoshita
1999	J	`jnl`	A Low-Loss Built-In Current Sensor. J. Electron. Test. Yukiya Miura, Hiroshi Yamazaki
1999	—	`conf`	IDDQ Current Dependency on Test Vectors and Bridging Resistance. Asian Test Symposium Arabi Keshk, Kozo Kinoshita, Yukiya Miura
1999	—	`conf`	Procedure to Overcome the Byzantine General's Problem for Bridging Faults in CMOS Circuits. Asian Test Symposium Arabi Keshk, Kozo Kinoshita, Yukiya Miura
1998	—	`conf`	A High-Speed IDDQ Sensor for Low-Voltage ICs. Asian Test Symposium Masaki Hashizume, Yukiya Miura, Masahiro Ichimiya, Takeomi Tamesada, Kozo Kinoshita
1997	A	`conf`	An IDDQ Sensor Circuit for Low-Voltage ICs. ITC Yukiya Miura
1996	J	`jnl`	Real-Time Current Testing for A/D Converters. IEEE Des. Test Comput. Yukiya Miura
1995	A	`conf`	A Comparative Analysis of Input Stimuli for Testing Mixed-Signal LSIs Based on Curent Testing. ITC Yukiya Miura
1995	J	`jnl`	A Method of Current Testing for CMOS Digital and Mixed-Signal LSIs. IEICE Trans. Inf. Syst. Yukiya Miura, Sachio Naito
1994	C	`conf`	A Case Study of Mixed-Signal Integrated Circuit Testing: An Application of Current Testing Using the Upper Limit and the Lower Limit. ISCAS Yukiya Miura, Sachio Naito, Kozo Kinoshita
1993	J	`jnl`	Design of testing circuit and test generation for built-in current testing. Syst. Comput. Jpn. Yukiya Miura, Yasushi Wada, Kozo Kinoshita
1992	A	`conf`	Circuit Design for Built-in Current Testing. ITC Yukiya Miura, Kozo Kinoshita
1988	J	`jnl`	Built - in concurrent testing for semiconductor random access memories by concurrently testing cells on a word-line. Syst. Comput. Jpn. Yukiya Miura, Hideo Tamamoto, Yuichi Narita
1987	J	`jnl`	A built-in test for functional testing in semiconductor random access memory. Syst. Comput. Jpn. Yukiya Miura, Hideo Tamamoto, Yuichi Narita