Yukio Mitsuyama

47 papers A 2B 4Misc 1Journal 20Unranked 19

Year	Rank	Type	Title / Venue / Authors
2025	J	`jnl`	Evaluation of Efficient and Flexible Hardware-Software Co-Design of Advantage Actor-Critic Reinforcement Learning for Edge Deployment. IEEE Access Chavakorn Somjaisuk, Wang Liao, Yukio Mitsuyama
2021	—	`conf`	Development of Autonomous Driving System based on Image Recognition using Programmable SoCs. FPT Ryohei Yamamoto, Yuki Izumi, Ryo Aono, Takumi Nagahara, Tomonari Tanaka, Wang Liao, Yukio Mitsuyama
2020	—	`conf`	33.3 Via-Switch FPGA: 65nm CMOS Implementation and Architecture Extension for Al Applications. ISSCC Masanori Hashimoto, Xu Bai, Naoki Banno, Munehiro Tada, Toshitsugu Sakamoto, Jaehoon Yu, Ryutaro Doi, Yusuke Araki, Hidetoshi Onodera, Takashi Imagawa, Hiroyuki Ochi, Kazutoshi Wakabayashi, Yukio Mitsuyama, Tadahiko Sugibayashi
2020	—	`conf`	Characterizing Energetic Dependence of Low-Energy Neutron-induced MCUs in 65 nm bulk SRAMs. IRPS Wang Liao, Kojiro Ito, Yukio Mitsuyama, Masanori Hashimoto
2020	J	`jnl`	Measurement of Variations in FPGAs under Various Load Conditions. IPSJ Trans. Syst. LSI Des. Methodol. Yukio Mitsuyama, Takashi Asada, Makio Eguchi
2019	—	`conf`	Development of Autonomous Driving System Using Programmable SoCs. FPT Tomonari Tanaka, Itsuki Ikeno, Riku Tsuruoka, Takumi Kuchiba, Wang Liao, Yukio Mitsuyama
2018	—	`ch.`	Design Flow and Design Tools. Principles and Structures of FPGAs Tomonori Izumi, Yukio Mitsuyama
2018	J	`jnl`	Sensor Signal Processing Using High-Level Synthesis With a Layered Architecture. IEEE Embed. Syst. Lett. Hiroki Hihara, Akira Iwasaki, Masanori Hashimoto, Hiroyuki Ochi, Yukio Mitsuyama, Hidetoshi Onodera, Hiroyuki Kanbara, Kazutoshi Wakabayashi, Tadahiko Sugibayashi, Takashi Takenaka, Hiromitsu Hada, Munehiro Tada, Makoto Miyamura, Toshitsugu Sakamoto
2018	J	`jnl`	Via-Switch FPGA: Highly Dense Mixed-Grained Reconfigurable Architecture With Overlay Via-Switch Crossbars. IEEE Trans. Very Large Scale Integr. Syst. Hiroyuki Ochi, Kosei Yamaguchi, Tetsuaki Fujimoto, Junshi Hotate, Takashi Kishimoto, Toshiki Higashi, Takashi Imagawa, Ryutaro Doi, Munehiro Tada, Tadahiko Sugibayashi, Wataru Takahashi, Kazutoshi Wakabayashi, Hidetoshi Onodera, Yukio Mitsuyama, Jaehoon Yu, Masanori Hashimoto
2016	B	`conf`	A highly-dense mixed grained reconfigurable architecture with overlay crossbar interconnect using via-switch. FPL Junshi Hotate, Takashi Kishimoto, Toshiki Higashi, Hiroyuki Ochi, Ryutaro Doi, Munehiro Tada, Tadahiko Sugibayashi, Kazutoshi Wakabayashi, Hidetoshi Onodera, Yukio Mitsuyama, Masanori Hashimoto
2015	—	`conf`	Reliability-configurable mixed-grained reconfigurable array compatible with high-level synthesis. ASP-DAC Masanori Hashimoto, Dawood Alnajiar, Hiroaki Konoura, Yukio Mitsuyama, Hajime Shimada, Kazutoshi Kobayashi, Hiroyuki Kanbara, Hiroyuki Ochi, Takashi Imagawa, Kazutoshi Wakabayashi, Takao Onoye, Hidetoshi Onodera
2014	J	`jnl`	Comparative Evaluation of Lifetime Enhancement with Fault Avoidance on Dynamically Reconfigurable Devices. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Hiroaki Konoura, Takashi Imagawa, Yukio Mitsuyama, Masanori Hashimoto, Takao Onoye
2014	J	`jnl`	NBTI Mitigation Method by Inputting Random Scan-In Vectors in Standby Time. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Hiroaki Konoura, Toshihiro Kameda, Yukio Mitsuyama, Masanori Hashimoto, Takao Onoye
2014	J	`jnl`	Reliability-Configurable Mixed-Grained Reconfigurable Array Supporting C-Based Design and Its Irradiation Testing. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Hiroaki Konoura, Dawood Alnajiar, Yukio Mitsuyama, Hajime Shimada, Kazutoshi Kobayashi, Hiroyuki Kanbara, Hiroyuki Ochi, Takashi Imagawa, Kazutoshi Wakabayashi, Masanori Hashimoto, Takao Onoye, Hidetoshi Onodera
2014	J	`jnl`	SET Pulse-Width Measurement Suppressing Pulse-Width Modulation and Within-Die Process Variation Effects. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Ryo Harada, Yukio Mitsuyama, Masanori Hashimoto, Takao Onoye
2014	—	`conf`	Variability and Soft-Error Resilience in Dependable VLSI Platform. ATS Yukio Mitsuyama, Hidetoshi Onodera
2013	J	`jnl`	A Worst-Case-Aware Design Methodology for Noise-Tolerant Oscillator-Based True Random Number Generator With Stochastic Behavior Modeling. IEEE Trans. Inf. Forensics Secur. Takehiko Amaki, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye
2013	J	`jnl`	Field Slack Assessment for Predictive Fault Avoidance on Coarse-Grained Reconfigurable Devices. IEICE Trans. Inf. Syst. Toshihiro Kameda, Hiroaki Konoura, Dawood Alnajiar, Yukio Mitsuyama, Masanori Hashimoto, Takao Onoye
2013	J	`jnl`	Implementing Flexible Reliability in a Coarse-Grained Reconfigurable Architecture. IEEE Trans. Very Large Scale Integr. Syst. Dawood Alnajiar, Hiroaki Konoura, Younghun Ko, Yukio Mitsuyama, Masanori Hashimoto, Takao Onoye
2013	—	`conf`	Mixed-grained reconfigurable architecture supporting flexible reliability and C-based design. ReConFig Hiroaki Konoura, Dawood Alnajiar, Yukio Mitsuyama, Hiroyuki Ochi, Takashi Imagawa, Shinichi Noda, Kazutoshi Wakabayashi, Masanori Hashimoto, Takao Onoye
2013	J	`jnl`	PVT-induced timing error detection through replica circuits and time redundancy in reconfigurable devices. IEICE Electron. Express Dawood Alnajiar, Yukio Mitsuyama, Masanori Hashimoto, Takao Onoye
2012	B	`conf`	A predictive delay fault avoidance scheme for coarse-grained reconfigurable architecture. FPL Toshihiro Kameda, Hiroaki Konoura, Dawood Alnajiar, Yukio Mitsuyama, Masanori Hashimoto, Takao Onoye
2012	J	`jnl`	Adaptive Performance Compensation With In-Situ Timing Error Predictive Sensors for Subthreshold Circuits. IEEE Trans. Very Large Scale Integr. Syst. Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye
2012	—	`conf`	Static voltage over-scaling and dynamic voltage variation tolerance with replica circuits and time redundancy in reconfigurable devices. ReConFig Dawood Alnajiar, Masanori Hashimoto, Takao Onoye, Yukio Mitsuyama
2011	B	`conf`	Implications of Reliability Enhancement Achieved by Fault Avoidance on Dynamically Reconfigurable Architectures. FPL Hiroaki Konoura, Yukio Mitsuyama, Masanori Hashimoto, Takao Onoye
2011	—	`conf`	NBTI Mitigation by Giving Random Scan-in Vectors during Standby Mode. PATMOS Toshihiro Kameda, Hiroaki Konoura, Yukio Mitsuyama, Masanori Hashimoto, Takao Onoye
2011	J	`jnl`	Stress Probability Computation for Estimating NBTI-Induced Delay Degradation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Hiroaki Konoura, Yukio Mitsuyama, Masanori Hashimoto, Takao Onoye
2010	Misc	`conf`	A Design Procedure for Oscillator-Based Hardware Random Number Generator with Stochastic Behavior Modeling. WISA Takehiko Amaki, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye
2010	—	`conf`	Adaptive performance control with embedded timing error predictive sensors for subthreshold circuits. ASP-DAC Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye
2010	—	`conf`	Comparative study on delay degrading estimation due to NBTI with circuit/instance/transistor-level stress probability consideration. ISQED Hiroaki Konoura, Yukio Mitsuyama, Masanori Hashimoto, Takao Onoye
2010	J	`jnl`	Measurement Circuits for Acquiring SET Pulse Width Distribution with Sub-FO1-Inverter-Delay Resolution. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Ryo Harada, Yukio Mitsuyama, Masanori Hashimoto, Takao Onoye
2010	—	`conf`	Measurement circuits for acquiring SET pulsewidth distribution with sub-FO1-inverter-delay resolution. ISQED Ryo Harada, Yukio Mitsuyama, Masanori Hashimoto, Takao Onoye
2010	J	`jnl`	Transistor Variability Modeling and its Validation With Ring-Oscillation Frequencies for Body-Biased Subthreshold Circuits. IEEE Trans. Very Large Scale Integr. Syst. Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye
2009	—	`conf`	Adaptive performance compensation with in-situ timing error prediction for subthreshold circuits. CICC Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye
2009	J	`jnl`	An Experimental Study on Body-Biasing Layout Style Focusing on Area Efficiency and Speed Controllability. IEICE Trans. Electron. Koichi Hamamoto, Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye
2009	B	`conf`	Coarse-grained dynamically reconfigurable architecture with flexible reliability. FPL Dawood Alnajiar, Younghun Ko, Takashi Imagawa, Hiroaki Konoura, Masayuki Hiromoto, Yukio Mitsuyama, Masanori Hashimoto, Hiroyuki Ochi, Takao Onoye
2009	J	`jnl`	Trade-Off Analysis between Timing Error Rate and Power Dissipation for Adaptive Speed Control with Timing Error Prediction. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye
2009	—	`conf`	Trade-off analysis between timing error rate and power dissipation for adaptive speed control with timing error prediction. ASP-DAC Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye
2009	A	`conf`	Tuning-friendly body bias clustering for compensating random variability in subthreshold circuits. ISLPED Koichi Hamamoto, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye
2008	J	`jnl`	Area-Efficient Reconfigurable Architecture for Media Processing. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Yukio Mitsuyama, Kazuma Takahashi, Rintaro Imai, Masanori Hashimoto, Takao Onoye, Isao Shirakawa
2008	A	`conf`	Correlation verification between transistor variability model with body biasing and ring oscillation frequency in 90nm subthreshold circuits. ISLPED Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye
2008	—	`conf`	Experimental study on body-biasing layout style-- negligible area overhead enables sufficient speed controllability --. ACM Great Lakes Symposium on VLSI Koichi Hamamoto, Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye
2005	J	`jnl`	Architecture of IEEE802.11i Cipher Algorithms for Embedded Systems. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Yukio Mitsuyama, Motoki Kimura, Takao Onoye, Isao Shirakawa
2002	—	`conf`	Burst mode: a new acceleration mode for 128-bit block ciphers. CICC Yukio Mitsuyama, Zaldy Andales, Takao Onoye, Isao Shirakawa
2001	—	`conf`	A dynamically reconfigurable hardware-based cipher chip. ASP-DAC Yukio Mitsuyama, Zaldy Andales, Takao Onoye, Isao Shirakawa
2001	—	`conf`	VLSI architecture of dynamically reconfigurable hardware-based cipher. ISCAS (4) Yukio Mitsuyama, Zaldy Andales, Takao Onoye, Isao Shirakawa
1999	—	`conf`	FeRAM Circuit Technology for System on a Chip. Evolvable Hardware Koji Asari, Yukio Mitsuyama, Takao Onoye, Isao Shirakawa, Hiroshige Hirano, Toshiyuki Honda, Tatsuo Otsuki, Takaaki Baba, Teresa H. Meng