Yukiko Kubo

11 papers Journal 5Unranked 6
YearRankTypeTitle / Venue / Authors
2006 J jnl
Global Routing by Iterative Improvements for Two-Layer Ball Grid Array Packages.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Yukiko Kubo, Atsushi Takahashi
2005 J jnl
A Via Assignment and Global Routing Method for 2-Layer Ball Grid Array Packages.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Yukiko Kubo, Atsushi Takahashi
2005 — conf
A global routing method for 2-layer ball grid array packages.
ISPD
Yukiko Kubo, Atsushi Takahashi
2005 J jnl
Equidistance routing in high-speed VLSI layout design.
Integr.
Yukiko Kubo, Hiroshi Miyashita, Yoji Kajitani, Kazuyuki Tateishi
2004 — conf
Equidistance routing in high-speed VLSI layout design.
ACM Great Lakes Symposium on VLSI
Yukiko Kubo, Hiroshi Miyashita, Yoji Kajitani, Kazuyuki Tateishi
2003 J jnl
An Incremental Wiring Algorithm for VLSI Layout Design.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Yukiko Kubo, Shigetoshi Nakatake, Yoji Kajitani, Masahiro Kawakita
2002 — conf
Chip size estimation based on wiring area.
APCCAS (2)
Yukiko Kubo, Shigetoshi Nakatake, Yoji Kajitani, Masahiro Kawakita
2002 J jnl
Consistent floorplanning with hierarchical superconstraints.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Shigetoshi Nakatake, Yukiko Kubo, Yoji Kajitani
2002 — conf
Explicit Expression and Simultaneous Optimization of Placement and Routing for Analog IC Layouts.
ASP-DAC/VLSI Design
Yukiko Kubo, Shigetoshi Nakatake, Yoji Kajitani, Masahiro Kawakita
2001 — conf
Consistent floorplanning with super hierarchical constraints.
ISPD
Shigetoshi Nakatake, Yukiko Kubo, Yoji Kajitani
2000 — conf
Self-reforming routing for stochastic search in VLSI interconnection layout.
ASP-DAC
Yukiko Kubo, Yasuhiro Takashima, Shigetoshi Nakatake, Yoji Kajitani