Yukihito Oowaki

25 papers C 1Journal 17Unranked 7

Year	Rank	Type	Title / Venue / Authors
2015	—	`conf`	Caching mechanisms towards single-level storage systems for Internet of Things. VLSIC Yosuke Bando, Konosuke Watanabe, Ken-ichi Maeda, Hiroki Kudo, Masahiro Ishiyama, Atsushi Kunimatsu, Hiroto Nakai, Masafumi Takahashi, Yukihito Oowaki
2014	—	`conf`	19.3 66.3KIOPS-random-read 690MB/s-sequential-read universal Flash storage device controller with unified memory extension. ISSCC Konosuke Watanabe, Kenichiro Yoshii, Nobuhiro Kondo, Ken-ichi Maeda, Toshio Fujisawa, Junji Wadatsumi, Daisuke Miyashita, Shouhei Kousai, Yasuo Unekawa, Shinsuke Fujii, Takuma Aoyama, Takayuki Tamura, Atsushi Kunimatsu, Yukihito Oowaki
2014	—	`conf`	A UHS-II SD card controller with 240MB/s write throughput and 260MB/s read throughput. A-SSCC Kenta Yasufuku, Naoto Oshiyama, Toshitada Saito, Yukimasa Miyamoto, Yutaka Nakamura, Ryota Terauchi, Atsushi Kondo, Takuma Aoyama, Masafumi Takahashi, Yukihito Oowaki, Ryoichi Bandai
2014	J	`jnl`	An LDPC Decoder With Time-Domain Analog and Digital Mixed-Signal Processing. IEEE J. Solid State Circuits Daisuke Miyashita, Ryo Yamaki, Kazunori Hashiyoshi, Hiroyuki Kobayashi, Shouhei Kousai, Yukihito Oowaki, Yasuo Unekawa
2013	—	`conf`	A 10.4pJ/b (32, 8) LDPC decoder with time-domain analog and digital mixed-signal processing. ISSCC Daisuke Miyashita, Ryo Yamaki, Kazunori Hashiyoshi, Hiroyuki Kobayashi, Shouhei Kousai, Yukihito Oowaki, Yasuo Unekawa
2011	J	`jnl`	A 40 nm 222 mW H.264 Full-HD Decoding, 25 Power Domains, 14-Core Application Processor With x512b Stacked DRAM. IEEE J. Solid State Circuits Yu Kikuchi, Makoto Takahashi, Tomohisa Maeda, Masatoshi Fukuda, Yasuhiro Koshio, Hiroyuki Hara, Hideho Arakida, Hideaki Yamamoto, Yousuke Hagiwara, Tetsuya Fujita, Manabu Watanabe, Hirokazu Ezawa, Takayoshi Shimazawa, Yasuo Ohara, Takashi Miyamori, Mototsugu Hamada, Masafumi Takahashi, Yukihito Oowaki
2011	—	`conf`	Development of low power and high performance application processor (T6G) for multimedia mobile applications. ASP-DAC Yoshiyuki Kitasho, Yu Kikuchi, Takayoshi Shimazawa, Yasuo Ohara, Masafumi Takahashi, Yoshio Masubuchi, Yukihito Oowaki
2010	—	`conf`	A 222mW H.264 Full-HD decoding application processor with x512b stacked DRAM in 40nm. ISSCC Yu Kikuchi, Makoto Takahashi, Tomohisa Maeda, Hiroyuki Hara, Hideho Arakida, Hideaki Yamamoto, Yousuke Hagiwara, Tetsuya Fujita, Manabu Watanabe, Takayoshi Shimazawa, Yasuo Ohara, Takashi Miyamori, Mototsugu Hamada, Yukihito Oowaki
2007	C	`conf`	An automated runtime power-gating scheme. ICCD Mototsugu Hamada, Takeshi Kitahara, Naoyuki Kawabe, Hironori Sato, Tsuyoshi Nishikawa, Takayoshi Shimazawa, Takahiro Yamashita, Hiroyuki Hara, Yukihito Oowaki
2006	J	`jnl`	A 63-mW H.264/MPEG-4 audio/visual codec LSI with module-wise dynamic Voltage/frequency scaling. IEEE J. Solid State Circuits Toshihide Fujiyoshi, Shinichiro Shiratake, Shuou Nomura, Tsuyoshi Nishikawa, Yoshiyuki Kitasho, Hideho Arakida, Yuji Okuda, Yoshiro Tsuboi, Mototsugu Hamada, Hiroyuki Hara, Tetsuya Fujita, Fumitoshi Hatori, Takayoshi Shimazawa, Kunihiko Yahagi, Hideki Takeda, Masami Murakata, Fumihiro Minami, Naoyuki Kawabe, Takeshi Kitahara, Katsuhiro Seta, Masafumi Takahashi, Yukihito Oowaki, Tohru Furuyama
2006	J	`jnl`	Conditional Data Mapping Flip-Flops for Low-Power and High-Performance Systems. IEEE Trans. Very Large Scale Integr. Syst. Chen Kong Teh, Mototsugu Hamada, Tetsuya Fujita, Hiroyuki Hara, N. Ikumi, Yukihito Oowaki
2006	J	`jnl`	Module-Wise Dynamic Voltage and Frequency Scaling for a 90 nm H.264/MPEG-4 Codec LSI. IEICE Trans. Electron. Yukihito Oowaki, Shinichiro Shiratake, Toshihide Fujiyoshi, Mototsugu Hamada, Fumitoshi Hatori, Masami Murakata, Masafumi Takahashi
2005	—	`conf`	A conditional clocking flip-flop for low power H.264/MPEG-4 audio/visual codec LSI. CICC Mototsugu Hamada, Hiroyuki Hara, Tetsuya Fujita, Chen Kong Teh, Takayoshi Shimazawa, Naoyuki Kawabe, Takeshi Kitahara, Yu Kikuchi, Tsuyoshi Nishikawa, Makoto Takahashi, Yukihito Oowaki
2001	J	`jnl`	A 76-mm IEEE J. Solid State Circuits Daisaburo Takashima, Yoshiaki Takeuchi, Tadashi Miyakawa, Yasuo Itoh, Ryu Ogiwara, Masahiro Kamoshida, Katsuhiko Hoya, Sumiko Mano Doumae, Tohru Ozaki, Hiroyuki Kanaya, Koji Yamakawa, Iwao Kunishima, Yukihito Oowaki
1999	J	`jnl`	A sub-40-ns chain FRAM architecture with 7-ns cell-plate-line drive. IEEE J. Solid State Circuits Daisaburo Takashima, Susumu Shuto, Iwao Kunishima, Hiroyuki Takenaka, Yukihito Oowaki, Shin'ichi Tanaka
1998	J	`jnl`	Noise suppression scheme for gigabit-scale and gigabyte/s data-rate LSI's. IEEE J. Solid State Circuits Daisaburo Takashima, Yukihito Oowaki, Shigeyoshi Watanabe, Kazunori Ohuchi
1997	J	`jnl`	A novel power-off mode for a battery-backup DRAM. IEEE J. Solid State Circuits Daisaburo Takashima, Yukihito Oowaki
1994	J	`jnl`	Open/folded bit-line arrangement for ultra-high-density DRAM's. IEEE J. Solid State Circuits Daisaburo Takashima, Shigeyoshi Watanabe, Hiroaki Nakano, Yukihito Oowaki, Kazunori Ohuchi
1994	J	`jnl`	Standby/active mode logic for sub-1-V operating ULSI memory. IEEE J. Solid State Circuits Daisaburo Takashima, Shigeyoshi Watanabe, Hiroalu Nakano, Yukihito Oowaki, Kazunori Ohuchi, Hiroyuki Tango
1993	J	`jnl`	An experimental DRAM with a NAND-structured cell. IEEE J. Solid State Circuits Takehiro Hasegawa, Daisaburo Takashima, Ryu Ogiwara, Masako Ohta, Shinichiro Shiratake, Takeshi Hamamoto, Takashi Yamada, Masami Aoki, Shigeru Ishibashi, Yukihito Oowaki, Shigeyoshi Watanabe, Fujio Masuoka
1992	J	`jnl`	Word-line architecture for highly reliable 64-Mb DRAM. IEEE J. Solid State Circuits Daisaburo Takashima, Yukihito Oowaki, Ryu Ogiwara, Yohji Watanabe, Kenji Tsuchida, Masako Ohta, Hiroaki Nakano, Shigeyoshi Watanabe, Kazunori Ohuchi
1991	J	`jnl`	A 33-ns 64-Mb DRAM. IEEE J. Solid State Circuits Yukihito Oowaki, Kenji Tsuchida, Yohji Watanabe, Daisaburo Takashima, Masako Ohta, Hiroaki Nakano, Shigeyoshi Watanabe, Akihiro Nitayama, Fumio Horiguchi, Kazunori Ohuchi, Fujio Masuoka
1990	J	`jnl`	The stabilized reference-line (SRL) technique for scaled DRAMs. IEEE J. Solid State Circuits Kenji Tsuchida, Yukihito Oowaki, Masako Ohta, Daisaburo Takashima, Shigeyoshi Watanabe, Kazuya Ohuchi, Fujio Masuoka
1989	J	`jnl`	An experimental 16-Mbit CMOS DRAM chip with a 100-MHz serial read/write mode. IEEE J. Solid State Circuits Shigeyoshi Watanabe, Yukihito Oowaki, Yasuo Itoh, Koji Sakui, Kenji Numata, Tsuneaki Fuse, Takayuki Kobayashi, Kenji Tsuchida, Masahiko Chiba, Takahiko Hara, Masako Ohta, Fumio Horiguchi, Katsuhiko Hieda, Akihiro Nitayama, Takeshi Hamamoto, Kazunori Ohuchi, Fujio Masuoka
1989	J	`jnl`	New nibbled-page architecture for high-density DRAMs. IEEE J. Solid State Circuits Kenji Numata, Yukihito Oowaki, Yasuo Itoh, Takahiko Hara, Kenji Tsuchida, Masako Ohta, Shigyoshi Watanabe, Kazunori Ohuchi