Yuji Osaki

13 papers Journal 7Unranked 6
YearRankTypeTitle / Venue / Authors
2014 J jnl
A Fully On-Chip, 6.66-kHz, 320-nA, 56ppm/°C, CMOS Relaxation Oscillator with PVT Variation Compensation Circuit.
IEICE Trans. Electron.
Keishi Tsubaki, Tetsuya Hirose, Yuji Osaki, Seiichiro Shiga, Nobutaka Kuroki, Masahiro Numa
2013 J jnl
1.2-V Supply, 100-nW, 1.09-V Bandgap and 0.7-V Supply, 52.5-nW, 0.55-V Subbandgap Reference Circuits for Nanowatt CMOS LSIs.
IEEE J. Solid State Circuits
Yuji Osaki, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa
2013 J jnl
A 0.8-V 110-nA CMOS current reference circuit using subthreshold operation.
IEICE Electron. Express
Igors Homjakovs, Tetsuya Hirose, Yuji Osaki, Masanori Hashimoto, Takao Onoye
2012 — conf
A 6.66-kHz, 940-nW, 56ppm/°C, fully on-chip PVT variation tolerant CMOS relaxation oscillator.
ICECS
Keishi Tsubaki, Tetsuya Hirose, Yuji Osaki, Seiichiro Shiga, Nobutaka Kuroki, Masahiro Numa
2012 J jnl
A Low-Power Level Shifter With Logic Error Correction for Extremely Low-Voltage Digital CMOS LSIs.
IEEE J. Solid State Circuits
Yuji Osaki, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa
2012 — conf
A low-power single-slope analog-to-digital converter with digital PVT calibration.
ICECS
Yuji Osaki, Tetsuya Hirose, Keishi Tsubaki, Nobutaka Kuroki, Masahiro Numa
2012 — conf
A nano-watt power CMOS amplifier with adaptive biasing for power-aware analog LSIs.
ESSCIRC
Yumiko Tsuruya, Tetsuya Hirose, Yuji Osaki, Nobutaka Kuroki, Masahiro Numa, Osamu Kobayashi
2011 — conf
A 95-nA, 523ppm/°C, 0.6-μW CMOS current reference circuit with subthreshold MOS resistor ladder.
ASP-DAC
Yuji Osaki, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa
2011 — conf
A level shifter with logic error correction circuit for extremely low-voltage digital CMOS LSIs.
ESSCIRC
Yuji Osaki, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa
2011 J jnl
A wide input voltage range level shifter circuit for extremely low-voltage digital LSIs.
IEICE Electron. Express
Yuji Osaki, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa
2011 J jnl
Robust Subthreshold CMOS Digital Circuit Design with On-Chip Adaptive Supply Voltage Scaling Technique.
IEICE Trans. Electron.
Yuji Osaki, Tetsuya Hirose, Kei Matsumoto, Nobutaka Kuroki, Masahiro Numa
2011 J jnl
Subthreshold SRAM with Write Assist Technique Using On-Chip Threshold Voltage Monitoring Circuit.
IEICE Trans. Electron.
Kei Matsumoto, Tetsuya Hirose, Yuji Osaki, Nobutaka Kuroki, Masahiro Numa
2010 — conf
A nano-ampere current reference circuit and its temperature dependence control by using temperature characteristics of carrier mobilities.
ESSCIRC
Tetsuya Hirose, Yuji Osaki, Nobutaka Kuroki, Masahiro Numa