Yuichiro Miyaoka

12 papers Journal 4Unranked 8
YearRankTypeTitle / Venue / Authors
2006 — conf
An interface-circuit synthesis method with configurable processor core in IP-based SoC designs.
ASP-DAC
Shunitsu Kohara, Naoki Tomono, Jumpei Uchida, Yuichiro Miyaoka, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
2005 J jnl
A SIMD Instruction Set and Functional Unit Synthesis Algorithm with SIMD Operation Decomposition.
IEICE Trans. Inf. Syst.
Nozomu Togawa, Koichi Tachikake, Yuichiro Miyaoka, Masao Yanagisawa, Tatsuo Ohtsuki
2005 — conf
A processor core synthesis system in IP-based SoC design.
ASP-DAC
Naoki Tomono, Shunitsu Kohara, Jumpei Uchida, Yuichiro Miyaoka, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
2005 J jnl
Sub-operation Parallelism Optimization in SIMD Processor Core Synthesis.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Hideki Kawazu, Jumpei Uchida, Yuichiro Miyaoka, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
2005 — conf
Sub-operation parallelism optimization in SIMD processor synthesis and its experimental evaluations.
ISCAS (4)
Nozomu Togawa, Hideki Kawazu, Jumpei Uchida, Yuichiro Miyaoka, Masao Yanagisawa, Tatsuo Ohtsuki
2004 — conf
A cosynthesis algorithm for application specific processors with heterogeneous datapaths.
ASP-DAC
Yuichiro Miyaoka, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
2004 — conf
Instruction set and functional unit synthesis for SIMD processor cores.
ASP-DAC
Nozomu Togawa, Koichi Tachikake, Yuichiro Miyaoka, Masao Yanagisawa, Tatsuo Ohtsuki
2003 J jnl
A Hardware/Software Partitioning Algorithm for Processor Cores with Packed SIMD-Type Instructions.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Nozomu Togawa, Koichi Tachikake, Yuichiro Miyaoka, Masao Yanagisawa, Tatsuo Ohtsuki
2003 J jnl
A Retargetable Simulator Generator for DSP Processor Cores with Packed SIMD-type Instructions.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Nozomu Togawa, Kyosuke Kasahara, Yuichiro Miyaoka, Jinku Choi, Masao Yanagisawa, Tatsuo Ohtsuki
2003 — conf
A hardware/software partitioning algorithm for SIMD processor cores.
ASP-DAC
Koichi Tachikake, Nozomu Togawa, Yuichiro Miyaoka, Jinku Choi, Masao Yanagisawa, Tatsuo Ohtsuki
2002 — conf
An algorithm of hardware unit generation for processor core synthesis with packed SIMD type instructions.
APCCAS (1)
Yuichiro Miyaoka, Jinku Choi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
2001 — conf
Area/delay estimation for digital signal processor cores.
ASP-DAC
Yuichiro Miyaoka, Yoshiharu Kataoka, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki