Yuichi Nakamura

60 papers A* 4A 1B 1C 4Journal 29Unranked 20
YearRankTypeTitle / Venue / Authors
2025 — ed.
Proceedings of the 30th Asia and South Pacific Design Automation Conference, ASPDAC 2025, Tokyo, Japan, January 20-23, 2025
ASPDAC
Yuichi Nakamura, Yu Wang
2025 J jnl
The 3rd Workshop on Quantum in Consumer Technology at IEEE Quantum Week 2024.
IEEE Consumer Electron. Mag.
Rafael Sotelo, Edoardo Giusto, Yuichi Nakamura, Jingbo Wang, Sreeraman Rajan, Himanshu Thapliyal
2024 J jnl
The 2nd Workshop on Quantum in Consumer Technology At IEEE Quantum Week 2023.
IEEE Consumer Electron. Mag.
Rafael Sotelo, Edoardo Giusto, Yuichi Nakamura, Jingbo Wang
2023 — conf
Technologies for Optical Submarine Cables: Past Present & Future.
OFC
Yuichi Nakamura, Hitoshi Takeshita
2023 J jnl
The First Workshop on Quantum in Consumer Technology at IEEE Quantum Week 2022.
IEEE Consumer Electron. Mag.
Rafael Sotelo, Jingbo Wang, Yuichi Nakamura, Ahmed Farouk, Rosario Arjona, Salvador E. Venegas-Andraca, Alex James, Araceli Venegas-Gomez, Bill Gonzalez
2021 C conf
Can Quantum Technologies Change "Consumer Electronics"?
ICCE
Yuichi Nakamura
2021 — conf
Theoretical and Experimental Analysis of Traveling Salesman Walk Problem.
APCCAS
Yasuhiro Takashima, Yuichi Nakamura
2019 — conf
Past, Current and Future Technologies for Optical Submarine Cables.
PHOTONICS@SC
Hitoshi Takeshita, Masaki Sato, Yoshihisa Inada, Emmanuel Le Taillandier de Gabory, Yuichi Nakamura
2018 J jnl
Silicon Photonics for Computing Systems.
ACM J. Emerg. Technol. Comput. Syst.
Jiang Xu, Yuichi Nakamura, Andrew B. Kahng
2018 — conf
Task Allocation and Scheduling Optimization in the Heterogeneous Core System.
NGCAS
Ryota Tsuchihashi, Komei Nomura, Yasuhiro Takashima, Yuichi Nakamura
2017 J jnl
A Loitering Discovery System Using Efficient Similarity Search Based on Similarity Hierarchy.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Jianquan Liu, Shoji Nishimura, Takuya Araki, Yuichi Nakamura
2017 — conf
Accelerating NFV application using CPU-FPGA tightly coupled architecture.
FPT
Yoshikazu Watanabe, Yuki Kobayashi, Takashi Takenaka, Takeo Hosomi, Yuichi Nakamura
2017 — conf
Future trend of deep learning frameworks - From the perspective of big data analytics and HPC.
APSIPA
Takuya Araki, Yuichi Nakamura
2017 A conf
Novel heterogeneous computing platforms and 5G communications for IoT applications.
ICCAD
Yuichi Nakamura, Hideyuki Shimonishi, Yuki Kobayashi, Kozo Satoda, Yashuhiro Matsunaga, Dai Kanetomo
2017 J jnl
Sustainable Incentive Mechanisms for Mobile Crowdsensing: Part 1.
IEEE Commun. Mag.
Linghe Kong, Kui Ren, Muhammad Khurram Khan, Qi Li, Ammar Rayes, Mérouane Debbah, Yuichi Nakamura
2017 J jnl
Sustainable Incentive Mechanisms for Mobile Crowdsensing: Part 2.
IEEE Commun. Mag.
Linghe Kong, Kui Ren, Muhammad Khurram Khan, Qi Li, Ammar Rayes, Mérouane Debbah, Yuichi Nakamura
2017 — conf
The Spirit of in-house CAD Achieved by the Legend of Master "Prof. Goto" and his Apprentices.
ISPD
Yuichi Nakamura
2016 — conf
Inter/intra-chip optical interconnection network: opportunities, challenges, and implementations.
NOCS
Peng Yang, Shigeru Nakamura, Kenichiro Yashiki, Zhehui Wang, Luan H. K. Duong, Zhifei Wang, Xuanqi Chen, Yuichi Nakamura, Jiang Xu
2016 — conf
PEVaS: Power and execution-time variation-aware scheduling for MPSoC.
NEWCAS
Komei Nomura, Yasuhiro Takashima, Yuichi Nakamura
2015 — conf
FPGA-accelerated complex event processing.
VLSIC
Takashi Takenaka, Hiroaki Inoue, Takeo Hosomi, Yuichi Nakamura
2015 J jnl
Inter-FPGA Routing for Partially Time-Multiplexing Inter-FPGA Signals on Multi-FPGA Systems with Various Topologies.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Masato Inagi, Yuichi Nakamura, Yasuhiro Takashima, Shin'ichi Wakabayashi
2014 — conf
An NoC-based evaluation platform for safety-critical automotive applications.
APCCAS
Tomohiro Yoneda, Masashi Imai, Hiroshi Saito, Takahiro Hanyu, Kenji Kise, Yuichi Nakamura
2013 J jnl
A Non-volatile Reconfigurable Offloader for Wireless Sensor Nodes.
Inf. Media Technol.
Shogo Nakaya, Makoto Miyamura, Noboru Sakimura, Yuichi Nakamura, Tadahiko Sugibayashi
2013 J jnl
A Non-volatile Reconfigurable Offloader for Wireless Sensor Nodes.
IPSJ Trans. Syst. LSI Des. Methodol.
Shogo Nakaya, Makoto Miyamura, Noboru Sakimura, Yuichi Nakamura, Tadahiko Sugibayashi
2013 — conf
Adaptive sensing of ECG signals using R-R interval prediction.
EMBC
Shogo Nakaya, Yuichi Nakamura
2013 C conf
Revisiting rendezvous protocols in the context of RDMA-capable host channel adapters and many-core processors.
EuroMPI
Masamichi Takagi, Yuichi Nakamura, Atsushi Hori, Balazs Gerofi, Yutaka Ishikawa
2013 J jnl
Write Control Method for Nonvolatile Flip-Flops Based on State Transition Analysis.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Naoya Okada, Yuichi Nakamura, Shinji Kimura
2012 J jnl
A non-volatile reconfigurable offloader for wireless sensor nodes.
SIGARCH Comput. Archit. News
Shogo Nakaya, Makoto Miyamura, Noboru Sakimura, Yuichi Nakamura, Tadahiko Sugibayashi
2012 — conf
An ILP-based Multiple Task Allocation Method for Fault Tolerance in Networks-on-Chip.
MCSoC
Hiroshi Saito, Tomohiro Yoneda, Yuichi Nakamura
2011 J jnl
A Verification and Analysis Tool Set for Embedded System Design.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Yuichi Nakamura
2011 — conf
A low power technology mapping method for Adaptive Logic Module.
FPT
Wei Chen, Xiaolin Zhang, Takeshi Yoshimura, Yuichi Nakamura
2011 — conf
Flexible architecture optimization and ASIC implementation of group signature algorithm using a customized HLS methodology.
HOST
Sumio Morioka, Toshiyuki Isshiki, Satoshi Obana, Yuichi Nakamura, Kazue Sako
2010 C conf
Delay analysis of sub-path on fabricated chips by several path-delay tests.
ISCAS
Takanobu Shiki, Yasuhiro Takashima, Yuichi Nakamura
2010 J jnl
Globally Optimal Time-multiplexing of Inter-FPGA Connections for Multi-FPGA Prototyping Systems.
Inf. Media Technol.
Masato Inagi, Yasuhiro Takashima, Yuichi Nakamura
2010 J jnl
Globally Optimal Time-multiplexing of Inter-FPGA Connections for Multi-FPGA Prototyping Systems.
IPSJ Trans. Syst. LSI Des. Methodol.
Masato Inagi, Yasuhiro Takashima, Yuichi Nakamura
2009 B conf
Globally optimal time-multiplexing in inter-FPGA connections for accelerating multi-FPGA systems.
FPL
Masato Inagi, Yasuhiro Takashima, Yuichi Nakamura
2008 J jnl
A Study of Multi-core Processor Design with Asynchronous Interconnect Using Synchronous Design Tools.
Inf. Media Technol.
Katsunori Tanaka, Yuichi Nakamura, Atsushi Atarashi
2008 J jnl
A Study of Multi-core Processor Design with Asynchronous Interconnect Using Synchronous Design Tools.
IPSJ Trans. Syst. LSI Des. Methodol.
Katsunori Tanaka, Yuichi Nakamura, Atsushi Atarashi
2008 J jnl
A Synthesis Method of General Floating-Point Arithmetic Units by Aligned Partition.
Inf. Media Technol.
Liangwei Ge, Song Chen, Yuichi Nakamura, Takeshi Yoshimura
2008 J jnl
A Synthesis Method of General Floating-Point Arithmetic Units by Aligned Partition.
IPSJ Trans. Syst. LSI Des. Methodol.
Liangwei Ge, Song Chen, Yuichi Nakamura, Takeshi Yoshimura
2008 — conf
A design method for skew tolerant latch design.
APCCAS
Yuichi Nakamura
2008 J jnl
Fine-Grained Power Gating Based on the Controlling Value of Logic Elements.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Lei Chen, Takashi Horiyama, Yuichi Nakamura, Shinji Kimura
2008 C conf
ILP-based optimization of time-multiplexed I/O assignment for multi-FPGA systems.
ISCAS
Masato Inagi, Yasuhiro Takashima, Yuichi Nakamura, Atsushi Takahashi
2008 J jnl
Optimal Time-Multiplexing in Inter-FPGA Connections for Accelerating Multi-FPGA Prototyping Systems.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Masato Inagi, Yasuhiro Takashima, Yuichi Nakamura, Atsushi Takahashi
2008 J jnl
Post-Silicon Clock-Timing Tuning Based on Statistical Estimation.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Yuko Hashizume, Yasuhiro Takashima, Yuichi Nakamura
2007 J jnl
A Performance-Driven Circuit Bipartitioning Method Considering Time-Multiplexed I/Os.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Masato Inagi, Yasuhiro Takashima, Yuichi Nakamura, Yoji Kajitani
2007 J jnl
A Relocation Method for Circuit Modifications.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Kunihiko Yanagibashi, Yasuhiro Takashima, Yuichi Nakamura
2007 J jnl
Efficient Memory Utilization for High-Speed FPGA-Based Hardware Emulators with SDRAMs.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Kohei Hosokawa, Katsunori Tanaka, Yuichi Nakamura
2006 — conf
A performance-driven circuit bipartitioning algorithm for multi-FPGA implementation with time-multiplexed I/Os.
FPT
Masato Inagi, Yasuhiro Takashima, Yuichi Nakamura, Yoji Kajitani
2006 A* conf
Budgeting-free hierarchical design method for large scale and high-performance LSIs.
DAC
Yuichi Nakamura, Mitsuru Tagata, Takumi Okamoto, Shigeyoshi Tawada, Ko Yoshikawa
2006 J jnl
Domino Logic Synthesis System and its Applications.
J. Circuits Syst. Comput.
Ko Yoshikawa, Shigeto Inui, Yasuhiko Hagihara, Yuichi Nakamura, Takeshi Yoshimura
2006 J jnl
Fast FPGA-Emulation-Based Simulation Environment for Custom Processors.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Yuichi Nakamura, Kohei Hosokawa
2006 J jnl
Hierarchical-Analysis-Based Fast Chip-Scale Power Estimation Method for Large and Complex LSIs.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Yuichi Nakamura, Takeshi Yoshimura
2005 — conf
A fast chip-scale power estimation method for large and complex LSIs based on hierarchical analysis.
ISCAS (1)
Yuichi Nakamura, Takeshi Yoshimura
2005 J jnl
An Engineering Change Orders Design Method Based on Patchwork-Like Partitioning for High Performance LSIs.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Yuichi Nakamura, Ko Yoshikawa, Takeshi Yoshimura
2004 A* conf
A fast hardware/software co-verification method for system-on-a-chip by using a C/C++ simulator and FPGA emulator with shared register communication.
DAC
Yuichi Nakamura, Kohei Hosokawa, Ichiro Kuroda, Ko Yoshikawa, Takeshi Yoshimura
2004 — conf
Timing optimization by replacing flip-flops to latches.
ASP-DAC
Ko Yoshikawa, Yasuhiko Hagihara, Keisuke Kanamaru, Yuichi Nakamura, Shigeto Inui, Takeshi Yoshimura
1997 — conf
A hardware/software co-simulation environment for micro-processor design with HDL simulator and OS interface.
ASP-DAC
Yoshiyuki Ito, Yuichi Nakamura
1995 A* conf
A Partitioning-Based Logic Optimization Method for Large Scale Circuits with Boolean Matrix.
DAC
Yuichi Nakamura, Takeshi Yoshimura
1995 A* conf
Multi-Level Logic Minimization Based on Multi-Signal Implications.
DAC
Masayuki Yuguchi, Yuichi Nakamura, Kazutoshi Wakabayashi, Tomoyuki Fujita