Yufeng Xie - RankMe

20 papers C 4Journal 10Unranked 6

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	A 40-nm Training-Inference STT-MRAM Near-Memory Computing Macro for Memory-Augmented Neural Network Acceleration. IEEE Trans. Very Large Scale Integr. Syst. Shengchao Zhou, Yifan Wang, Hongrui Meng, Yajun Wu, Zizhao Ma, Teng Zou, Tai Min, Shaohao Wang, Yufeng Xie
2025	C	`conf`	A 40nm STT-MRAM Near-Memory Computing Macro for Memory-Augmented Neural Network Acceleration. ISCAS Hongrui Meng, Yajun Wu, Shengchao Zhou, Zizhao Ma, Tai Min, Shaohao Wang, Yufeng Xie
2025	C	`conf`	High sensing margin and parallelism 6T-2MTJ SOT-MRAM based TCAM for energy-Efficient Similarity Priority calculation in MANNs. ISCAS Shengchao Zhou, Teng Zou, Zeming Wang, Xianwu Hu, Hongrui Meng, Yajun Wu, Chuxin Zhang, Caihua Wan, Yufeng Xie
2025	J	`jnl`	Yield Diagnosis and Tuning for Emerging Semiconductors During Research Stage. IEEE Access Chunshan Wang, Zizhao Ma, Yuxuan Zhu, Chensheng Jin, Dongyu Chen, Chuxin Zhang, Yining Chen, Wenzhong Bao, Yufeng Xie
2024	J	`jnl`	Contactless Diagnosis Method and Unsupervised Learning for Panel-Level Photovoltaic Plant Operation and Maintenance. IEEE Access Yifan Wang, Jianrong Xu, Fei Xu, Long Deng, Chensheng Jin, Wenzhong Bao, Yufeng Xie
2023	C	`conf`	A 40nm 150 TOPS/W High Row-Parallel MRAM Compute-in-Memory Macro with Series 3T1MTJ Bitcell for MAC Operation. ISCAS Zizhao Ma, Xianwu Hu, Yihao Wang, Gan Wen, Xiaoyang Zeng, Yufeng Xie
2023	J	`jnl`	An 8.8 TFLOPS/W Floating-Point RRAM-Based Compute-in-Memory Macro Using Low Latency Triangle-Style Mantissa Multiplication. IEEE Trans. Circuits Syst. II Express Briefs Xianwu Hu, Yu Wang, Zizhao Ma, Gan Wen, Zeming Wang, Zhichao Lu, Yunlong Liu, Yanlei Li, Xingdong Liang, Xiaoyang Zeng, Yufeng Xie
2023	—	`conf`	GCFP-ACIM: A 40nm 4.74TFLOPS/W General Complex Float-Point Analog Compute-in-Memory with Adaptive Power-Saving for HDR Signal Processing Applications. A-SSCC Zizhao Ma, Xianwu Hu, Gan Wen, Yihao Wang, Zeming Wang, Yukai Lin, Yu Wang, Yuhao Guo, Yanlei Li, Xingdong Liang, Xiaoyang Zeng, Yufeng Xie
2022	C	`conf`	A High Area-Efficiency RRAM-Based Strong PUF with Multi-Entropy Source and Configurable Double-Read Process. ISCAS Xianwu Hu, Yu Wang, Jiayun Feng, Zizhao Ma, Xiaoyang Zeng, Yufeng Xie
2021	—	`conf`	A Semi-Floating Gate Transistors In-Memory Computing design with 40.14 TOPS/W for matrix-multiplication with frequently updated weight. ASICON Yukai Lin, Yu Wang, Xianwu Hu, Jiayun Feng, Gan Wen, Xiankui Xiong, Haidong Tian, Yufeng Xie
2021	—	`conf`	An 8Kb 40-nm 2T2MTJ STT-MRAM Design with 2.6ns Access Time and Time-Adjustable Writing Process. ASICON Xianwu Hu, Dongyang Li, Yu Wang, Jiayun Feng, Zizhao Ma, Shaohao Wang, Tai Min, Xiaoyang Zeng, Yufeng Xie
2019	—	`conf`	A digitalized RRAM-based Spiking Neuron Network system with 3-bit weight and unsupervised online learning scheme. ASICON Danqing Wu, Shilin Yan, Haodi Tang, Yu Wang, Jiayun Feng, Xianwu Hu, Jiaxin Cao, Yufeng Xie
2017	J	`jnl`	Dynamic Data-Dependent Reference to Improve Sense Margin and Speed of Magnetoresistive Random Access Memory. IEEE Trans. Circuits Syst. II Express Briefs Xiaoyong Xue, Yarong Fu, Yanqing Zhao, Juan Xu, Jianguo Yang, Yufeng Xie, Yinyin Lin, Ryan Huang, Qingtian Zou, Jingang Wu
2016	J	`jnl`	A Logic Resistive Memory Chip for Embedded Key Storage With Physical Security. IEEE Trans. Circuits Syst. II Express Briefs Yufeng Xie, Xiaoyong Xue, Jianguo Yang, Yinyin Lin, Qingtian Zou, Ryan Huang, Jingang Wu
2013	J	`jnl`	A 0.13 µm 8 Mb Logic-Based Cu IEEE J. Solid State Circuits Xiaoyong Xue, Wenxiang Jian, Jianguo Yang, Fanjie Xiao, Gang Chen, Shuliu Xu, Yufeng Xie, Yinyin Lin, Ryan Huang, Qingtian Zou, Jingang Wu
2012	J	`jnl`	64Kb logic RRAM chip resisting physical and side-channel attacks for encryption keys storage. IEICE Electron. Express Yufeng Xie, Wenxiang Jian, Xiaoyong Xue, Gang Jin, Yinyin Lin
2011	—	`conf`	A BIST scheme for high-speed Gain Cell eDRAM. ASICON Bing Yan, Yufeng Xie, Rui Yuan, Yinyin Lin
2011	J	`jnl`	Novel 2T programmable element to improve density and performance of FPGA. IEICE Electron. Express Xiaoyong Xue, Yufeng Xie, Yinyin Lin
2011	—	`conf`	Novel RRAM programming technology for instant-on and high-security FPGAs. ASICON Xiaoyong Xue, Wenxiang Jian, Yufeng Xie, Qing Dong, Rui Yuan, Yinyin Lin
2010	J	`jnl`	A 3D RRAM Using a Stackable Multi-Layer 1TXR Cell. IEICE Trans. Electron. Ji Zhang, Yiqing Ding, Xiaoyong Xue, Gang Jin, Yuxin Wu, Yufeng Xie, Yinyin Lin