Yufei Ma

52 papers A* 6A 8B 3C 2Journal 19Unranked 13
YearRankTypeTitle / Venue / Authors
2026 — conf
18.2 A 22nm 1.87ms/Frame Streaming Multi-Speaker ASR Accelerator Leveraging Contextual-Aware Redundancy Skipping with 2D-Writable Microscaling Compute-in-Memory and Similarity-Aware TCAM Design.
ISSCC
Wenjie Ren, Mingxuan Li, Zhenghao Jin, Yifan Ding, Ruohuang Xu, Xiangjun Ye, Yufei Ma, Tianyu Jia, Le Ye
2026 J jnl
A 22-nm Residual Spiking Neural Network Chip Based on Sparsity-Adaptive In-Memory Computing and a Spike-Driven Architecture.
IEEE J. Solid State Circuits
Ying Liu, Ninghui Shang, Tianhao Zhao, Peiyu Chen, Tianyu Jia, Zhixuan Wang, Yufei Ma, Le Ye
2026 J jnl
A Full-Stack Framework for GNN Acceleration via Partition-Compiler-Architecture Co-Design.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Yangjie Zhou, Zhihui Zhang, Shuwen Lu, Cong Guo, Jingwen Leng, Feng Zhang, Yufei Ma, Yun Liang, Minyi Guo
2026 J jnl
Quartet: A Digital Compute-in-Memory Versatile AI Accelerator With Heterogeneous Tensor Engines and Off-Chip-Less Dataflow.
IEEE Trans. Circuits Syst. I Regul. Pap.
Yikan Qiu, Guoxiang Li, Meng Wu, Yifan Jia, Le Ye, Yufei Ma
2025 — conf
13.1 A 0.22mm2 161nW Noise-Robust Voice-Activity Detection Using Information-Aware Data Compression and Neuromorphic Spatial-Temporal Feature Extraction.
ISSCC
Ying Liu, Jie Li, Qining Zhang, Tianhao Zhao, Chenhao Shi, Ninghui Shang, Peiyu Chen, Xiaohuan Ge, Yufei Ma, Linxiao Shen, Zhixuan Wang, Ru Huang, Le Ye
2025 A conf
3D-MoE: Accelerating Multi-Expert Activated LLMs on 3D In/Near-Memory Computing Architecture via Hybrid Parallelism.
ICCAD
Xinyu Qu, Zehua Zhang, Runnan Xu, Yufei Ma
2025 A* conf
3D-SubG: A 3D Stacked Hybrid Processing Near/In-Memory Accelerator for Subgraph GNNs.
DAC
Guoxiang Li, Runnan Xu, Ruohang Xu, Yikan Qiu, Renati Tuerhong, Muhan Zhang, Le Ye, Yufei Ma
2025 A* conf
3D-TokSIM: Stacking 3D Memory with Token-Stationary Compute-in-Memory for Speculative LLM Inference.
DAC
Wentao Zhao, Boya Lv, Meng Wu, Peiyu Chen, Fengyun Yan, Yufei Ma, Tianyu Jia, Ru Huang, Le Ye
2025 J jnl
A 22-nm Delta-Sigma Computing-In-Memory SRAM Macro With Near-Zero-Mean Outputs and LSB-First ADCs for Edge AI Processing.
IEEE J. Solid State Circuits
Peiyu Chen, Wentao Zhao, Meng Wu, Linxiao Shen, Tianyu Jia, Ru Huang, Le Ye, Yufei Ma
2025 A* conf
Accelerating Diffusion Transformer via Increment-Calibrated Caching with Channel-Aware Singular Value Decomposition.
CVPR
Zhiyuan Chen, Keyi Li, Yifan Jia, Le Ye, Yufei Ma
2025 J jnl
Accelerating Diffusion Transformer via Increment-Calibrated Caching with Channel-Aware Singular Value Decomposition.
CoRR
Zhiyuan Chen, Keyi Li, Yifan Jia, Le Ye, Yufei Ma
2024 — conf
30.2 A 22nm 0.26nW/Synapse Spike-Driven Spiking Neural Network Processing Unit Using Time-Step-First Dataflow and Sparsity-Adaptive In-Memory Computing.
ISSCC
Ying Liu, Yufei Ma, Ninghui Shang, Tianhao Zhao, Peiyu Chen, Meng Wu, Jiayoon Ru, Tianyu Jia, Le Ye, Zhixuan Wang, Ru Huang
2024 — conf
A Heterogeneous TinyML SoC with Energy-Event-Performance-Aware Management and Compute-in-Memory Two-Stage Event-Driven Wakeup.
VLSI Technology and Circuits
Yanchi Dong, Xueping Liu, Kangbo Bai, Guoxiang Li, Meng Wu, Yiqi Jing, Yihan Zhang, Pixian Zhan, Yadong Zhang, Yufei Ma, Ru Huang, Le Ye, Tianyu Jia
2024 A* conf
AIG-CIM: A Scalable Chiplet Module with Tri-Gear Heterogeneous Compute-in-Memory for Diffusion Acceleration.
DAC
Yiqi Jing, Meng Wu, Jiaqi Zhou, Yiyang Sun, Yufei Ma, Ru Huang, Tianyu Jia, Le Ye
2024 J jnl
Alternating Subspace Approximate Message Passing.
CoRR
Xu Zhu, Yufei Ma, Xiaoguang Li, Tiejun Li
2024 A* conf
An In-Memory Computing Accelerator with Reconfigurable Dataflow for Multi-Scale Vision Transformer with Hybrid Topology.
DAC
Zhiyuan Chen, Yufei Ma, Keyi Li, Yifan Jia, Guoxiang Li, Meng Wu, Tianyu Jia, Le Ye, Ru Huang
2024 J jnl
DCIM-GCN: Digital Computing-in-Memory Accelerator for Graph Convolutional Network.
IEEE Trans. Circuits Syst. I Regul. Pap.
Yufei Ma, Yikan Qiu, Wentao Zhao, Guoxiang Li, Meng Wu, Tianyu Jia, Le Ye, Ru Huang
2024 — conf
Quartet: A 22nm 0.09mJ/lnference Digital Compute-in-Memory Versatile AI Accelerator with Heterogeneous Tensor Engines and Off-Chip-Less Dataflow.
CICC
Yikan Qiu, Yufei Ma, Meng Wu, Yifan Jia, Xinyu Qu, Zecheng Zhou, Jincheng Lou, Tianyu Jia, Le Ye, Ru Huang
2024 — conf
S2D-CIM: A 22nm 128Kb Systolic Digital Compute-in-Memory Macro with Domino Data Path for Flexible Vector Operation and 2-D Weight Update in Edge AI Applications.
CICC
Meng Wu, Wenjie Ren, Peiyu Chen, Wentao Zhao, Yiqi Jing, Jiayoon Ru, Zhixuan Wang, Yufei Ma, Ru Huang, Tianyu Jia, Le Ye
2024 J jnl
Sparsity-Aware In-Memory Neuromorphic Computing Unit With Configurable Topology of Hybrid Spiking and Artificial Neural Network.
IEEE Trans. Circuits Syst. I Regul. Pap.
Ying Liu, Zhiyuan Chen, Wentao Zhao, Tianhao Zhao, Tianyu Jia, Zhixuan Wang, Ru Huang, Le Ye, Yufei Ma
2023 — conf
A 22nm Delta-Sigma Computing-In-Memory (Δ∑CIM) SRAM Macro with Near-Zero-Mean Outputs and LSB-First ADCs Achieving 21.38TOPS/W for 8b-MAC Edge AI Processing.
ISSCC
Peiyu Chen, Meng Wu, Wentao Zhao, Jiajia Cui, Zhixuan Wang, Yadong Zhang, Qijun Wang, Jiayoon Ru, Linxiao Shen, Tianyu Jia, Yufei Ma, Le Ye, Ru Huang
2023 — conf
A A 22nm 0.43pJ/SOP Sparsity-Aware In-Memory Neuromorphic Computing System with Hybrid Spiking and Artificial Neural Network and Configurable Topology.
CICC
Ying Liu, Zhiyuan Chen, Zhixuan Wang, Wentao Zhao, Wei He, Jianfeng Zhu, Oijun Wang, Ning Zhang, Tianyu Jia, Yufei Ma, Le Ye, Ru Huang
2023 A* conf
A Model-Specific End-to-End Design Methodology for Resource-Constrained TinyML Hardware.
DAC
Yanchi Dong, Tianyu Jia, Kaixuan Du, Yiqi Jing, Qijun Wang, Pixian Zhan, Yadong Zhang, Fengyun Yan, Yufei Ma, Yun Liang, Le Ye, Ru Huang
2023 J jnl
An 82-nW 0.53-pJ/SOP Clock-Free Spiking Neural Network With 40-μs Latency for AIoT Wake-Up Functions Using a Multilevel-Event-Driven Bionic Architecture and Computing-in-Memory Technique.
IEEE Trans. Circuits Syst. I Regul. Pap.
Ying Liu, Yufei Ma, Wei He, Zhixuan Wang, Linxiao Shen, Jiayoon Ru, Ru Huang, Le Ye
2023 A conf
DCIM-3DRec: A 3D Reconstruction Accelerator with Digital Computing-in-Memory and Octree-Based Scheduler.
ISLPED
Yiqi Jing, Yiyang Sun, Xiao Wang, Wentao Zhao, Meng Wu, Fengyun Yan, Yufei Ma, Le Ye, Tianyu Jia
2023 — conf
RIMAC: An Array-Level ADC/DAC-Free ReRAM-Based in-Memory DNN Processor with Analog Cache and Computation.
ASP-DAC
Peiyu Chen, Meng Wu, Yufei Ma, Le Ye, Ru Huang
2023 J jnl
Research progress on low-power artificial intelligence of things (AIoT) chip design.
Sci. China Inf. Sci.
Le Ye, Zhixuan Wang, Tianyu Jia, Yufei Ma, Linxiao Shen, Yihan Zhang, Heyi Li, Peiyu Chen, Meng Wu, Ying Liu, Yiqi Jing, Hao Zhang, Ru Huang
2022 J jnl
A Flexible and Efficient FPGA Accelerator for Various Large-Scale and Lightweight CNNs.
IEEE Trans. Circuits Syst. I Regul. Pap.
Xiao Wu, Yufei Ma, Meiqi Wang, Zhongfeng Wang
2022 A conf
DCIM-GCN: Digital Computing-in-Memory to Efficiently Accelerate Graph Convolutional Networks.
ICCAD
Yikan Qiu, Yufei Ma, Wentao Zhao, Meng Wu, Le Ye, Ru Huang
2022 J jnl
Hybrid Stochastic-Binary Computing for Low-Latency and High-Precision Inference of CNNs.
IEEE Trans. Circuits Syst. I Regul. Pap.
Zhiyuan Chen, Yufei Ma, Zhongfeng Wang
2021 A conf
SWIFT: Small-World-based Structural Pruning to Accelerate DNN Inference on FPGA.
FPGA
Yufei Ma, Gokul Krishnan, Yu Cao, Le Ye, Ru Huang
2020 — conf
An Efficient FPGA Accelerator Optimized for High Throughput Sparse CNN Inference.
APCCAS
Jiayu Wen, Yufei Ma, Zhongfeng Wang
2020 J jnl
Automatic Compilation of Diverse CNNs Onto High-Performance FPGA Accelerators.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Yufei Ma, Yu Cao, Sarma B. K. Vrudhula, Jae-sun Seo
2020 — conf
Efficient Hardware Post Processing of Anchor-Based Object Detection on FPGA.
ISVLSI
Hui Zhang, Wei Wu, Yufei Ma, Zhongfeng Wang
2020 — conf
Efficient Inference of Large-Scale and Lightweight Convolutional Neural Networks on FPGA.
SoCC
Xiao Wu, Yufei Ma, Zhongfeng Wang
2020 — conf
In-Memory Computing: The Next-Generation AI Computing Paradigm.
ACM Great Lakes Symposium on VLSI
Yufei Ma, Yuan Du, Li Du, Jun Lin, Zhongfeng Wang
2020 A conf
Optimizing Stochastic Computing for Low Latency Inference of Convolutional Neural Networks.
ICCAD
Zhiyuan Chen, Yufei Ma, Zhongfeng Wang
2020 J jnl
Performance Modeling for CNN Inference Accelerators on FPGA.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Yufei Ma, Yu Cao, Sarma B. K. Vrudhula, Jae-sun Seo
2019 B conf
Automatic Compiler Based FPGA Accelerator for CNN Training.
FPL
Shreyas Kolala Venkataramanaiah, Yufei Ma, Shihui Yin, Eriko Nurvitadhi, Aravind Dasu, Yu Cao, Jae-sun Seo
2019 J jnl
Automatic Compiler Based FPGA Accelerator for CNN Training.
CoRR
Shreyas Kolala Venkataramanaiah, Yufei Ma, Shihui Yin, Eriko Nurvitadhi, Aravind Dasu, Yu Cao, Jae-sun Seo
2019 J jnl
Efficient Network Construction Through Structural Plasticity.
IEEE J. Emerg. Sel. Topics Circuits Syst.
Xiaocong Du, Zheng Li, Yufei Ma, Yu Cao
2019 J jnl
Efficient Network Construction through Structural Plasticity.
CoRR
Xiaocong Du, Zheng Li, Yufei Ma, Yu Cao
2018 J jnl
ALAMO: FPGA acceleration of deep learning algorithms with a modularized RTL compiler.
Integr.
Yufei Ma, Naveen Suda, Yu Cao, Sarma B. K. Vrudhula, Jae-sun Seo
2018 A conf
Algorithm-hardware co-design of single shot detector for fast object detection on FPGAs.
ICCAD
Yufei Ma, Tu Zheng, Yu Cao, Sarma B. K. Vrudhula, Jae-sun Seo
2018 — —
Hardware Acceleration of Deep Convolutional Neural Networks on FPGA.
Yufei Ma
2018 J jnl
Optimizing the Convolution Operation to Accelerate Deep Neural Networks on FPGA.
IEEE Trans. Very Large Scale Integr. Syst.
Yufei Ma, Yu Cao, Sarma B. K. Vrudhula, Jae-sun Seo
2017 B conf
An automatic RTL compiler for high-throughput FPGA implementation of diverse deep convolutional neural networks.
FPL
Yufei Ma, Yu Cao, Sarma B. K. Vrudhula, Jae-sun Seo
2017 C conf
End-to-end scalable FPGA accelerator for deep residual networks.
ISCAS
Yufei Ma, Minkyu Kim, Yu Cao, Sarma B. K. Vrudhula, Jae-sun Seo
2017 A conf
Optimizing Loop Operation and Dataflow in FPGA Acceleration of Deep Convolutional Neural Networks.
FPGA
Yufei Ma, Yu Cao, Sarma B. K. Vrudhula, Jae-sun Seo
2016 B conf
Scalable and modularized RTL compilation of Convolutional Neural Networks onto FPGA.
FPL
Yufei Ma, Naveen Suda, Yu Cao, Jae-sun Seo, Sarma B. K. Vrudhula
2016 A conf
Throughput-Optimized OpenCL-based FPGA Accelerator for Large-Scale Convolutional Neural Networks.
FPGA
Naveen Suda, Vikas Chandra, Ganesh Dasika, Abinash Mohanty, Yufei Ma, Sarma B. K. Vrudhula, Jae-sun Seo, Yu Cao
2015 C conf
Energy-efficient reconstruction of compressively sensed bioelectrical signals with stochastic computing circuits.
ICCD
Yufei Ma, Minkyu Kim, Yu Cao, Jae-sun Seo, Sarma B. K. Vrudhula