Yuekang Guo

35 papers C 7Journal 17Unranked 11
YearRankTypeTitle / Venue / Authors
2026 J jnl
A 14-bit 1.4 GS/s current-steering DAC with square-dithered frequency-modulated DEM achieving >60-dBc SFDR in 180 nm CMOS.
Microelectron. J.
Qiang Pan, Yitao Wang, Jiayi Chen, Yuekang Guo, Jing Jin, Jianjun Zhou
2026 J jnl
A 3-5 V to Sub-1 V DLDO-SC-Sigma Converter With Auxiliary Loop for Efficiency Improvement in High-Density Power Delivery.
IEEE J. Solid State Circuits
Yuxiang Li, Jing Jin, Yuekang Guo, Jianjun Zhou, Junmin Jiang
2026 J jnl
A 40-nm CMOS Phase-Tunable Four-Phase Injection-Locked Ring VCO Utilizing Unbalanced Feedforward Topology Achieving -211.1- to -207.3-dBc/Hz FoM
IEEE J. Solid State Circuits
Huzhi Tang, Yuekang Guo, Jing Jin, Xiaoming Liu, Yi Liu, Zhongyuan Chang, Howard C. Yang, Jianjun Zhou
2026 — conf
A 5-to-1V DLDO-Hybrid-Sigma Converter Achieving Fast Transient for High-Density Power Delivery.
ASP-DAC
Zizhe Huang, Yuxiang Li, Yuekang Guo, Jing Jin, Jianjun Zhou, Junmin Jiang
2025 J jnl
A 14-bit 2.6GS/s RF sampling pipelined ADC in 28nm CMOS.
Microelectron. J.
Hui Zhang, Dawei Dong, Haijun Wang, Dan Li, Yuan Gao, Chaoyi Hu, Hao Xu, Xinlei Song, Jing Jin, Yuekang Guo, Lin Cheng
2025 J jnl
A 25 MHz-BW 81 dB-DR TDC-Based CTDSM With Background Analog-Integration-Based ISI Error Calibration Achieving >8 dB Even-Order Harmonic Suppression.
IEEE Trans. Circuits Syst. I Regul. Pap.
Tao Zhong, Yuekang Guo, Jianjun Zhou, Hui Zhang, Jing Jin
2025 J jnl
A 470 μW 20 kHz-BW 107.3 dB-SNDR Nested CT DSM Using Negative-R-Based Cross-RC Integrator and Weighted Multi-Threshold MSB-Pass Quantizer.
IEEE Trans. Circuits Syst. I Regul. Pap.
Jing Jin, Meng Xu, Yuekang Guo, Xiaoming Liu, Nan Sun, Jianjun Zhou
2025 J jnl
A 78.1 dB SNDR 10 MHz-BW continuous-time noise-shaping SAR ADC in 28 nm CMOS.
Microelectron. J.
Hui Zhang, Yong Li, Dawei Dong, Danben He, Yuan Gao, Jing Jin, Yuekang Guo, Lei Qiu, Zhenrong Li, Lin Cheng
2025 J jnl
A Fully Symmetric Oscillator-Based CMOS Ising Machine Architecture With Successive Approximation Sampling and Power Efficient Solution Refinement.
IEEE Trans. Circuits Syst. I Regul. Pap.
Ke Wu, Yuekang Guo, Xiaoming Liu, Zhongyuan Chang, Howard C. Yang, Jing Jin, Jianjun Zhou
2025 J jnl
A two-phase oscillation scheme with direct background correction for VCO-based ADC.
Microelectron. J.
Tao Zhong, Yuekang Guo, Jing Jin, Jianjun Zhou
2025 C conf
A1-GS/s 7-bit 3-then-1 bit/cycle SAR ADC with A Reconfigurable Reference-Embedded Comparator.
ISCAS
Jinwei Wu, Yuekang Guo, Meng Xu, Lingyan Fan, Jing Jin, Jianjun Zhou
2025 C conf
An EF-CIFF Noise-Shaping SAR ADC with A Joint Dynamic Amplifier, Comparator and Lossless Passive Summer Structure.
ISCAS
Yuzhi Ai, Yuekang Guo, Zhengyuan Lou, Hui Zhang, Jing Jin, Jianjun Zhou
2024 J jnl
A 0.83-pJ/b 20-Gb/s/Pin Single-Ended Transceiver With AC/DC-Coupled Pre-Emphasis FFE and Edge-Dependent Phase-Modulation DFE for Low-Power Memory Controllers.
IEEE Trans. Circuits Syst. I Regul. Pap.
Xiaofei Wang, Jing Jin, Xiaoming Liu, Hui Wang, Huzhi Tang, Chao Yang, Yuekang Guo, Tingting Mo, Jianjun Zhou
2024 — conf
A 470μW 20kHz-BW 107.3dB-SNDR Nested CT DSM Employing Negative-R-Based Cross-RC Filter and Weighted Multi-Threshold MSB-Pass Quantizer.
CICC
Jing Jin, Yuekang Guo, Meng Xu, Xiaoming Liu, Nan Sun, Jianjun Zhou
2024 C conf
A Self-Calibrated Sampling Noise Cancellation Technique for Noise-Shaping SAR ADC.
ISCAS
Zhengyuan Lou, Meng Xu, Yuekang Guo, Jing Jin, Jianjun Zhou
2023 J jnl
A 372 μW 10 kHz-BW 109.2 dB-SNDR Nested Delta-Sigma Modulator Using Hysteresis-Comparison MSB-Pass Quantization.
IEEE J. Solid State Circuits
Yuekang Guo, Jing Jin, Xiaoming Liu, Jianjun Zhou
2023 J jnl
A 60-MS/s 5-MHz BW Noise-Shaping SAR ADC With Integrated Input Buffer Achieving 84.2-dB SNDR and 97.3-dB SFDR Using Dynamic Level-Shifting and ISI-Error Correction.
IEEE J. Solid State Circuits
Yuekang Guo, Jing Jin, Xiaoming Liu, Jianjun Zhou
2023 — conf
A Fully Synthesizable Dynamic Voltage Comparator with Time-Domain Offset Calibration.
MWSCAS
Shunyan Wang, Yuekang Guo, Qiang Pan, Xiaoming Liu, Shan Wang, Jing Jin
2023 C conf
A LUT-based Background Linearization Technique for VCO-based ADC Employing $K_{\text{VCO}}-\text{Locked}-\text{Loop}$.
ISCAS
Yuekang Guo, Jing Jin, Xiaoming Liu, Zhaolin Yang, Jianjun Zhou
2023 — conf
A Non-Linearity Digital Background Calibration Algorithm with Piece-Wise Linear Functions.
MWSCAS
Ke Wu, Yuekang Guo, Xiaoming Liu, Jing Jin, Howard C. Yang, Jianjun Zhou
2022 C conf
A 3bit/cycle 1GS/s 8-bit SAR ADC Employing Asynchronous Ping-Pong Quantization Scheme.
ISCAS
Yuekang Guo, Xiaoming Liu, Jing Jin, Jianjun Zhou
2022 J jnl
A Fast-Settling Phase-Locked Loop Utilizing Cycle-Slipping-Elimination PFDCP.
IEEE Trans. Circuits Syst. II Express Briefs
Chao Yang, Xiaoming Liu, Jing Jin, Yuekang Guo, Jianjun Zhou
2022 J jnl
A Harmonic Rejecting N-Path Filter with Harmonic Gain Calibration Technique.
Circuits Syst. Signal Process.
Ran Bu, Jing Jin, Zhaolin Yang, Yuekang Guo, Jianjun Zhou
2022 — conf
A Power-Efficient CMOS Image Sensor with In-Sensor Processing and In-Pixel Gain Calibration.
MWSCAS
Ke Wu, Yuekang Guo, Jing Jin, Xiaoming Liu, Jianjun Zhou
2022 J jnl
An 18.1 mW 50 MHz-BW 76.4 dB-SNDR CTSDM With PVT-Robust VCO Quantizer and Latency-Free Background-Calibrated DAC.
IEEE Trans. Circuits Syst. I Regul. Pap.
Yuekang Guo, Jing Jin, Xiaoming Liu, Jianjun Zhou
2021 — conf
A Center Frequency Calibration Technique for Ring VCO Exploiting Delay
MWSCAS
Yuekang Guo, Qiang Pan, Xiaoming Liu, Jing Jin
2021 — conf
A Latency-Optimized Lookup Table for Nonlinearity Calibration in VCO-Based Sigma-Delta ADCs.
MWSCAS
Yanlin He, Yuekang Guo, Jing Jin, Jianjun Zhou
2021 — conf
A Linearization Technique for Ring VCO Exploiting Bulk-Modulation.
MWSCAS
Qiang Pan, Yuekang Guo, Jing Jin, Jianjun Zhou
2021 — conf
A Low Power PVT Stabilization Technique for Dynamic Amplifier in Pipelined SAR ADC.
MWSCAS
Yuekang Guo, Jing Jin, Jianjun Zhou
2021 C conf
A Phase Domain Excess Loop Delay Compensation Technique with Latency Optimized Phase Selector for VCO-Based Continuous-Time ΔΣ ADC.
ISCAS
Yuekang Guo, Jing Jin, Xiaoming Liu, Jianjun Zhou
2021 J jnl
A Power-Efficient SAR ADC with Optimized Timing-Redistribution Asynchronous SAR Logic in 40-nm CMOS.
Circuits Syst. Signal Process.
Mengying Hu, Jing Jin, Yuekang Guo, Xiaoming Liu, Jianjun Zhou
2021 — conf
Analysis of SAR ADC Quantization Error and Nonlinearity in PMCW Automotive Radar.
ASICON
Tao Zhong, Yuekang Guo, Jing Jin
2020 C conf
A Low Power Temperature-Compensated Common-Mode Voltage Detector for Dynamic Amplifiers.
ISCAS
Ran Wang, Yuekang Guo, Jing Jin, Xiaoming Liu, Naifeng Jing, Jianjun Zhou
2020 J jnl
An Inverter-Based Continuous Time Sigma Delta ADC With Latency-Free DAC Calibration.
IEEE Trans. Circuits Syst.
Yuekang Guo, Jing Jin, Xiaoming Liu, Jianjun Zhou
2019 — conf
A Low-Power 10-bit 160-MSample/s DAC in 40-nm CMOS for Baseband Wireless Transmitter.
ASICON
Yifei Wang, Xiaofei Wang, Yuekang Guo, Ting Jin