Yuefeng Cao

19 papers C 3Journal 5Unranked 11
YearRankTypeTitle / Venue / Authors
2025 J jnl
A Multi-Step ADC With Lightweight Input Buffer Distortion, Sub-Stage Coarse-Fine Gain, and Sampling Skew Background Calibrations.
IEEE Trans. Circuits Syst. I Regul. Pap.
Xianghui Pan, Buhui Rui, Yuefeng Cao, Rui Paulo Martins, Yan Zhu, Chi-Hang Chan
2025 J jnl
A Single-Channel 12-b 2-GS/s PVT-Robust Pipelined ADC With Sturdy Ring Amplifier and Time-Domain Quantizer.
IEEE J. Solid State Circuits
Yuefeng Cao, Minglei Zhang, Yan Zhu, Rui Paulo Martins, Chi-Hang Chan
2025 J jnl
Soft Classification in a Composite Source Model.
Entropy
Yuefeng Cao, Jiakun Liu, Wenyi Zhang
2024 — conf
22.1 A 12GS/s 12b 4× Time-Interleaved Pipelined ADC with Comprehensive Calibration of TI Errors and Linearized Input Buffer.
ISSCC
Yuefeng Cao, Minglei Zhang, Yan Zhu, Rui Paulo Martins, Chi-Hang Chan
2024 J jnl
A 12-GS/s 12-b 4× Time-Interleaved ADC Using Input-Independent Timing Skew Calibration With Global Dither Injection and Linearized Input Buffer.
IEEE J. Solid State Circuits
Yuefeng Cao, Minglei Zhang, Yan Zhu, Rui Paulo Martins, Chi-Hang Chan
2024 — conf
The Race for the Extra Pico Second without Losing the Decibel: A Partial-Review of Single-Channel Energy-Efficient High-Speed Nyquist ADCs.
CICC
Chi-Hang Chan, Minglei Zhang, Yuefeng Cao, Honazhi Zhao, Rui Paulo Martins, Yan Zhu
2023 — conf
A 12b 1GS/s ADC with Lightweight Input Buffer Distortion Background Calibration Achieving >75dB SFDR over PVT.
CICC
Xiang-Hui Pan, Buhui Rui, Yuefeng Cao, Yan Zhu, Chi-Hang Chan, Rui Paulo Martins
2023 — conf
A 79.5dB-SNDR Pipelined-SAR ADC with a Linearity-Shifting 32× Dynamic Amplifier and Mounted-Over-Die Bypass Capacitors.
VLSI Technology and Circuits
Minglei Zhang, Yuefeng Cao, Yan Zhu, Chi-Hang Chan, Rui Paulo Martins
2023 — conf
A Single-Channel 12b 2GS/s PVT-Robust Pipelined ADC with Critically Damped Ring Amplifier and Time-Domain Quantizer.
ISSCC
Yuefeng Cao, Minglei Zhang, Yan Zhu, Chi-Hang Chan, Rui Paulo Martins
2021 J jnl
A 91.0-dB SFDR Single-Coarse Dual-Fine Pipelined-SAR ADC With Split-Based Background Calibration in 28-nm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap.
Yuefeng Cao, Shumin Zhang, Tianli Zhang, Yongzhen Chen, Yutong Zhao, Chixiao Chen, Fan Ye, Junyan Ren
2019 — conf
A 10b 250MS/s SAR ADC with Speed-Enhanced SAR Logic and Free Time More Than a Half of Sampling Period.
ASICON
Shumin Zhang, Yuefeng Cao, Fan Ye, Junyan Ren
2019 — conf
Machine Learning Based Prior-Knowledge-Free Calibration for Split Pipelined-SAR ADCs with Open-Loop Amplifiers Achieving 93.7-dB SFDR.
ESSCIRC
Tianli Zhang, Yuefeng Cao, Shumin Zhang, Chixiao Chen, Fan Ye, Junyan Ren
2018 C conf
A 800 MS/s, 12-Bit, Ringamp-Based SAR assisted Pipeline ADC with Gain Error Cancellation.
ISCAS
Yongzhen Chen, Zhekan Ni, Yuefeng Cao, Fan Ye, Junyan Ren
2018 — conf
An 11b 80MS/s SAR ADC With Speed-Enhanced SAR Logic and High-Linearity CDAC.
APCCAS
Yuefeng Cao, Yongzhen Chen, Zhekan Ni, Fan Ye, Junyan Ren
2018 C conf
An Operational Amplifier Assisted Input Buffer and An Improved Bootstrapped Switch for High-Speed and High-Resolution ADCs.
ISCAS
Yuefeng Cao, Tianli Zhang, Yongzhen Chen, Fan Ye, Junyan Ren
2018 C conf
Use Multilayer Perceptron in Calibrating Multistage Non-linearity of Split Pipelined-ADC.
ISCAS
Tianli Zhang, Yuefeng Cao, Fan Ye, Junyan Ren
2017 — conf
A proved dither-injection method for memory effect in double sampling pipelined ADC.
ASICON
Fubiao Cao, Yongzhen Chen, Yuefeng Cao, Fan Ye, Junyan Ren
2017 — conf
An improved ring amplifier with process- and supply voltage-insensitive dead-zone.
MWSCAS
Yuefeng Cao, Yongzhen Chen, Tianli Zhang, Fan Ye, Junyan Ren
2016 — conf
Bad Data Identification Based on Optimized Local Outlier Detection Algorithm.
GRMSE (1)
Jingxian Qi, Yuefeng Cao, Jianhua Shi