Yue Zhang

68 papers A* 1A 5C 4Journal 41Unranked 17
YearRankTypeTitle / Venue / Authors
2026 J jnl
A multi-population co-evolutionary algorithm based on dual-space division for dynamic multi-objective optimization problems.
Inf. Sci.
Yaru Hu, Jiaru Xia, Junwei Ou, Yanjie Song, Jun Li, Jinhua Zheng, Gaige Wang, Yue Zhang
2026 J jnl
An Evolutionary Algorithm With Memory Guidance for Data Transmission Scheduling Optimization in Communication Satellite Network.
IEEE Trans. Syst. Man Cybern. Syst.
Yingying Ren, Qiuli Li, Yue Zhang, Jiting Li, Witold Pedrycz, Ponnuthurai Nagaratnam Suganthan, Rammohan Mallipeddi, Yanjie Song
2026 J jnl
Closed-Loop CBRAM Crossbar System Toward Hardware Acceleration of Quantum Algorithms.
IEEE Trans. Circuits Syst. I Regul. Pap.
Iosif-Angelos Fyrigos, Theodoros Panagiotis Chatzinikolaou, Konstantinos Rallis, Vasileios G. Ntinas, Panagiotis Bousoulas, Dimitris Tsoukalas, Panagiotis Dimitrakis, Yue Zhang, Georgios Ch. Sirakoulis
2025 J jnl
A 32 kb 55 nm Radiation-Hardened SRAM Chip With SEU ≤1.1 E-11 Upsets/Bit-Day, SEL >107.1 MeV ⋅ cm²/mg, and TID >100 Krad(Si) for Space Applications.
IEEE Trans. Circuits Syst. I Regul. Pap.
Deming Zhang, Jiaxin Yang, Dingyi Luo, Jianpeng Zhang, Lang Zeng, Bi Wang, Yue Zhang, Weisheng Zhao
2025 J jnl
A Heterogeneous System With Computing in Memory Processing Elements to Accelerate CNN Inference.
IEEE Trans. Circuits Syst. I Regul. Pap.
Jinkai Wang, Youxiang Chen, Zekun Wang, Zhengkun Gu, Bojun Zhang, Haiming Qiu, Kun Zhang, Weisheng Zhao, Yue Zhang
2025 J jnl
A High-Speed, Low-Power, High-Reliability and Fully Single Event Double Node Upset Tolerant Design for Magnetic Random Access Memory.
IEEE Trans. Circuits Syst. I Regul. Pap.
Jiaxin Yang, Ziyang Guo, Shixuan Wang, Jilong Liu, Yue Zhang, Weisheng Zhao, Lang Zeng, Deming Zhang
2025 J jnl
An evolutionary task scheduling algorithm using fuzzy fitness evaluation method for communication satellite network.
Swarm Evol. Comput.
Xuemei Jiang, Yangyang Guo, Yue Zhang, Yanjie Song, Witold Pedrycz, Lining Xing
2025 J jnl
Dynamic Challenge Cross-Selection Physical Unclonable Function Based on MRAM.
IEEE Trans. Very Large Scale Integr. Syst.
Siying Wu, Yu Gong, Jiaao Dai, Da Song, Shouzhong Peng, Yue Zhang, You Wang, Weiqiang Liu
2025 A conf
HRAMTran: A Hybrid-RAM Transformer Accelerator With Dynamic Sparsity Floating-Point CIM and Written-Back Transpose Array.
ICCAD
Bojun Zhang, Jinkai Wang, Xianan Zhu, Ziyuan Guo, Zhengkun Gu, Kaili Zhang, Zhizhong Zhang, Kun Zhang, Weisheng Zhao, Yue Zhang
2025 J jnl
Predictive control for operation and maintenance in smart manufacturing systems with multiple operating modes.
Comput. Ind. Eng.
Yue Zhang, Qiang Feng, Dongming Fan, Yi Ren, Yanjie Song, Meng Liu, Zili Wang
2024 J jnl
A Charge-Domain Compute-In-Memory Macro With Cell-Embedded DA Conversion and Two-Stage AD Conversion for Bit-Scalable MAC Operation.
IEEE Trans. Circuits Syst. II Express Briefs
Kaili Zhang, Zhongzhen Tong, XinXin Liang, Chengzhi Wang, You Wang, Yue Zhang, Weisheng Zhao, Lang Zeng, Deming Zhang
2024 — conf
A Novel Radiation-Hardened Non-volatile Magnetic Latch Circuit.
NVMTS
Jiaxin Yang, Jilong Liu, Lang Zeng, Yue Zhang, Weisheng Zhao, Deming Zhang
2024 J jnl
A Novel Search-Based Compute-in-Memory Minimum Values Generation Scheme for Low-Complexity LDPC Min-Sum Decoding.
IEEE Trans. Circuits Syst. II Express Briefs
Zhipeng Guo, Deming Zhang, Kaili Zhang, Mingyang Song, Yue Zhang, Lang Zeng
2024 J jnl
A reinforcement learning-based evolutionary algorithm for the unmanned aerial vehicles maritime search and rescue path planning problem considering multiple rescue centers.
Memetic Comput.
Haowen Zhan, Yue Zhang, Jingbo Huang, Yanjie Song, Lining Xing, Jie Wu, Zengyun Gao
2024 J jnl
APIM: An Antiferromagnetic MRAM-Based Processing-In-Memory System for Efficient Bit-Level Operations of Quantized Convolutional Neural Networks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Yueting Li, Jinkai Wang, Daoqian Zhu, Jinhao Li, Ao Du, Xueyan Wang, Yue Zhang, Weisheng Zhao
2024 J jnl
Data-driven dynamic pricing and inventory management of an omni-channel retailer in an uncertain demand environment.
Expert Syst. Appl.
Shiyu Liu, Jun Wang, Rui Wang, Yue Zhang, Yanjie Song, Lining Xing
2024 J jnl
Energy-Efficient Satellite Range Scheduling Using a Reinforcement Learning-Based Memetic Algorithm.
IEEE Trans. Aerosp. Electron. Syst.
Yanjie Song, Ponnuthurai Nagaratnam Suganthan, Witold Pedrycz, Ran Yan, Dongming Fan, Yue Zhang
2024 A* conf
FRM-CIM: Full-Digital Recursive MAC Computing in Memory System Based on MRAM for Neural Network Applications.
DAC
Jinkai Wang, Zekun Wang, Bojun Zhang, Zhengkun Gu, Youxiang Chen, Weisheng Zhao, Yue Zhang
2024 J jnl
Generalized Model and Deep Reinforcement Learning-Based Evolutionary Method for Multitype Satellite Observation Scheduling.
IEEE Trans. Syst. Man Cybern. Syst.
Yanjie Song, Junwei Ou, Witold Pedrycz, Ponnuthurai Nagaratnam Suganthan, Xinwei Wang, Lining Xing, Yue Zhang
2024 J jnl
RSACIM: Resistance Summation Analog Computing in Memory With Accuracy Optimization Scheme Based on MRAM.
IEEE Trans. Circuits Syst. I Regul. Pap.
Jinkai Wang, Zhengkun Gu, Bojun Zhang, Youxiang Chen, Zekun Wang, Kun Zhang, Youguang Zhang, Yue Zhang
2024 J jnl
Reinforcement learning-assisted evolutionary algorithm: A survey and research opportunities.
Swarm Evol. Comput.
Yanjie Song, Yutong Wu, Yangyang Guo, Ran Yan, Ponnuthurai Nagaratnam Suganthan, Yue Zhang, Witold Pedrycz, Swagatam Das, Rammohan Mallipeddi, Oladayo Solomon Ajani, Qiang Feng
2023 J jnl
A Novel 9T1C-SRAM Compute-In-Memory Macro With Count-Less Pulse-Width Modulation Input and ADC-Less Charge-Integration-Count Output.
IEEE Trans. Circuits Syst. I Regul. Pap.
Kaili Zhang, Deming Zhang, Mingyang Song, Zhipeng Guo, You Wang, Chengzhi Wang, Yue Zhang, Lang Zeng
2023 J jnl
Optimization of maritime support network with relays under uncertainty: A novel matheuristics method.
Reliab. Eng. Syst. Saf.
Yue Zhang, Qiang Feng, Dongming Fan, Yi Ren, Bo Sun, Dezhen Yang, Zili Wang
2023 J jnl
Reinforcement Learning-assisted Evolutionary Algorithm: A Survey and Research Opportunities.
CoRR
Yanjie Song, Yutong Wu, Yangyang Guo, Ran Yan, Ponnuthurai N. Suganthan, Yue Zhang, Witold Pedrycz, Yingwu Chen, Swagatam Das, Rammohan Mallipeddi, Oladayo Solomon Ajani
2023 A conf
TAM: A Computing in Memory based on Tandem Array within STT-MRAM for Energy-Efficient Analog MAC Operation.
DATE
Jinkai Wang, Zhengkun Gu, Hongyu Wang, Zuolei Hao, Bojun Zhang, Weisheng Zhao, Yue Zhang
2022 J jnl
Memristor Crossbar Arrays Performing Quantum Algorithms.
IEEE Trans. Circuits Syst. I Regul. Pap.
Iosif-Angelos Fyrigos, Vasileios G. Ntinas, Nikolaos Vasileiadis, Georgios Ch. Sirakoulis, Panagiotis Dimitrakis, Yue Zhang, Ioannis G. Karafyllidis
2022 J jnl
Reconfigurable Bit-Serial Operation Using Toggle SOT-MRAM for High-Performance Computing in Memory Architecture.
IEEE Trans. Circuits Syst. I Regul. Pap.
Jinkai Wang, Yining Bai, Hongyu Wang, Zuolei Hao, Guanda Wang, Kun Zhang, Youguang Zhang, Weifeng Lv, Yue Zhang
2021 — conf
A Computing-in-memory Scheme with Series Bit-cell in STT-MRAM for Efficient Multi-bit Analog Multiplication.
NANOARCH
Zuolei Hao, Yue Zhang, Jinkai Wang, Hongyu Wang, Yining Bai, Guanda Wang, Weisheng Zhao
2021 J jnl
Time-Domain Computing in Memory Using Spintronics for Energy-Efficient Convolutional Neural Network.
IEEE Trans. Circuits Syst. I Regul. Pap.
Yue Zhang, Jinkai Wang, Chenyu Lian, Yining Bai, Guanda Wang, Zhizhong Zhang, Zhenyi Zheng, Lei Chen, Kun Zhang, Georgios Ch. Sirakoulis, Youguang Zhang
2020 J jnl
A Diode-Enhanced Scheme for Giant Magnetoresistance Amplification and Reconfigurable Logic.
IEEE Access
Jiang Nan, Kun Zhang, Yue Zhang, Shaohua Yan, Zhizhong Zhang, Zhenyi Zheng, Guanda Wang, Qunwen Leng, Youguang Zhang, Weisheng Zhao
2020 — conf
A Novel In-memory Computing Scheme Based on Toggle Spin Torque MRAM.
ACM Great Lakes Symposium on VLSI
Yining Bai, Yue Zhang, Jinkai Wang, Guanda Wang, Zhizhong Zhang, Zhenyi Zheng, Kun Zhang, Weisheng Zhao
2020 J jnl
A Self-Matching Complementary-Reference Sensing Scheme for High-Speed and Reliable Toggle Spin Torque MRAM.
IEEE Trans. Circuits Syst.
Jinkai Wang, Chenyu Lian, Yining Bai, Guanda Wang, Zhizhong Zhang, Zhenyi Zheng, Lei Chen, Kelian Lin, Kun Zhang, Youguang Zhang, Xiulong Wu, Sorin Cotofana, Yue Zhang
2020 — conf
An In-memory Highly Reconfigurable Logic Circuit Based on Diode-assisted Enhanced Magnetoresistance Device.
ACM Great Lakes Symposium on VLSI
Zhe Huang, Yue Zhang, Kun Zhang, Zhizhong Zhang, Jinkai Wang, Youguang Zhang, Weisheng Zhao
2020 C conf
Efficient Time-Domain In-Memory Computing Based on TST-MRAM.
ISCAS
Jinkai Wang, Yue Zhang, Chenyu Lian, Yining Bai, Zhe Huang, Guanda Wang, Kun Zhang, Youguang Zhang, Weisheng Zhao
2019 — conf
High speed and reliable Sensing Scheme with Three Voltages for STT-MRAM.
NANOARCH
Jinkai Wang, Yue Zhang, Chenyu Lian, Guanda Wang, Kun Zhang, Xiulong Wu, Youguang Zhang, Weisheng Zhao
2019 — conf
Shaped Content Addressable Memory Based On Spin Orbit Torque Driven Chiral Domain Wall Motions.
NANOARCH
Yue Zhang, Jiang Nan, Guanda Wang, Xueying Zhang, Youguang Zhang, Weisheng Zhao
2019 — conf
Thermal Stable and Fast Perpendicular Shape Anisotropy Magnetic Tunnel Junction.
NANOARCH
Guanda Wang, Yue Zhang, Zhe Huang, Jinkai Wang, Kun Zhang, Zhizhong Zhang, Youguang Zhang, Weisheng Zhao
2019 J jnl
Ultra-Dense Ring-Shaped Racetrack Memory Cache Design.
IEEE Trans. Circuits Syst. I Regul. Pap.
Guanda Wang, Yue Zhang, Beibei Zhang, Bi Wu, Jiang Nan, Xueying Zhang, Zhizhong Zhang, Jacques-Olivier Klein, Dafine Ravelosona, Zhaohao Wang, Youguang Zhang, Weisheng Zhao
2018 — conf
Design Space Exploration of Magnetic Tunnel Junction based Stochastic Computing in Deep Learning.
ACM Great Lakes Symposium on VLSI
You Wang, Yue Zhang, Youguang Zhang, Weisheng Zhao, Hao Cai, Lirida A. B. Naviner
2017 A conf
A true random number generator based on parallel STT-MTJs.
DATE
Yuanzhuo Qu, Jie Han, Bruce F. Cockburn, Witold Pedrycz, Yue Zhang, Weisheng Zhao
2017 — conf
Compact modeling of high spin transfer torque efficiency double-barrier magnetic tunnel junction.
NANOARCH
Guanda Wang, Yue Zhang, Zhizhong Zhang, Jiang Nan, Zhenyi Zheng, Yu Wang, Lang Zeng, Youguang Zhang, Weisheng Zhao
2016 J jnl
A process-variation-resilient methodology of circuit design by using asymmetrical forward body bias in 28 nm FDSOI.
Microelectron. Reliab.
You Wang, Hao Cai, Lirida A. B. Naviner, Xiaoxuan Zhao, Yue Zhang, Mariem Slimani, Jacques-Olivier Klein, Weisheng Zhao
2016 J jnl
All Spin Artificial Neural Networks Based on Compound Spintronic Synapse and Neuron.
IEEE Trans. Biomed. Circuits Syst.
Deming Zhang, Lang Zeng, Kaihua Cao, Mengxing Wang, Shouzhong Peng, Yue Zhang, Youguang Zhang, Jacques-Olivier Klein, Yu Wang, Weisheng Zhao
2016 J jnl
Perspectives of Racetrack Memory for Large-Capacity On-Chip Memory: From Device to System.
IEEE Trans. Circuits Syst. I Regul. Pap.
Yue Zhang, Chao Zhang, Jiang Nan, Zhizhong Zhang, Xueying Zhang, Jacques-Olivier Klein, Dafine Ravelosona, Guangyu Sun, Weisheng Zhao
2016 — conf
Ultra-low power all spin logic device acceleration based on voltage controlled magnetic anisotropy.
NANOARCH
Zhizhong Zhang, Yue Zhang, Lei Yue, Li Su, Yichuan Shi, Youguang Zhang, Weisheng Zhao
2015 J jnl
Compact thermal modeling of spin transfer torque magnetic tunnel junction.
Microelectron. Reliab.
You Wang, Hao Cai, Lirida A. B. Naviner, Yue Zhang, Jacques-Olivier Klein, Weisheng Zhao
2015 A conf
From device to system: cross-layer design exploration of racetrack memory.
DATE
Guangyu Sun, Chao Zhang, Hehe Li, Yue Zhang, Weiqi Zhang, Yizi Gu, Yinan Sun, Jacques-Olivier Klein, Dafine Ravelosona, Yongpan Liu, Weisheng Zhao, Huazhong Yang
2015 C conf
Perspectives of racetrack memory based on current-induced domain wall motion: From device to system.
ISCAS
Yue Zhang, Chao Zhang, Jacques-Olivier Klein, Dafine Ravelosona, Guangyu Sun, Weisheng Zhao
2015 J jnl
Spintronics: Emerging Ultra-Low-Power Circuits and Systems beyond MOS Technology.
ACM J. Emerg. Technol. Comput. Syst.
Wang Kang, Yue Zhang, Zhaohao Wang, Jacques-Olivier Klein, Claude Chappert, Dafine Ravelosona, Gefei Wang, Youguang Zhang, Weisheng Zhao
2015 J jnl
Synchronous 8-bit Non-Volatile Full-Adder based on Spin Transfer Torque Magnetic Tunnel Junction.
IEEE Trans. Circuits Syst. I Regul. Pap.
Erya Deng, Yue Zhang, Wang Kang, Bernard Dieny, Jacques-Olivier Klein, Guillaume Prenat, Weisheng Zhao
2015 J jnl
Tunnel Junction with Perpendicular Magnetic Anisotropy: Status and Challenges.
Micromachines
Mengxing Wang, Yue Zhang, Xiaoxuan Zhao, Weisheng Zhao
2014 — conf
An overview of spin-based integrated circuits.
ASP-DAC
Wang Kang, Weisheng Zhao, Zhaohao Wang, Jacques-Olivier Klein, Yue Zhang, Djaafar Chabi, Youguang Zhang, Dafine Ravelosona, Claude Chappert
2014 J jnl
Compact model of magnetic tunnel junction with stochastic spin transfer torque switching for reliability analyses.
Microelectron. Reliab.
You Wang, Yue Zhang, Erya Deng, Jacques-Olivier Klein, Lirida A. B. Naviner, Weisheng Zhao
2014 — conf
Design and analysis of Racetrack memory based on magnetic domain wall motion in nanowires.
NANOARCH
Nesrine Ben Romdhane, Weisheng Zhao, Yue Zhang, Jacques-Olivier Klein, Z. R. Wang, Dafine Ravelosona
2014 J jnl
Design and analysis of crossbar architecture based on complementary resistive switching non-volatile memory cells.
J. Parallel Distributed Comput.
Weisheng Zhao, Jean-Michel Portal, Wang Kang, Mathieu Moreau, Yue Zhang, Hassen Aziza, Jacques-Olivier Klein, Zhaohao Wang, Damien Querlioz, Damien Deleruyelle, Marc Bocquet, Dafine Ravelosona, Christophe Muller, Claude Chappert
2014 A conf
Spintronics for low-power computing.
DATE
Yue Zhang, Weisheng Zhao, Jacques-Olivier Klein, Wang Kang, Damien Querlioz, Youguang Zhang, Dafine Ravelosona, Claude Chappert
2014 J jnl
Synchronous Non-Volatile Logic Gate Design Based on Resistive Switching Memories.
IEEE Trans. Circuits Syst. I Regul. Pap.
Weisheng Zhao, Mathieu Moreau, Erya Deng, Yue Zhang, Jean-Michel Portal, Jacques-Olivier Klein, Marc Bocquet, Hassen Aziza, Damien Deleruyelle, Christophe Muller, Damien Querlioz, Nesrine Ben Romdhane, Dafine Ravelosona, Claude Chappert
2014 J jnl
Ultra Low Power Magnetic Flip-Flop Based on Checkpointing/Power Gating and Self-Enable Mechanisms.
IEEE Trans. Circuits Syst. I Regul. Pap.
Djaafar Chabi, Weisheng Zhao, Erya Deng, Yue Zhang, Nesrine Ben Romdhane, Jacques-Olivier Klein, Claude Chappert
2013 J jnl
A low-cost built-in error correction circuit design for STT-MRAM reliability improvement.
Microelectron. Reliab.
Wang Kang, Weisheng Zhao, Zhaohao Wang, Yue Zhang, Jacques-Olivier Klein, Youguang Zhang, Claude Chappert, Dafine Ravelosona
2013 — conf
Analytical study of complementary memristive synchronous logic gates.
NANOARCH
Jean-Michel Portal, Mathieu Moreau, Marc Bocquet, Hassen Aziza, Damien Deleruyelle, Christophe Muller, Yue Zhang, Erya Deng, Jacques-Olivier Klein, Damien Querlioz, Dafine Ravelosona, Claude Chappert, Weisheng Zhao
2013 — conf
Low power magnetic flip-flop based on checkpointing and self-enable mechanism.
NEWCAS
Djaafar Chabi, Weisheng Zhao, Yue Zhang, Jacques-Olivier Klein, Claude Chappert
2013 J jnl
Magnetic Adder Based on Racetrack Memory.
IEEE Trans. Circuits Syst. I Regul. Pap.
Hong-Phuc Trinh, Weisheng Zhao, Jacques-Olivier Klein, Yue Zhang, Dafine Ravelosona, Claude Chappert
2013 C conf
Spin-electronics based logic fabrics.
VLSI-SoC
Weisheng Zhao, Jacques-Olivier Klein, Zhaohao Wang, Yue Zhang, Nesrine Ben Romdhane, Damien Querlioz, Dafine Ravelosona, Claude Chappert
2013 — conf
Synchronous full-adder based on complementary resistive switching memory cells.
NEWCAS
Yue Zhang, Erya Deng, Jacques-Olivier Klein, Damien Querlioz, Dafine Ravelosona, Claude Chappert, Weisheng Zhao, Mathieu Moreau, Jean-Michel Portal, Marc Bocquet, Hassen Aziza, Damien Deleruyelle, Christophe Muller
2012 — conf
Crossbar architecture based on 2R complementary resistive switching memory cell.
NANOARCH
Weisheng Zhao, Yue Zhang, Jacques-Olivier Klein, Damien Querlioz, Djaafar Chabi, Dafine Ravelosona, Claude Chappert, Jean-Michel Portal, Marc Bocquet, Hassen Aziza, Damien Deleruyelle, Christophe Muller
2012 J jnl
Failure and reliability analysis of STT-MRAM.
Microelectron. Reliab.
Weisheng Zhao, Yue Zhang, Thibaut Devolder, Jacques-Olivier Klein, Dafine Ravelosona, Claude Chappert, Pascale Mazoyer
2011 C conf
Embedded MRAM for high-speed computing.
VLSI-SoC
Weisheng Zhao, Yue Zhang, Yahya Lakys, Jacques-Olivier Klein, Daniel Etiemble, D. Revelosona, Claude Chappert, Lionel Torres, Luis Vitorio Cargnini, Raphael Martins Brum, Yoann Guillemenet, Gilles Sassatelli
2011 — conf
High Performance SoC Design Using Magnetic Logic and Memory.
VLSI-SoC (Selected Papers)
Weisheng Zhao, Lionel Torres, Luis Vitorio Cargnini, Raphael Martins Brum, Yue Zhang, Yoann Guillemenet, Gilles Sassatelli, Yahya Lakys, Jacques-Olivier Klein, Daniel Etiemble, Dafine Ravelosona, Claude Chappert