Yue Zha

19 papers A* 5A 5Misc 1Journal 6Unranked 2
YearRankTypeTitle / Venue / Authors
2022 A conf
Revisiting PathFinder Routing Algorithm.
FPGA
Yue Zha, Jing Li
2021 A* conf
Hetero-ViTAL: A Virtualization Stack for Heterogeneous FPGA Clusters.
ISCA
Yue Zha, Jing Li
2021 A* conf
When application-specific ISA meets FPGAs: a multi-layer virtualization framework for heterogeneous cloud FPGAs.
ASPLOS
Yue Zha, Jing Li
2020 A* conf
Hyper-Ap: Enhancing Associative Processing Through A Full-Stack Optimization.
ISCA
Yue Zha, Jing Li
2020 J jnl
Liquid Silicon: A Nonvolatile Fully Programmable Processing-in-Memory Processor With Monolithically Integrated ReRAM.
IEEE J. Solid State Circuits
Yue Zha, Etienne Nowak, Jing Li
2020 J jnl
MEG: A RISCV-based System Emulation Infrastructure for Near-data Processing Using FPGAs and High-bandwidth Memory.
ACM Trans. Reconfigurable Technol. Syst.
Jialiang Zhang, Yue Zha, Nicholas Beckwith, Bangya Liu, Jing Li
2020 A* conf
Virtualizing FPGAs in the Cloud.
ASPLOS
Yue Zha, Jing Li
2019 — conf
Liquid Silicon: A Nonvolatile Fully Programmable Processing-In-Memory Processor with Monolithically Integrated ReRAM for Big Data/Machine Learning Applications.
VLSI Circuits
Yue Zha, Etienne Nowak, Jing Li
2019 Misc conf
MEG: A RISCV-Based System Simulation Infrastructure for Exploring Memory Optimization Using FPGAs and Hybrid Memory Cube.
FCCM
Jialiang Zhang, Yang Liu, Gaurav Jain, Yue Zha, Jonathan Ta, Jing Li
2018 J jnl
An Alternative Analytical Approach to Associative Processing.
IEEE Comput. Archit. Lett.
Soroosh Khoram, Yue Zha, Jing Li
2018 J jnl
CMA: A Reconfigurable Complex Matching Accelerator for Wire-Speed Network Intrusion Detection.
IEEE Comput. Archit. Lett.
Yue Zha, Jing Li
2018 A* conf
Liquid Silicon-Monona: A Reconfigurable Memory-Oriented Computing Fabric with Scalable Multi-Context Support.
ASPLOS
Yue Zha, Jing Li
2018 A conf
Liquid Silicon: A Data-Centric Reconfigurable Architecture Enabled by RRAM Technology.
FPGA
Yue Zha, Jing Li
2018 J jnl
Specialization: A New Path Towards Low Power.
J. Low Power Electron.
Yue Zha, Jing Li
2017 A conf
A Mixed-Signal Data-Centric Reconfigurable Architecture enabled by RRAM Technology (Abstract Only).
FPGA
Yue Zha, Jialiang Zhang, Zhiqiang Wei, Jing Li
2017 — conf
Challenges and Opportunities: From Near-memory Computing to In-memory Computing.
ISPD
Soroosh Khoram, Yue Zha, Jialiang Zhang, Jing Li
2017 J jnl
IMEC: A Fully Morphable In-Memory Computing Fabric Enabled by Resistive Crossbar.
IEEE Comput. Archit. Lett.
Yue Zha, Jing Li
2017 A conf
RRAM-based reconfigurable in-memory computing architecture with hybrid routing.
ICCAD
Yue Zha, Jing Li
2016 A conf
Reconfigurable in-memory computing with resistive memory crossbar.
ICCAD
Yue Zha, Jing Li