Yuchun Ma

96 papers A* 2A 4B 1C 5Journal 27Unranked 56
YearRankTypeTitle / Venue / Authors
2025 J jnl
Fine Grain 3D Integration for Microarchitecture Design Through Cube Packing Exploration.
CoRR
Yongxiang Liu, Yuchun Ma, Eren Kurshan, Glenn Reinman, Jason Cong
2025 — conf
Iterative Design of a Teaching Assistant Training Program in Computer Science Using the Agile Method.
SIGCSE (1)
Runda Liu, Shengqi Chen, Jiajie Chen, Songjie Niu, Yuchun Ma, Xiaofeng Tang
2023 J jnl
Adaptive Selection and Clustering of Partial Reconfiguration Modules for Modern FPGA Design Flow.
ACM Trans. Reconfigurable Technol. Syst.
Kang Zhao, Yuchun Ma, Ruining He, Jixing Zhang, Ning Xu, Jinian Bian
2022 J jnl
SNEGAN: Signed Network Embedding by Using Generative Adversarial Nets.
IEEE Trans. Emerg. Top. Comput. Intell.
Lijia Ma, Yuchun Ma, Qiuzhen Lin, Junkai Ji, Carlos A. Coello Coello, Maoguo Gong
2019 A conf
AddressNet: Shift-Based Primitives for Efficient Convolutional Neural Networks.
WACV
Yihui He, Xianggen Liu, Huasong Zhong, Yuchun Ma
2018 — conf
Lattice-Based Scheduling for Multi-FPGA Systems.
FPT
Teng Yu, Bo Feng, Mark Stillwell, Liucheng Guo, Yuchun Ma, John Thomson
2018 J jnl
Shift-based Primitives for Efficient Convolutional Neural Networks.
CoRR
Huasong Zhong, Xianggen Liu, Yihui He, Yuchun Ma
2017 B conf
Intelligent Composition of Test Papers based on MOOC Learning Data.
EDM
Lin Ma, Yuchun Ma
2017 J jnl
基于MPSoC并行调度的矩阵乘法加速算法研究 (Research on Acceleration of Matrix Multiplication Based on Parallel Scheduling on MPSoC).
计算机科学
Fei Yang, Yuchun Ma, Jin Hou, Ning Xu
2016 — conf
F-CNN: An FPGA-based framework for training Convolutional Neural Networks.
ASAP
Wenlai Zhao, Haohuan Fu, Wayne Luk, Teng Yu, Shaojun Wang, Bo Feng, Yuchun Ma, Guangwen Yang
2016 — conf
Modular Placement for Interposer based Multi-FPGA Systems.
ACM Great Lakes Symposium on VLSI
Fubing Mao, Wei Zhang, Bo Feng, Bingsheng He, Yuchun Ma
2016 — conf
Relation-oriented resource allocation for multi-accelerator systems.
ASAP
Teng Yu, Bo Feng, Mark Stillwell, José Gabriel F. Coutinho, Wenlai Zhao, Shuang Liang, Wayne Luk, Alexander L. Wolf, Yuchun Ma
2015 J jnl
HS3-DPG: Hierarchical Simulation for 3-D P/G Network.
IEEE Trans. Very Large Scale Integr. Syst.
Yu Wang, Song Yao, Shuai Tao, Xiaoming Chen, Yuchun Ma, Yiyu Shi, Huazhong Yang
2015 — conf
HW/SW Partitioning Algorithm Targeting MPSOC with Dynamic Partial Reconfigurable Fabric.
CAD/Graphics
Chao Zhang, Yuchun Ma, Wayne Luk
2015 J jnl
Whitespace-Aware TSV Arrangement in 3-D Clock Tree Synthesis.
IEEE Trans. Very Large Scale Integr. Syst.
Wulong Liu, Yu Wang, Guoqing Chen, Yuchun Ma, Yuan Xie, Huazhong Yang
2014 — ed.
2014 International Conference on Field-Programmable Technology, FPT 2014, Shanghai, China, December 10-12, 2014
FPT
Jialin Chen, Wenbo Yin, Yuichiro Shibata, Lingli Wang, Hayden Kwok-Hay So, Yuchun Ma
2014 — conf
A universal FPGA-based floating-point matrix processor for mobile systems.
FPT
Wenqiang Wang, Kaiyuan Guo, Mengyuan Gu, Yuchun Ma, Yu Wang
2014 — conf
Efficient region-aware P/G TSV planning for 3D ICs.
ISQED
Song Yao, Xiaoming Chen, Yu Wang, Yuchun Ma, Yuan Xie, Huazhong Yang
2014 C conf
HW/SW partitioning for region-based dynamic partial reconfigurable FPGAs.
ICCD
Yuchun Ma, Jinglan Liu, Chao Zhang, Wayne Luk
2014 J jnl
Network flow-based simultaneous retiming and slack budgeting for low power design.
CoRR
Bei Yu, Sheqin Dong, Yuchun Ma, Tao Lin, Yu Wang, Song Chen, Satoshi Goto
2014 J jnl
On-Chip Hybrid Power Supply System for Wireless Sensor Nodes.
ACM J. Emerg. Technol. Comput. Syst.
Wulong Liu, Yu Wang, Yuchun Ma, Yuan Xie, Huazhong Yang
2013 C conf
Automatic enhanced CDFG generation based on runtime instrumentation.
CSCWD
Zhongda Yuan, Yuchun Ma, Jinian Bian, Kang Zhao
2013 — conf
Data dependency aware prefetch scheduling for Dynamic Partial reconfigurable designs.
ASICON
Jixin Zhang, Ning Xu, Yuchun Ma, Yu Wang, Jinian Bian
2013 C conf
Efficient custom instruction generation based on characterizing of basic blocks.
CSCWD
Guoqiang Liang, Yuchun Ma, Kang Zhao, Jinian Bian
2013 J jnl
Evaluation and mitigation of performance degradation under random telegraph noise for digital circuits.
IET Circuits Devices Syst.
Xiaoming Chen, Hong Luo, Yu Wang, Yu Cao, Yuan Xie, Yuchun Ma, Huazhong Yang
2013 — conf
HS3DPG: Hierarchical simulation for 3D P/G network.
ASP-DAC
Shuai Tao, Xiaoming Chen, Yu Wang, Yuchun Ma, Yiyu Shi, Hui Wang, Huazhong Yang
2013 — conf
Incremental 3D NoC synthesis based on physical-aware router merging algorithm.
ASICON
YuanYuan Li, Ning Xu, Yuchun Ma, Jinian Bian
2013 — conf
RALP: Reconvergence-aware layer partitioning for 3D FPGAs.
ReConFig
Qingyu Liu, Yuchun Ma, Yu Wang, Wayne Luk, Jinian Bian
2013 — conf
TSV-aware topology generation for 3D Clock Tree Synthesis.
ISQED
Wulong Liu, Haixiao Du, Yu Wang, Yuchun Ma, Yuan Xie, Jinguo Quan, Huazhong Yang
2013 J jnl
Thermal-Aware Post Layout Voltage-Island Generation for 3D ICs.
J. Comput. Sci. Technol.
Ning Xu, Yuchun Ma, Jia Liu, Shou-Chun Tao
2013 J jnl
Thermal-aware P/G TSV planning for IR drop reduction in 3D ICs.
Integr.
Zuowei Li, Yuchun Ma, Qiang Zhou, Yici Cai, Yuan Xie, Tingting Huang
2013 J jnl
Unification of PR Region floorplanning and Fine-Grained Placement for Dynamic Partially Reconfigurable FPGAs.
J. Circuits Syst. Comput.
Ruining He, Guoqiang Liang, Yuchun Ma, Yu Wang, Jinian Bian
2013 — conf
Whitespace-aware TSV arrangement in 3D clock tree synthesis.
ISVLSI
Xin Li, Wulong Liu, Haixiao Du, Yu Wang, Yuchun Ma, Huazhong Yang
2012 A conf
ISBA: An independent set-based algorithm for automated partial reconfiguration module generation.
ICCAD
Ruining He, Yuchun Ma, Kang Zhao, Jinian Bian
2012 — conf
Leakage-aware performance-driven TSV-planning based on network flow algorithm in 3D ICs.
ISQED
Kan Wang, Sheqin Dong, Yuchun Ma, Satoshi Goto, Jason Cong
2012 — conf
PDPR: Fine-Grained Placement for Dynamic Partially Reconfigurable FPGAs.
ARC
Ruining He, Guoqiang Liang, Yuchun Ma, Yu Wang, Jinian Bian
2012 — conf
SMPP: Generic SAT Solver over Reconfigurable Hardware Accelerator.
IPDPS Workshops
Zhongda Yuan, Yuchun Ma, Jinian Bian
2012 — conf
Temporal Performance Degradation under RTN: Evaluation and Mitigation for Nanoscale Circuits.
ISVLSI
Hong Luo, Yu Wang, Yu Cao, Yuan Xie, Yuchun Ma, Huazhong Yang
2012 — conf
Thermal-aware power network design for IR drop reduction in 3D ICs.
ASP-DAC
Zuowei Li, Yuchun Ma, Qiang Zhou, Yici Cai, Yu Wang, Tingting Huang, Yuan Xie
2012 J jnl
Variation-Aware Supply Voltage Assignment for Simultaneous Power and Aging Optimization.
IEEE Trans. Very Large Scale Integr. Syst.
Xiaoming Chen, Yu Wang, Yu Cao, Yuchun Ma, Huazhong Yang
2011 — conf
Circuit-level delay modeling considering both TDDB and NBTI.
ISQED
Hong Luo, Xiaoming Chen, Jyothi Velamala, Yu Wang, Yu Cao, Vikas Chandra, Yuchun Ma, Huazhong Yang
2011 — conf
Incremental layout optimization for NoC designs based on MILP formulation.
ASICON
Jia Liu, Yuchun Ma, Ning Xu, Yu Wang
2011 J jnl
Leakage-Aware TSV-Planning with Power-Temperature-Delay Dependence in 3D ICs.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Kan Wang, Sheqin Dong, Yuchun Ma, Yu Wang, Xianlong Hong, Jason Cong
2011 — conf
Network flow-based simultaneous retiming and slack budgeting for low power design.
ASP-DAC
Bei Yu, Sheqin Dong, Yuchun Ma, Tao Lin, Yu Wang, Song Chen, Satoshi Goto
2011 — conf
Novel and efficient min cut based voltage assignment in gate level.
ISQED
Tao Lin, Sheqin Dong, Song Chen, Yuchun Ma, Ou He, Satoshi Goto
2011 — conf
On-chip hybrid power supply system for wireless sensor nodes.
ASP-DAC
Wulong Liu, Yu Wang, Wei Liu, Yuchun Ma, Yuan Xie, Huazhong Yang
2011 — conf
Rethinking thermal via planning with timing-power-temperature dependence for 3D ICs.
ASP-DAC
Kan Wang, Yuchun Ma, Sheqin Dong, Yu Wang, Xianlong Hong, Jason Cong
2011 — conf
Tree-Based Partitioning Approach for Network-on-Chip Synthesis.
CAD/Graphics
Binjie Song, Shan Zeng, Yuchun Ma, Ning Xu, Yu Wang
2010 — conf
PS-FPG: pattern selection based co-design of floorplan and power/ground network with wiring resource optimization.
ASP-DAC
Li Li, Yuchun Ma, Ning Xu, Yu Wang, Xianlong Hong
2010 J jnl
Signal through-the-silicon via planning and pin assignment for thermal and wire length optimization in 3D ICs.
Integr.
Xu He, Sheqin Dong, Yuchun Ma
2010 — conf
Simultaneous slack budgeting and retiming for synchronous circuits optimization.
ASP-DAC
Shenghua Liu, Yuchun Ma, Xianlong Hong, Yu Wang
2010 J jnl
Thermal Impacts of Leakage Power in 2D/3D floorplanning.
J. Circuits Syst. Comput.
Yuchun Ma, Qiang Zhou, Pingqiang Zhou, Xianlong Hong
2009 — conf
A novel thermal optimization flow using incremental floorplanning for 3D ICs.
ASP-DAC
Xin Li, Yuchun Ma, Xianlong Hong
2009 — conf
Incremental power optimization for multiple supply voltage design.
ISQED
Yuchun Ma, Xiang Qiu, Xiangqing He, Xianlong Hong
2009 — conf
Modern Floorplanning with Boundary Clustering Constraint.
ISVLSI
Li Li, Yuchun Ma, Ning Xu, Yu Wang, Xianlong Hong
2009 — conf
Multi-objective Floorplanning Based on Fuzzy Logic.
FSKD (4)
Fubing Mao, Yuchun Ma, Ning Xu, Xianlong Hong, Yu Wang
2009 — conf
Simultaneous buffer and interlayer via planning for 3D floorplanning.
ISQED
Xu He, Sheqin Dong, Yuchun Ma, Xianlong Hong
2009 J jnl
Thermal-Aware Incremental Floorplanning for 3D ICs Based on MILP Formulation.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Yuchun Ma, Xin Li, Yu Wang, Xianlong Hong
2009 A conf
Variation-aware supply voltage assignment for minimizing circuit degradation and leakage.
ISLPED
Xiaoming Chen, Yu Wang, Yu Cao, Yuchun Ma, Huazhong Yang
2008 — conf
IPOSA: A Novel Slack Distribution Algorithm for Interconnect Power Optimization.
ISQED
Xiang Qiu, Yuchun Ma, Xiangqing He, Xianlong Hong
2008 J jnl
Investigating the effects of fine-grain three-dimensional integration on microarchitecture design.
ACM J. Emerg. Technol. Comput. Syst.
Yuchun Ma, Yongxiang Liu, Eren Kursun, Glenn Reinman, Jason Cong
2008 — conf
LP based white space redistribution for thermal via planning and performance optimization in 3D ICs.
ASP-DAC
Xin Li, Yuchun Ma, Xianlong Hong, Sheqin Dong, Jason Cong
2008 — conf
MRAPF: Minimum RTT Asymmetric-Path First for Mobile Multi-homed End-to-End Transfer.
FSKD (4)
Jiemin Liu, Yuchun Ma, Yuan Gao
2007 A conf
3D-STAF: scalable temperature and leakage aware floorplanning for three-dimensional integrated circuits.
ICCAD
Pingqiang Zhou, Yuchun Ma, Zhuoyuan Li, Robert P. Dick, Li Shang, Hai Zhou, Xianlong Hong, Qiang Zhou
2007 C conf
A Fast 3D-BSG Algorithm for 3D Packing Problem.
ISCAS
Lingyi Zhang, Sheqin Dong, Xianlong Hong, Yuchun Ma
2007 — conf
An accurate and efficient probabilistic congestion estimation model in x architecture.
SLIP
Yaoguang Wei, Sheqin Dong, Xianlong Hong, Yuchun Ma
2007 — conf
An effective buffer planning algorithm for IP based fixed-outline SOC placement.
ACM Great Lakes Symposium on VLSI
Ou He, Sheqin Dong, Jinian Bian, Yuchun Ma, Xianlong Hong
2007 C conf
Fine grain 3D integration for microarchitecture design through cube packing exploration.
ICCD
Yongxiang Liu, Yuchun Ma, Eren Kursun, Glenn Reinman, Jason Cong
2007 — conf
Interconnect Power Optimization Based on Timing Analysis.
ISVLSI
Liu Yang, Sheqin Dong, Yuchun Ma, Xianlong Hong
2007 — conf
Micro-architecture Pipelining Optimization with Throughput-Aware Floorplanning.
ASP-DAC
Yuchun Ma, Zhuoyuan Li, Jason Cong, Xianlong Hong, Glenn Reinman, Sheqin Dong, Qiang Zhou
2007 — conf
Thermal Effects with Leakage Power Considered in 2D/3D Floorplanning.
CAD/Graphics
Pingqiang Zhou, Yuchun Ma, Qiang Zhou, Xianlong Hong
2007 — conf
Thermal-driven Symmetry Constraint for Analog Layout with CBL Representation.
ASP-DAC
Jiayi Liu, Sheqin Dong, Yuchun Ma, Di Long, Xianlong Hong
2006 — conf
A Two-stage Incremental Floorplanning Algorithm with Boundary Constraints.
APCCAS
Liu Yang, Sheqin Dong, Xianlong Hong, Yuchun Ma
2006 — conf
An automated design flow for 3D microarchitecture evaluation.
ASP-DAC
Jason Cong, Ashok Jagannathan, Yuchun Ma, Glenn Reinman, Jie Wei, Yan Zhang
2006 J jnl
General Floorplans with L/T-Shaped Blocks Using Corner Block List.
J. Comput. Sci. Technol.
Yuchun Ma, Xianlong Hong, Sheqin Dong, Chung-Kuan Cheng, Jun Gu
2006 J jnl
VLSI Block Placement With Alignment Constraints.
IEEE Trans. Circuits Syst. II Express Briefs
Song Chen, Sheqin Dong, Xianlong Hong, Yuchun Ma, Chung-Kuan Cheng
2005 — conf
Buffer Planning Algorithm Based on Partial Clustered Floorplanning.
ISQED
Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Chung-Kuan Cheng
2005 J jnl
Buffer planning as an Integral part of floorplanning with consideration of routing congestion.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Chung-Kuan Cheng, Jun Gu
2005 — conf
Floorplanning with Consideration of White Space Resource Distribution for Repeater Planning.
ISQED
Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Chung-Kuan Cheng
2005 — conf
Performance constrained floorplanning based on partial clustering [IC layout].
ISCAS (2)
Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Chung-Kuan Cheng
2005 — conf
VLSI block placement with alignment constraints based on corner block list.
ISCAS (6)
Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Chung-Kuan Cheng
2004 J jnl
A buffer planning algorithm for chip-level floorplanning.
Sci. China Ser. F Inf. Sci.
Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Yici Cai, Chung-Kuan Cheng, Jun Gu
2004 — conf
A buffer planning algorithm with congestion optimization.
ASP-DAC
Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Yici Cai, Chung-Kuan Cheng, Jun Gu
2004 — conf
Buffer allocation algorithm with consideration of routing congestion.
ASP-DAC
Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Yici Cai, Chung-Kuan Cheng, Jun Gu
2004 J jnl
Corner block list representation and its application with boundary constraints.
Sci. China Ser. F Inf. Sci.
Xianlong Hong, Yuchun Ma, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu
2004 J jnl
Fast Evaluation of Bounded Slice-Line Grid.
J. Comput. Sci. Technol.
Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Chung-Kuan Cheng, Jun Gu
2004 J jnl
Stairway compaction using corner block list and its applications with rectilinear blocks.
ACM Trans. Design Autom. Electr. Syst.
Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu
2003 — conf
A buffer planning algorithm based on dead space redistribution.
ASP-DAC
Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Yici Cai, Chung-Kuan Cheng, Jun Gu
2003 — conf
An integrated floorplanning with an efficient buffer planning algorithm.
ISPD
Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Yici Cai, Chung-Kuan Cheng, Jun Gu
2003 — conf
Arbitrary convex and concave rectilinear block packing based on corner block list.
ISCAS (5)
Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Song Chen, Chung-Kuan Cheng, Jun Gu
2003 A* conf
Dynamic global buffer planning optimization based on detail block locating and congestion analysis.
DAC
Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Yici Cai, Chung-Kuan Cheng, Jun Gu
2003 — conf
Evaluating a bounded slice-line grid assignment in O(nlogn) time.
ISCAS (4)
Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Yici Cai, Chung-Kuan Cheng, Jun Gu
2002 — conf
Stairway Compaction using Corner Block List and Its Applications with Rectilinear Blocks.
ASP-DAC/VLSI Design
Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu
2001 A* conf
Floorplanning with Abutment Constraints and L-Shaped/T-Shaped Blocks based on Corner Block List.
DAC
Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu
2001 J jnl
Floorplanning with abutment constraints based on corner block list.
Integr.
Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu
2001 — conf
VLSI floorplanning with boundary constraints based on corner block list.
ASP-DAC
Yuchun Ma, Sheqin Dong, Xianlong Hong, Yici Cai, Chung-Kuan Cheng, Jun Gu