Yuanqing Cheng

63 papers A* 2A 7B 1C 7Journal 27Unranked 19
YearRankTypeTitle / Venue / Authors
2026 J jnl
ASAP: Accelerating Corner-Based Timing Analysis With Bayesian Active Self-Attention Neural Process.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Longze Wang, Wei W. Xing, Zhelong Wang, Christos P. Sotiriou, Nikolaos Sketopoulos, Ning Xu, Yuanqing Cheng
2026 — conf
Full-Chip Thermal Map Estimation by Multimodal Data Fusion via Denoising Diffusion.
ASP-DAC
Jing Li, Wei Xing, Yuquan Sun, Yuanqing Cheng
2026 — conf
Φ-BO: Physics-Informed Bayesian Optimization for Multi-Port Decoupling Capacitor Placement in 2.5-D Chiplets.
ASP-DAC
Quansen Wang, Yuchuan Lin, Zhuohua Liu, Wei Xing, Wei Zhang, Ning Xu, Yuanqing Cheng
2025 A conf
A Comprehensive Inductance-Aware Modeling Approach to Power Distribution Network in Heterogeneous 3D Integrated Circuits.
DATE
Quansen Wang, Vasilis F. Pavlidis, Yuanqing Cheng
2025 J jnl
Carbon Nanotube Interconnect Optimizations With Bayesian Neural Network and Bayesian Optimization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Zhelong Wang, Wei W. Xing, Ning Xu, Yuanqing Cheng
2025 A conf
Cool3D: Cost-Optimized and Efficient Liquid Cooling for 3D Integrated Circuits.
DATE
Jing Li, Bingrui Zhang, Yuquan Sun, Wei Xing, Yuanqing Cheng
2025 — conf
Inductive Effect-Aware Power Distribution Network Modeling and Analysis for Heterogeneous 3D Integrated Circuits.
ISVLSI
Quansen Wang, Vasilis F. Pavlidis, Xuning Feng, Rui Wang, Wei Zhang, Yuanqing Cheng
2025 C conf
Inter-chip Clock Network Synthesis on Passive Interposer of 2.5D Chiplet Considering Transmission Line Effect.
VLSI-SoC
Tai Yan, Yiyu Wang, Zhan Li, Ning Xu, Yuanqing Cheng
2025 — conf
PV-Clock: Process Variation-Aware 3D Clock Network Synthesis for Robust and Power-Efficient Timing Optimization.
ISVLSI
Yiyu Wang, Vasilis F. Pavlidis, Rui Wang, Yuanqing Cheng
2025 J jnl
Testing and Fault Tolerance Techniques for Carbon Nanotube-Based FPGAs.
CoRR
Siyuan Lu, Kangwei Xu, Peng Xie, Rui Wang, Yuanqing Cheng
2025 J jnl
Testing and fault tolerance techniques for carbon nanotube-based FPGAs.
Integr.
Siyuan Lu, Kangwei Xu, Peng Xie, Rui Wang, Yuanqing Cheng
2024 — conf
3D SRAM Design & Optimization with Open Source Memory Compiler.
3DIC
Sunan Chen, Chao Wu, Yunlang Cai, Yuan Guan, Yuanqing Cheng
2024 A conf
ARO: Autoregressive Operator Learning for Transferable and Multi-fidelity 3D-IC Thermal Analysis With Active Learning.
ICCAD
Mingyue Wang, Yuanqing Cheng, Weiheng Zeng, Zhenjie Lu, Vasilis F. Pavlidis, Wei Xing
2024 B conf
BoCNT: A Bayesian Optimization Framework for Global CNT Interconnect Optimization.
ASPDAC
Hang Wu, Ning Xu, Wei W. Xing, Yuanqing Cheng
2024 A* conf
MAUnet: Multiscale Attention U-Net for Effective IR Drop Prediction.
DAC
Mingyue Wang, Yuanqing Cheng, Yage Lin, Kelin Peng, Shunchuan Yang, Zhou Jin, Wei W. Xing
2024 J jnl
Multicorner Timing Analysis Acceleration for Iterative Physical Design of ICs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Wei W. Xing, Longze Wang, Zhelong Wang, Zhaoyu Shi, Ning Xu, Yuanqing Cheng, Weisheng Zhao
2024 J jnl
PDG: A Prefetcher for Dynamic Graph Updating.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Xinmiao Zhang, Cheng Liu, Jiacheng Ni, Yuanqing Cheng, Lei Zhang, Huawei Li, Xiaowei Li
2023 A conf
OPT: Optimal Proposal Transfer for Efficient Yield Optimization for Analog and SRAM Circuits.
ICCAD
Yanfang Liu, Guohao Dai, Yuanqing Cheng, Wang Kang, Wei W. Xing
2023 A* conf
TOTAL: Multi-Corners Timing Optimization Based on Transfer and Active Learning.
DAC
Wei W. Xing, Zheng Xing, Rongqi Lu, Zhelong Wang, Ning Xu, Yuanqing Cheng, Weisheng Zhao
2022 J jnl
All-spin PUF: An Area-efficient and Reliable PUF Design with Signature Improvement for Spin-transfer Torque Magnetic Cell-based All-spin Circuits.
ACM J. Emerg. Technol. Comput. Syst.
Kangwei Xu, Dongrong Zhang, Qiang Ren, Yuanqing Cheng, Patrick Girard
2022 J jnl
Carbon Nanotube SRAM in 5-nm Technology Node Design, Optimization, and Performance Evaluation - Part I: CNFET Transistor Optimization.
IEEE Trans. Very Large Scale Integr. Syst.
Rongmei Chen, Lin Chen, Jie Liang, Yuanqing Cheng, Souhir Elloumi, Jaehyun Lee, Kangwei Xu, Vihar P. Georgiev, Kai Ni, Peter Debacker, Asen Asenov, Aida Todri-Sanial
2022 J jnl
Carbon Nanotube SRAM in 5-nm Technology Node Design, Optimization, and Performance Evaluation - Part II: CNT Interconnect Optimization.
IEEE Trans. Very Large Scale Integr. Syst.
Rongmei Chen, Lin Chen, Jie Liang, Yuanqing Cheng, Souhir Elloumi, Jaehyun Lee, Kangwei Xu, Vihar P. Georgiev, Kai Ni, Peter Debacker, Asen Asenov, Aida Todri-Sanial
2022 J jnl
Emerging monolithic 3D integration: Opportunities and challenges from the computer system perspective.
Integr.
Yuanqing Cheng, Xiaochen Guo, Vasilis F. Pavlidis
2022 — conf
Fault Testing and Diagnosis Techniques for Carbon Nanotube-Based FPGAs.
ASP-DAC
Kangwei Xu, Yuanqing Cheng
2022 A conf
GIA: A Reusable General Interposer Architecture for Agile Chiplet Integration.
ICCAD
Fuping Li, Ying Wang, Yuanqing Cheng, Yujie Wang, Yinhe Han, Huawei Li, Xiaowei Li
2022 — conf
Thermal Modeling and Design Exploration for Monolithic 3D ICs.
ISQED
Baoli Peng, Vasilis F. Pavlidis, Yi-Chung Chen, Yuanqing Cheng
2021 J jnl
A Survey of Test and Reliability Solutions for Magnetic Random Access Memories.
Proc. IEEE
Patrick Girard, Yuanqing Cheng, Arnaud Virazel, Wei Zhao, Rajendra Bishnoi, Mehdi B. Tahoori
2021 J jnl
DOVA PRO: A Dynamic Overwriting Voltage Adjustment Technique for STT-MRAM L1 Cache Considering Dielectric Breakdown Effect.
IEEE Trans. Very Large Scale Integr. Syst.
Jinbo Chen, Chengcheng Lu, Jiacheng Ni, Xiaochen Guo, Patrick Girard, Yuanqing Cheng
2021 J jnl
Taming Process Variations in CNFET for Efficient Last Level Cache Design.
CoRR
Dawen Xu, Zhuangyu Feng, Cheng Liu, Li Li, Ying Wang, Yuanqing Cheng, Huawei Li, Xiaowei Li
2020 J jnl
A Novel High Performance and Energy Efficient NUCA Architecture for STT-MRAM LLCs With Thermal Consideration.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Bi Wu, Pengcheng Dai, Yuanqing Cheng, Ying Wang, Jianlei Yang, Zhaohao Wang, Dijun Liu, Weisheng Zhao
2020 J jnl
Bulkyflip: A NAND-SPIN-Based Last-Level Cache With Bandwidth-Oriented Write Management Policy.
IEEE Trans. Circuits Syst. I Regul. Pap.
Bi Wu, Weisheng Zhao, Xiaobo Sharon Hu, Pengcheng Dai, Zhaohao Wang, Chao Wang, Ying Wang, Jianlei Yang, Yuanqing Cheng, Dijun Liu, Youguang Zhang
2020 — conf
DOVA: A Dynamic Overwriting Voltage Adjustment for STT-RAM L1 Cache.
ISQED
Jinbo Chen, Keren Liu, Xiaochen Guo, Patrick Girard, Yuanqing Cheng
2020 — conf
SIP: Boosting Up Graph Computing by Separating the Irregular Property Data.
ACM Great Lakes Symposium on VLSI
Jiacheng Ni, Xiaochen Guo, Yuanqing Cheng
2020 J jnl
Write Back Energy Optimization for STT-MRAM-based Last-level Cache with Data Pattern Characterization.
ACM J. Emerg. Technol. Comput. Syst.
Jiacheng Ni, Keren Liu, Bi Wu, Weisheng Zhao, Yuanqing Cheng, Xiaolong Zhang, Ying Wang
2020 — conf
Zero-skew Clock Network Synthesis for Monolithic 3D ICs with Minimum Wirelength.
ACM Great Lakes Symposium on VLSI
Wei Wang, Vasilis F. Pavlidis, Yuanqing Cheng
2019 J jnl
An Adaptive Thermal-Aware ECC Scheme for Reliable STT-MRAM LLC Design.
IEEE Trans. Very Large Scale Integr. Syst.
Bi Wu, Beibei Zhang, Yuanqing Cheng, Ying Wang, Dijun Liu, Weisheng Zhao
2018 J jnl
An Adaptive 3T-3MTJ Memory Cell Design for STT-MRAM-Based LLCs.
IEEE Trans. Very Large Scale Integr. Syst.
Linuo Xue, Bi Wu, Beibei Zhang, Yuanqing Cheng, Peiyuan Wang, Chando Park, Jimmy J. Kan, Seung-Hyuk Kang, Yuan Xie
2018 C conf
NEAR: A Novel Energy Aware Replacement Policy for STT-MRAM LLCs.
ISCAS
Chen Liu, Yuanqing Cheng, Ying Wang, Youguang Zhang, Weisheng Zhao
2018 J jnl
Power Supply Noise Aware Task Scheduling on Homogeneous 3D MPSoCs Considering the Thermal Constraint.
J. Comput. Sci. Technol.
Yinglin Zhao, Jianlei Yang, Weisheng Zhao, Aida Todri-Sanial, Yuanqing Cheng
2018 — conf
Write Energy Optimization for STT-MRAM Cache with Data Pattern Characterization.
ISVLSI
Bi Wu, Xiaolong Zhang, Yuanqing Cheng, Zhaohao Wang, Dijun Liu, Youguang Zhang, Weisheng Zhao
2017 — conf
Building energy-efficient multi-level cell STT-RAM caches with data compression.
ASP-DAC
Liu Liu, Ping Chi, Shuangchen Li, Yuanqing Cheng, Yuan Xie
2017 J jnl
STT-RAM Buffer Design for Precision-Tunable General-Purpose Neural Network Accelerator.
IEEE Trans. Very Large Scale Integr. Syst.
Lili Song, Ying Wang, Yinhe Han, Huawei Li, Yuanqing Cheng, Xiaowei Li
2017 A conf
Thermosiphon: A thermal aware NUCA architecture for write energy reduction of the STT-MRAM based LLCs.
ICCAD
Bi Wu, Yuanqing Cheng, Pengcheng Dai, Jianlei Yang, Youguang Zhang, Dijun Liu, Ying Wang, Weisheng Zhao
2016 J jnl
A Study of 3-D Power Delivery Networks With Multiple Clock Domains.
IEEE Trans. Very Large Scale Integr. Syst.
Aida Todri-Sanial, Yuanqing Cheng
2016 C conf
AES design improvement towards information safety.
ISCAS
Liang Wu, Xiaoxiao Wang, Xiaoying Zhao, Yuanqing Cheng, Donglin Su, Aixin Chen, Qihang Shi, Mark Tehranipoor
2016 J jnl
Alleviating Through-Silicon-Via Electromigration for 3-D Integrated Circuits Taking Advantage of Self-Healing Effect.
IEEE Trans. Very Large Scale Integr. Syst.
Yuanqing Cheng, Aida Todri-Sanial, Jianlei Yang, Weisheng Zhao
2016 C conf
An efficient all-digital IR-Drop Alarmer for DVFS-based SoC.
ISCAS
Liting Yu, Xiaoxiao Wang, Yuanqing Cheng, Xiaoying Zhao, Pengyuan Jiao, Aixin Chen, Donglin Su, LeRoy Winemberg, Mehdi Sadi, Mark Tehranipoor
2016 — conf
Architecture design with STT-RAM: Opportunities and challenges.
ASP-DAC
Ping Chi, Shuangchen Li, Yuanqing Cheng, Yu Lu, Seung-Hyuk Kang, Yuan Xie
2016 A conf
ODESY: a novel 3T-3MTJ cell design with optimized area DEnsity, scalability and latencY.
ICCAD
Linuo Xue, Yuanqing Cheng, Jianlei Yang, Peiyuan Wang, Yuan Xie
2016 J jnl
PSI Conscious Write Scheduling: Architectural Support for Reliable Power Delivery in 3-D Die-Stacked PCM.
IEEE Trans. Very Large Scale Integr. Syst.
Ying Wang, Yinhe Han, Huawei Li, Lei Zhang, Yuanqing Cheng, Xiaowei Li
2016 C conf
Quantitative evaluation of reliability and performance for STT-MRAM.
ISCAS
Liuyang Zhang, Aida Todri-Sanial, Wang Kang, Youguang Zhang, Lionel Torres, Yuanqing Cheng, Weisheng Zhao
2016 J jnl
Radiation-Induced Soft Error Analysis of STT-MRAM: A Device to Circuit Approach.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Jianlei Yang, Peiyuan Wang, Yaojun Zhang, Yuanqing Cheng, Weisheng Zhao, Yiran Chen, Hai (Helen) Li
2016 J jnl
Temperature Impact Analysis and Access Reliability Enhancement for 1T1MTJ STT-RAM.
IEEE Trans. Reliab.
Bi Wu, Yuanqing Cheng, Jianlei Yang, Aida Todri-Sanial, Weisheng Zhao
2015 C conf
A body-biasing of readout circuit for STT-RAM with improved thermal reliability.
ISCAS
Lun Yang, Yuanqing Cheng, Yuhao Wang, Hao Yu, Weisheng Zhao, Aida Todri-Sanial
2015 C conf
A case of precision-tunable STT-RAM memory design for approximate neural network.
ISCAS
Ying Wang, Lili Song, Yinhe Han, Yuanqing Cheng, Huawei Li, Xiaowei Li
2015 — conf
An architecture-level cache simulation framework supporting advanced PMA STT-MRAM.
NANOARCH
Bi Wu, Yuanqing Cheng, Ying Wang, Aida Todri-Sanial, Guangyu Sun, Lionel Torres, Weisheng Zhao
2015 — conf
Channel Modeling and Reliability Enhancement Design Techniques for STT-MRAM.
ISVLSI
Liuyang Zhang, Wang Kang, Youguang Zhang, Yuanqing Cheng, Lang Zeng, Jacques-Olivier Klein, Weisheng Zhao
2014 — conf
HARS: A High-Performance Reliable Routing Scheme for 3D NoCs.
ISVLSI
Jun Zhou, Huawei Li, Yuntan Fang, Tiancheng Wang, Yuanqing Cheng, Xiaowei Li
2014 — conf
Power supply noise-aware workload assignments for homogeneous 3D MPSoCs with thermal consideration.
ASP-DAC
Yuanqing Cheng, Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel
2013 — conf
A novel method to mitigate TSV electromigration for 3D ICs.
ISVLSI
Yuanqing Cheng, Aida Todri-Sanial, Alberto Bosio, Luigi Dillio, Patrick Girard, Arnaud Virazel, Pascal Vivet, Marc Belleville
2013 J jnl
TSV Minimization for Circuit - Partitioned 3D SoC Test Wrapper Design.
J. Comput. Sci. Technol.
Yuanqing Cheng, Lei Zhang, Yinhe Han, Xiaowei Li
2013 J jnl
Thermal-Constrained Task Allocation for Interconnect Energy Reduction in 3-D Homogeneous MPSoCs.
IEEE Trans. Very Large Scale Integr. Syst.
Yuanqing Cheng, Lei Zhang, Yinhe Han, Xiaowei Li
2011 — conf
Wrapper Chain Design for Testing TSVs Minimization in Circuit-Partitioned 3D SoC.
Asian Test Symposium
Yuanqing Cheng, Lei Zhang, Yinhe Han, Jun Liu, Xiaowei Li