Yuanlong Xiao

18 papers A* 1A 3B 2Misc 1Journal 5Unranked 6
YearRankTypeTitle / Venue / Authors
2024 J jnl
ExHiPR: Extended High-Level Partial Reconfiguration for Fast Incremental FPGA Compilation.
ACM Trans. Reconfigurable Technol. Syst.
Yuanlong Xiao, Dongjoon Park, Zeyu Jason Niu, Aditya Hota, André DeHon
2024 A conf
RapidStream IR: Infrastructure for FPGA High-Level Physical Synthesis.
ICCAD
Jason Lau, Yuanlong Xiao, Yutong Xie, Yuze Chi, Linghao Song, Shaojie Xiang, Michael Lo, Zhiru Zhang, Jason Cong, Licheng Guo
2024 J jnl
RapidStream IR: Infrastructure for FPGA High-Level Physical Synthesis.
CoRR
Jason Lau, Yuanlong Xiao, Yutong Xie, Yuze Chi, Linghao Song, Shaojie Xiang, Michael Lo, Zhiru Zhang, Jason Cong, Licheng Guo
2023 — conf
Asymmetry in Butterfly Fat Tree FPGA NoC.
ICFPT
Dongjoon Park, Zhijing Yao, Yuanlong Xiao, André DeHon
2023 J jnl
RapidStream 2.0: Automated Parallel Implementation of Latency-Insensitive FPGA Designs Through Partial Reconfiguration.
ACM Trans. Reconfigurable Technol. Syst.
Licheng Guo, Pongstorn Maidee, Yun Zhou, Chris Lavin, Eddie Hung, Wuxi Li, Jason Lau, Weikang Qiao, Yuze Chi, Linghao Song, Yuanlong Xiao, Alireza Kaviani, Zhiru Zhang, Jason Cong
2022 — conf
Fast and Flexible FPGA Development using Hierarchical Partial Reconfiguration.
FPT
Dongjoon Park, Yuanlong Xiao, André DeHon
2022 A conf
HiPR: Fast, Incremental Custom Partial Reconfiguration for HLS Developers.
FPGA
Yuanlong Xiao, André DeHon
2022 B conf
HiPR: High-level Partial Reconfiguration for Fast Incremental FPGA Compilation.
FPL
Yuanlong Xiao, Aditya Hota, Dongjoon Park, André DeHon
2022 A* conf
PLD: fast FPGA compilation to make reconfigurable acceleration compatible with modern incremental refinement software development.
ASPLOS
Yuanlong Xiao, Eric Micallef, Andrew Butt, Matthew Hofmann, Marc Alston, Matthew Goldsmith, Andrew Merczynski-Hait, André DeHon
2021 Misc conf
HLS-Compatible, Embedded-Processor Stream Links.
FCCM
Eric Micallef, Yuanlong Xiao, André DeHon
2021 J jnl
Meta-level issues in Offloading: Scoping, Composition, Development, and their Automation.
CoRR
André DeHon, Hans Giesen, Nik Sultana, Yuanlong Xiao
2020 — conf
Fast Linking of Separately-Compiled FPGA Blocks without a NoC.
FPT
Yuanlong Xiao, Syed Tousif Ahmed, André DeHon
2019 — conf
An Automatic Transistor-Level Tool for GRM FPGA Interconnect Circuits Optimization.
ACM Great Lakes Symposium on VLSI
Zhengjie Li, Yuanlong Xiao, Yufan Zhang, Yunbing Pang, Chengyu Hu, Jian Wang, Jinmei Lai
2019 — conf
Reducing FPGA Compile Time with Separate Compilation for FPGA Building Blocks.
FPT
Yuanlong Xiao, Dongjoon Park, Andrew Butt, Hans Giesen, Zhaoyang Han, Rui Ding, Nevo Magnezi, Raphael Rubin, André DeHon
2019 A conf
Transistor-Level Optimization Methodology for GRM FPGA Interconnect Circuits.
FPGA
Zhengjie Li, Yuanlong Xiao, Yufan Zhang, Yunbing Pang, Jian Wang, Jinmei Lai
2018 B conf
Case for Fast FPGA Compilation Using Partial Reconfiguration.
FPL
Dongjoon Park, Yuanlong Xiao, Nevo Magnezi, André DeHon
2016 J jnl
A universal automatic on-chip measurement of FPGA's internal setup and hold times.
IEICE Electron. Express
Yuanlong Xiao, Jian Wang, Jinmei Lai
2015 — conf
A power efficient current-mode differential driver for FPGAs.
ASICON
Yuanlong Xiao, Jian Wang, Jinmei Lai