Yuan Xie - RankMe

637 papers A* 123A 79B 10C 21Misc 11Journal 263Unranked 126

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	Hardware-Software Co-design for 3D-DRAM-based LLM Serving Accelerator. CoRR Cong Li, Yihan Yin, Chenhao Xue, Zhao Wang, Fujun Bai, Yixin Guo, Xiping Jiang, Qiang Wu, Yuan Xie, Guangyu Sun
2026	—	`conf`	PF-LLM: Large Language Model Hinted Hardware Prefetching. ASPLOS (2) Ceyu Xu, Xiangfeng Sun, Weihang Li, Chen Bai, Bangyan Wang, Mengming Li, Zhiyao Xie, Yuan Xie
2026	—	`conf`	Reconfigurable Quantum Instruction Set Computers for High Performance Attainable on Hardware. ASPLOS (2) Zhaohui Yang, Dawei Ding, Qi Ye, Cupjin Huang, Jianxin Chen, Yuan Xie
2026	J	`jnl`	STEED: Space and Time-Efficient Encrypted Database Using FHE. IEEE Trans. Dependable Secur. Comput. Fahong Zhang, Zhen Gu, Yiran Li, Yilei Wang, Cheng Hong, Zhaohui Chen, Yufei Wang, Yanheng Lu, Meng Li, Leibo Liu, Sheng Wang, Feifei Li, Chen Yang, Dimin Niu, Yuan Xie
2026	J	`jnl`	Two-stage knowledge distillation for visible-infrared person re-identification. Pattern Recognit. Jiangming Shi, Xiangbo Yin, Demao Zhang, Zhizhong Zhang, Yuan Xie, Yanyun Qu
2025	J	`jnl`	3D Guard-Layer: An Integrated Agentic AI Safety System for Edge Artificial Intelligence. CoRR Eren Kurshan, Yuan Xie, Paul Franzon
2025	J	`jnl`	A Tightly Coupled AI-ISP Vision Processor. IEEE Trans. Circuits Syst. Video Technol. Hao Zhang, Sicheng Li, Yupeng Gui, Zhiyong Li, Shusong Xu, Yanheng Lu, Dimin Niu, Hongzhong Zheng, Yen-Kuang Chen, Yuan Xie, Yibo Fan
2025	J	`jnl`	DSTC: Dual-Side Sparse Tensor Core for DNNs Acceleration on Modern GPU Architectures. IEEE Trans. Computers Chen Zhang, Yang Wang, Zhiqiang Xie, Cong Guo, Yunxin Liu, Jingwen Leng, Zhigang Ji, Yuan Xie, Ru Huang
2025	J	`jnl`	Enabling Efficient Sparse Multiplications on GPUs With Heuristic Adaptability. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jiaming Xu, Shan Huang, Jinhao Li, Guyue Huang, Yuan Xie, Yu Wang, Guohao Dai
2025	A*	`conf`	H ISCA Cong Li, Yihan Yin, Xintong Wu, Jingchen Zhu, Zhutianya Gao, Dimin Niu, Qiang Wu, Xin Si, Yuan Xie, Chen Zhang, Guangyu Sun
2025	A	`conf`	How Do Errors Impact NN Accuracy on Non-Ideal Analog PIM? Fast Evaluation via an Error-Injected Robustness Metric. ICCAD Lidong Guo, Zhenhua Zhu, Qiushi Lin, Yuan Xie, Huazhong Yang, Wangyang Fu, Yu Wang
2025	J	`jnl`	Klotski v2: Improved DNN Model Orchestration Framework for Dataflow Architecture Accelerators. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Chen Bai, Xuechao Wei, Youwei Zhuo, Yi Cai, Hongzhong Zheng, Bei Yu, Yuan Xie
2025	J	`jnl`	Leveraging 3D Technologies for Hardware Security: Opportunities and Challenges. CoRR Peng Gu, Shuangchen Li, Dylan C. Stow, Russell Barnes, Liu Liu, Yuan Xie, Eren Kursshan
2025	J	`jnl`	Matrix: Multi-Cipher Structures Dataflow for Parallel and Pipelined TFHE Accelerator. ACM Trans. Archit. Code Optim. Ling Liang, Zhen Gu, Fahong Zhang, Zhaohui Chen, Zhirui Li, Xin Fan, Dimin Niu, Meng Li, Zhiyong Li, Zongwei Wang, Hongzhong Zheng, Yimao Cai, Yuan Xie
2025	J	`jnl`	MemTunnel: A CXL-Based Rack-Scale Host Memory Pooling Architecture for Cloud Service. IEEE Trans. Parallel Distributed Syst. Tianchan Guan, Yijin Guan, Zhaoyang Du, Jiacheng Ma, Boyu Tian, Zhao Wang, Teng Ma, Zheng Liu, Yang Kong, Yuan Xie, Mingyu Gao, Guangyu Sun, Hongzhong Zheng, Dimin Niu
2025	A*	`conf`	NVMePass: A Lightweight, High-performance and Scalable NVMe Virtualization Architecture with I/O Queues Passthrough. HPCA Yiquan Chen, Zhen Jin, Yijing Wang, Yi Chen, Jiexiong Xu, Hao Yu, Jinlong Chen, Wenhai Lin, Kanghua Fang, Keyao Zhang, Chengkun Wei, Qiang Liu, Yuan Xie, Wenzhi Chen
2025	J	`jnl`	NoCFuzzer: Automating NoC Verification in UVM. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ruiyang Ma, Jiayi Huang, Shijian Zhang, Yuan Xie, Guojie Luo
2025	A*	`conf`	Push Multicast: A Speculative and Coherent Interconnect for Mitigating Manycore CPU Communication Bottleneck. HPCA Jiayi Huang, Yanhua Chen, Zhe Wang, Christopher J. Hughes, Yufei Ding, Yuan Xie
2025	A*	`conf`	REACT3D: Real-time Edge Accelerator for Incremental Training in 3D Gaussian Splatting based SLAM Systems. MICRO Hongyi Wang, Zhenhua Zhu, Tianchen Zhao, Yunfei Xiang, Zehao Wang, Jincheng Yu, Huazhong Yang, Yuan Xie, Yu Wang
2025	J	`jnl`	ReQISC: A Reconfigurable Quantum Computer Microarchitecture and Compiler Co-Design. CoRR Zhaohui Yang, Dawei Ding, Qi Ye, Cupjin Huang, Jianxin Chen, Yuan Xie
2025	J	`jnl`	SAFE: A Scalable Homomorphic Encryption Accelerator for Vertical Federated Learning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Zhaohui Chen, Zhen Gu, Yanheng Lu, Xuanle Ren, Ruiguang Zhong, Wen-jie Lu, Jiansong Zhang, Yichi Zhang, Hanghang Wu, Xiaofu Zheng, Heng Liu, Tingqiang Chu, Cheng Hong, Changzheng Wei, Dimin Niu, Yuan Xie
2025	J	`jnl`	Survey on Characterizing and Understanding GNNs From a Computer Architecture Perspective. IEEE Trans. Parallel Distributed Syst. Meng Wu, Mingyu Yan, Wenming Li, Xiaochun Ye, Dongrui Fan, Yuan Xie
2025	J	`jnl`	Switchable Token-Specific Codebook Quantization For Face Image Compression. CoRR Yongbo Wang, Haonan Wang, Guodong Mu, Ruixin Zhang, Jiaqi Chen, Jingyun Zhang, Jun Wang, Yuan Xie, Zhizhong Zhang, Shouhong Ding
2025	A*	`conf`	TRACI: Network Acceleration of Input-Dynamic Communication for Large-Scale Deep Learning Recommendation Model. ISCA Guyue Huang, Hao Li, Le Qin, Jiayi Huang, Yangwook Kang, Yufei Ding, Yuan Xie
2025	J	`jnl`	Thermal-Aware 3D Design for Side-Channel Information Leakage. CoRR Dylan C. Stow, Russell Barnes, Eren Kurshan, Yuan Xie
2025	J	`jnl`	Through Silicon Via Aware Design Planning for Thermally Efficient 3-D Integrated Circuits. CoRR Yibo Chen, Eren Kurshan, Dave Motschman, Charles Johnson, Yuan Xie
2025	A*	`conf`	UniNDP: A Unified Compilation and Simulation Tool for Near DRAM Processing Architectures. HPCA Tongxin Xie, Zhenhua Zhu, Bing Li, Yukai He, Cong Li, Guangyu Sun, Huazhong Yang, Yuan Xie, Yu Wang
2024	J	`jnl`	A Comprehensive Survey on GNN Characterization. CoRR Meng Wu, Mingyu Yan, Wenming Li, Xiaochun Ye, Dongrui Fan, Yuan Xie
2024	—	`conf`	EVT: Accelerating Deep Learning Training with Epilogue Visitor Tree. ASPLOS (3) Zhaodong Chen, Andrew Kerr, Richard Cai, Jack Kosaian, Haicheng Wu, Yufei Ding, Yuan Xie
2024	A*	`conf`	Learning Commonality, Divergence and Variety for Unsupervised Visible-Infrared Person Re-identification. NeurIPS Jiangming Shi, Xiangbo Yin, Yachao Zhang, Zhizhong Zhang, Yuan Xie, Yanyun Qu
2024	J	`jnl`	Optimizing NVMe Storage for Large-Scale Deployment: Key Technologies and Strategies in Alibaba Cloud. IEEE Micro Yiquan Chen, Yuan Xie, Yijing Wang, Jiexiong Xu, Zhen Jin, Anyu Li, Xiaoyan Fu, Qiang Liu, Wenzhi Chen
2024	—	`conf`	Salus: A Practical Trusted Execution Environment for CPU-FPGA Heterogeneous Cloud Platforms. ASPLOS (4) Yu Zou, Yiran Li, Sheng Wang, Le Su, Zhen Gu, Yanheng Lu, Yijin Guan, Dimin Niu, Mingyu Gao, Yuan Xie, Feifei Li
2024	J	`jnl`	Survey of Machine Learning for Software-assisted Hardware Design Verification: Past, Present, and Prospect. ACM Trans. Design Autom. Electr. Syst. Nan Wu, Yingjie Li, Hang Yang, Hanqiu Chen, Steve Dai, Cong Hao, Cunxi Yu, Yuan Xie
2023	J	`jnl`	A Comprehensive Survey on Distributed Training of Graph Neural Networks. Proc. IEEE Haiyang Lin, Mingyu Yan, Xiaochun Ye, Dongrui Fan, Shirui Pan, Wenguang Chen, Yuan Xie
2023	J	`jnl`	A Survey of Machine Learning for Computer Architecture and Systems. ACM Comput. Surv. Nan Wu, Yuan Xie
2023	—	`conf`	ALCOP: Automatic Load-Compute Pipelining in Deep Learning Compiler for AI-GPUs. MLSys Guyue Huang, Yang Bai, Liu Liu, Yuke Wang, Bei Yu, Yufei Ding, Yuan Xie
2023	J	`jnl`	Accelerating Distributed GNN Training by Codes. IEEE Trans. Parallel Distributed Syst. Yanhong Wang, Tianchan Guan, Dimin Niu, Qiaosha Zou, Hongzhong Zheng, Chuanjin Richard Shi, Yuan Xie
2023	A*	`conf`	ArchExplorer: Microarchitecture Exploration Via Bottleneck Analysis. MICRO Chen Bai, Jiayi Huang, Xuechao Wei, Yuzhe Ma, Sicheng Li, Hongzhong Zheng, Bei Yu, Yuan Xie
2023	A*	`conf`	CHAM: A Customized Homomorphic Encryption Accelerator for Fast Matrix-Vector Product. DAC Xuanle Ren, Zhaohui Chen, Zhen Gu, Yanheng Lu, Ruiguang Zhong, Wen-jie Lu, Jiansong Zhang, Yichi Zhang, Hanghang Wu, Xiaofu Zheng, Heng Liu, Tingqiang Chu, Cheng Hong, Changzheng Wei, Dimin Niu, Yuan Xie
2023	J	`jnl`	Comprehensive SNN Compression Using ADMM Optimization and Activity Regularization. IEEE Trans. Neural Networks Learn. Syst. Lei Deng, Yujie Wu, Yifan Hu, Ling Liang, Guoqi Li, Xing Hu, Yufei Ding, Peng Li, Yuan Xie
2023	A*	`conf`	DF-GAS: a Distributed FPGA-as-a-Service Architecture towards Billion-Scale Graph-based Approximate Nearest Neighbor Search. MICRO Shulin Zeng, Zhenhua Zhu, Jun Liu, Haoyu Zhang, Guohao Dai, Zixuan Zhou, Shuangchen Li, Xuefei Ning, Yuan Xie, Huazhong Yang, Yu Wang
2023	B	`conf`	Dynamic N: M Fine-Grained Structured Sparse Attention Mechanism. PPoPP Zhaodong Chen, Zheng Qu, Yuying Quan, Liu Liu, Yufei Ding, Yuan Xie
2023	J	`jnl`	E-Booster: A Field-Programmable Gate Array-Based Accelerator for Secure Tree Boosting Using Additively Homomorphic Encryption. IEEE Micro Guiming Wu, Qianwen He, Jiali Jiang, Zhenxiang Zhang, Yunfeng Shi, Xin Long, Linquan Jiang, Shuangchen Li, Yuan Xie, Changzheng Wei, Yuan Zhao, Ying Yan, Hui Zhang, Yinchao Zou
2023	A*	`conf`	ECSSD: Hardware/Data Layout Co-Designed In-Storage-Computing Architecture for Extreme Classification. ISCA Siqi Li, Fengbin Tu, Liu Liu, Jilan Lin, Zheng Wang, Yangwook Kang, Yufei Ding, Yuan Xie
2023	J	`jnl`	Efficient Super-Resolution System With Block-Wise Hybridization and Quantized Winograd on FPGA. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Bizhao Shi, Jiaxi Zhang, Zhuolun He, Xuechao Wei, Sicheng Li, Guojie Luo, Hongzhong Zheng, Yuan Xie
2023	J	`jnl`	Exploring Adversarial Attack in Spiking Neural Networks With Spike-Compatible Gradient. IEEE Trans. Neural Networks Learn. Syst. Ling Liang, Xing Hu, Lei Deng, Yujie Wu, Guoqi Li, Yufei Ding, Peng Li, Yuan Xie
2023	A*	`conf`	Gamora: Graph Learning based Symbolic Reasoning for Large-Scale Boolean Networks. DAC Nan Wu, Yingjie Li, Cong Hao, Steve Dai, Cunxi Yu, Yuan Xie
2023	J	`jnl`	Gamora: Graph Learning based Symbolic Reasoning for Large-Scale Boolean Networks. CoRR Nan Wu, Yingjie Li, Cong Hao, Steve Dai, Cunxi Yu, Yuan Xie
2023	A*	`conf`	HBP: Hierarchically Balanced Pruning and Accelerator Co-Design for Efficient DNN Inference. DAC Ao Ren, Yuhao Wang, Tao Zhang, Jiaxing Shi, Duo Liu, Xianzhang Chen, Yujuan Tan, Yuan Xie
2023	J	`jnl`	High-performance and Scalable Software-based NVMe Virtualization Mechanism with I/O Queues Passthrough. CoRR Yiquan Chen, Zhen Jin, Yijing Wang, Yi Chen, Hao Yu, Jiexiong Xu, Jinlong Chen, Wenhai Lin, Kanghua Fang, Chengkun Wei, Qiang Liu, Yuan Xie, Wenzhi Chen
2023	J	`jnl`	IronMan-Pro: Multiobjective Design Space Exploration in HLS via Reinforcement Learning and Graph Neural Network-Based Modeling. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Nan Wu, Yuan Xie, Cong Hao
2023	A	`conf`	Klotski: DNN Model Orchestration Framework for Dataflow Architecture Accelerators. ICCAD Chen Bai, Xuechao Wei, Youwei Zhuo, Yi Cai, Hongzhong Zheng, Bei Yu, Yuan Xie
2023	J	`jnl`	MNSIM 2.0: A Behavior-Level Modeling Tool for Processing-In-Memory Architectures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Zhenhua Zhu, Hanbo Sun, Tongxin Xie, Yu Zhu, Guohao Dai, Lixue Xia, Dimin Niu, Xiaoming Chen, Xiaobo Sharon Hu, Yu Cao, Yuan Xie, Huazhong Yang, Yu Wang
2023	J	`jnl`	NP-Hardness of Tensor Network Contraction Ordering. CoRR Jianyu Xu, Hanwen Zhang, Ling Liang, Lei Deng, Yuan Xie, Guoqi Li
2023	J	`jnl`	NPS: A Framework for Accurate Program Sampling Using Graph Neural Network. CoRR Yuanwei Fang, Zihao Liu, Yanheng Lu, Jiawei Liu, Jiajie Li, Yi Jin, Jian Chen, Yen-Kuang Chen, Hongzhong Zheng, Yuan Xie
2023	A*	`conf`	RM-STC: Row-Merge Dataflow Inspired GPU Sparse Tensor Core for Energy-Efficient Sparse Acceleration. MICRO Guyue Huang, Zhengyang Wang, Po-An Tsai, Chen Zhang, Yufei Ding, Yuan Xie
2023	J	`jnl`	ReDCIM: Reconfigurable Digital Computing- In -Memory Processor With Unified FP/INT Pipeline for Cloud AI Acceleration. IEEE J. Solid State Circuits Fengbin Tu, Yiqi Wang, Zihan Wu, Ling Liang, Yufei Ding, Bongjin Kim, Leibo Liu, Shaojun Wei, Yuan Xie, Shouyi Yin
2023	J	`jnl`	SDP: Co-Designing Algorithm, Dataflow, and Architecture for In-SRAM Sparse NN Acceleration. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Fengbin Tu, Yiqi Wang, Ling Liang, Yufei Ding, Leibo Liu, Shaojun Wei, Shouyi Yin, Yuan Xie
2023	J	`jnl`	SPCIM: Sparsity-Balanced Practical CIM Accelerator With Optimized Spatial-Temporal Multi-Macro Utilization. IEEE Trans. Circuits Syst. I Regul. Pap. Yiqi Wang, Fengbin Tu, Leibo Liu, Shaojun Wei, Yuan Xie, Shouyi Yin
2023	J	`jnl`	SPG: Structure-Private Graph Database via SqueezePIR. Proc. VLDB Endow. Ling Liang, Jilan Lin, Zheng Qu, Ishtiyaque Ahmad, Fengbin Tu, Trinabh Gupta, Yufei Ding, Yuan Xie
2023	—	`conf`	Spada: Accelerating Sparse Matrix Multiplication with Adaptive Dataflow. ASPLOS (2) Zhiyao Li, Jiaxiang Li, Taijie Chen, Dimin Niu, Hongzhong Zheng, Yuan Xie, Mingyu Gao
2023	A*	`conf`	TT-GNN: Efficient On-Chip Graph Neural Network Training via Embedding Reformation and Hardware Optimization. MICRO Zheng Qu, Dimin Niu, Shuangchen Li, Hongzhong Zheng, Yuan Xie
2023	J	`jnl`	TranCIM: Full-Digital Bitline-Transpose CIM-based Sparse Transformer Accelerator With Pipeline/Parallel Reconfigurable Modes. IEEE J. Solid State Circuits Fengbin Tu, Zihan Wu, Yiqi Wang, Ling Liang, Liu Liu, Yufei Ding, Leibo Liu, Shaojun Wei, Yuan Xie, Shouyi Yin
2022	—	`conf`	184QPS/W 64Mb/mm ISSCC Dimin Niu, Shuangchen Li, Yuhao Wang, Wei Han, Zhe Zhang, Yijin Guan, Tianchan Guan, Fei Sun, Fei Xue, Lide Duan, Yuanwei Fang, Hongzhong Zheng, Xiping Jiang, Song Wang, Fengguo Zuo, Yubing Wang, Bing Yu, Qiwei Ren, Yuan Xie
2022	A	`conf`	2022 ICCAD CAD Contest Problem C: Microarchitecture Design Space Exploration. ICCAD Sicheng Li, Chen Bai, Xuechao Wei, Bizhao Shi, Yen-Kuang Chen, Yuan Xie
2022	—	`conf`	A 28nm 15.59µJ/Token Full-Digital Bitline-Transpose CIM-Based Sparse Transformer Accelerator with Pipeline/Parallel Reconfigurable Modes. ISSCC Fengbin Tu, Zihan Wu, Yiqi Wang, Ling Liang, Liu Liu, Yufei Ding, Leibo Liu, Shaojun Wei, Yuan Xie, Shouyi Yin
2022	—	`conf`	A 28nm 29.2TFLOPS/W BF16 and 36.5TOPS/W INT8 Reconfigurable Digital CIM Processor with Unified FP/INT Pipeline and Bitwise In-Memory Booth Multiplication for Cloud Deep Learning Acceleration. ISSCC Fengbin Tu, Yiqi Wang, Zihan Wu, Ling Liang, Yufei Ding, Bongjin Kim, Leibo Liu, Shaojun Wei, Yuan Xie, Shouyi Yin
2022	J	`jnl`	A Comprehensive Survey on Distributed Training of Graph Neural Networks. CoRR Haiyang Lin, Mingyu Yan, Xiaochun Ye, Dongrui Fan, Shirui Pan, Wenguang Chen, Yuan Xie
2022	J	`jnl`	A Comprehensive and Modularized Statistical Framework for Gradient Norm Equality in Deep Neural Networks. IEEE Trans. Pattern Anal. Mach. Intell. Zhaodong Chen, Lei Deng, Bangyan Wang, Guoqi Li, Yuan Xie
2022	J	`jnl`	A Systematic View of Model Leakage Risks in Deep Neural Network Systems. IEEE Trans. Computers Xing Hu, Ling Liang, Xiaobing Chen, Lei Deng, Yu Ji, Yufei Ding, Zidong Du, Qi Guo, Timothy Sherwood, Yuan Xie
2022	A*	`conf`	A one-for-all and ASPLOS Bangyan Wang, Lei Deng, Fei Sun, Guohao Dai, Liu Liu, Yu Wang, Yuan Xie
2022	A*	`conf`	A synthesis framework for stitching surface code with superconducting quantum devices. ISCA Anbang Wu, Gushu Li, Hezi Zhang, Gian Giacomo Guerreschi, Yufei Ding, Yuan Xie
2022	C	`conf`	AI-assisted Synthesis in Next Generation EDA: Promises, Challenges, and Prospects. ICCD Nan Wu, Yuan Xie, Cong Hao
2022	J	`jnl`	Accelerating CPU-Based Sparse General Matrix Multiplication With Binary Row Merging. IEEE Access Zhaoyang Du, Yijin Guan, Tianchan Guan, Dimin Niu, Hongzhong Zheng, Yuan Xie
2022	J	`jnl`	Accelerating CPU-based Sparse General Matrix Multiplication with Binary Row Merging. CoRR Zhaoyang Du, Yijin Guan, Tianchan Guan, Dimin Niu, Hongzhong Zheng, Yuan Xie
2022	A	`conf`	Accelerating Spatiotemporal Supervised Training of Large-Scale Spiking Neural Networks on GPU. DATE Ling Liang, Zhaodong Chen, Lei Deng, Fengbin Tu, Guoqi Li, Yuan Xie
2022	J	`jnl`	Alleviating Datapath Conflicts and Design Centralization in Graph Analytics Acceleration. CoRR Haiyang Lin, Mingyu Yan, Duo Wang, Mo Zou, Fengbin Tu, Xiaochun Ye, Dongrui Fan, Yuan Xie
2022	A*	`conf`	Alleviating datapath conflicts and design centralization in graph analytics acceleration. DAC Haiyang Lin, Mingyu Yan, Duo Wang, Mo Zou, Fengbin Tu, Xiaochun Ye, Dongrui Fan, Yuan Xie
2022	A*	`conf`	AutoComm: A Framework for Enabling Efficient Communication in Distributed Quantum Programs. MICRO Anbang Wu, Hezi Zhang, Gushu Li, Alireza Shabani, Yuan Xie, Yufei Ding
2022	A*	`conf`	BEACON: Scalable Near-Data-Processing Accelerators for Genome Analysis near Memory Pool with the CXL Support. MICRO Wenqin Huangfu, Krishna T. Malladi, Andrew Chang, Yuan Xie
2022	A*	`conf`	CHEX: CHannel EXploration for CNN Model Compression. CVPR Zejiang Hou, Minghai Qin, Fei Sun, Xiaolong Ma, Kun Yuan, Yi Xu, Yen-Kuang Chen, Rong Jin, Yuan Xie, Sun-Yuan Kung
2022	J	`jnl`	CHEX: CHannel EXploration for CNN Model Compression. CoRR Zejiang Hou, Minghai Qin, Fei Sun, Xiaolong Ma, Kun Yuan, Yi Xu, Yen-Kuang Chen, Rong Jin, Yuan Xie, Sun-Yuan Kung
2022	—	`conf`	COMB-MCM: Computing-on-Memory-Boundary NN Processor with Bipolar Bitwise Sparsity Optimization for Scalable Multi-Chiplet-Module Edge Machine Learning. ISSCC Haozhe Zhu, Bo Jiao, Jinshan Zhang, Xinru Jia, Yunzhengmao Wang, Tianchan Guan, Shengcheng Wang, Dimin Niu, Hongzhong Zheng, Chixiao Chen, Mingyu Wang, Lihua Zhang, Xiaoyang Zeng, Qi Liu, Yuan Xie, Ming Liu
2022	J	`jnl`	Characterizing and Understanding HGNNs on GPUs. IEEE Comput. Archit. Lett. Mingyu Yan, Mo Zou, Xiaocheng Yang, Wenming Li, Xiaochun Ye, Dongrui Fan, Yuan Xie
2022	J	`jnl`	Characterizing and Understanding HGNNs on GPUs. CoRR Mingyu Yan, Mo Zou, Xiaocheng Yang, Wenming Li, Xiaochun Ye, Dongrui Fan, Yuan Xie
2022	B	`conf`	Compact Multi-level Sparse Neural Networks with Input Independent Dynamic Rerouting. ICTAI Minghai Qin, Tianyun Zhang, Fei Sun, Yen-Kuang Chen, Makan Fardad, Yanzhi Wang, Yuan Xie
2022	J	`jnl`	Cost-Aware Exploration for Chiplet-Based Architecture with Advanced Packaging Technologies. CoRR Tianqi Tang, Yuan Xie
2022	A*	`conf`	DIMMining: pruning-efficient and parallel graph mining on near-memory-computing. ISCA Guohao Dai, Zhenhua Zhu, Tianyu Fu, Chiyue Wei, Bangyan Wang, Xiangyu Li, Yuan Xie, Huazhong Yang, Yu Wang
2022	A*	`conf`	DOTA: detect and omit weak attentions for scalable transformer acceleration. ASPLOS Zheng Qu, Liu Liu, Fengbin Tu, Zhaodong Chen, Yufei Ding, Yuan Xie
2022	J	`jnl`	Dynamic N: M Fine-grained Structured Sparse Attention Mechanism. CoRR Zhaodong Chen, Yuying Quan, Zheng Qu, Liu Liu, Yufei Ding, Yuan Xie
2022	J	`jnl`	Dynamic Sparse Attention for Scalable Transformer Acceleration. IEEE Trans. Computers Liu Liu, Zheng Qu, Zhaodong Chen, Fengbin Tu, Yufei Ding, Yuan Xie
2022	J	`jnl`	EPQuant: A Graph Neural Network compression approach based on product quantization. Neurocomputing Linyong Huang, Zhe Zhang, Zhaoyang Du, Shuangchen Li, Hongzhong Zheng, Yuan Xie, Nianxiong Tan
2022	A*	`conf`	Effective Model Sparsification by Scheduled Grow-and-Prune Methods. ICLR Xiaolong Ma, Minghai Qin, Fei Sun, Zejiang Hou, Kun Yuan, Yi Xu, Yanzhi Wang, Yen-Kuang Chen, Rong Jin, Yuan Xie
2022	J	`jnl`	Efficient Processing of Sparse Tensor Decomposition via Unified Abstraction and PE-Interactive Architecture. IEEE Trans. Computers Bangyan Wang, Lei Deng, Zheng Qu, Shuangchen Li, Zheng Zhang, Yuan Xie
2022	J	`jnl`	Enabling Data Movement and Computation Pipelining in Deep Learning Compiler. CoRR Guyue Huang, Yang Bai, Liu Liu, Yuke Wang, Bei Yu, Yufei Ding, Yuan Xie
2022	—	`conf`	Faith: An Efficient Framework for Transformer Verification on GPUs. USENIX ATC Boyuan Feng, Tianqi Tang, Yuke Wang, Zhaodong Chen, Zheng Wang, Shu Yang, Yuan Xie, Yufei Ding
2022	J	`jnl`	Faith: An Efficient Framework for Transformer Verification on GPUs. CoRR Boyuan Feng, Tianqi Tang, Yuke Wang, Zhaodong Chen, Zheng Wang, Shu Yang, Yuan Xie, Yufei Ding
2022	J	`jnl`	H2Learn: High-Efficiency Learning Accelerator for High-Accuracy Spiking Neural Networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ling Liang, Zheng Qu, Zhaodong Chen, Fengbin Tu, Yujie Wu, Lei Deng, Guoqi Li, Peng Li, Yuan Xie
2022	J	`jnl`	HEDA: Multi-Attribute Unbounded Aggregation over Homomorphically Encrypted Database. Proc. VLDB Endow. Xuanle Ren, Le Su, Zhen Gu, Sheng Wang, Feifei Li, Yuan Xie, Song Bian, Chao Li, Fan Zhang
2022	J	`jnl`	Hardware-Enabled Efficient Data Processing With Tensor-Train Decomposition. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Zheng Qu, Lei Deng, Bangyan Wang, Hengnu Chen, Jilan Lin, Ling Liang, Guoqi Li, Zheng Zhang, Yuan Xie
2022	J	`jnl`	Heuristic Adaptability to Input Dynamics for SpMM on GPUs. CoRR Guohao Dai, Guyue Huang, Shang Yang, Zhongming Yu, Hengrui Zhang, Yufei Ding, Yuan Xie, Huazhong Yang, Yu Wang
2022	A*	`conf`	Heuristic adaptability to input dynamics for SpMM on CPUs. DAC Guohao Dai, Guyue Huang, Shang Yang, Zhongming Yu, Hengrui Zhang, Yufei Ding, Yuan Xie, Huazhong Yang, Yu Wang
2022	J	`jnl`	High-Level Synthesis Performance Prediction using GNNs: Benchmarking, Modeling, and Advancing. CoRR Nan Wu, Hang Yang, Yuan Xie, Pan Li, Cong Hao
2022	A*	`conf`	High-level synthesis performance prediction using GNNs: benchmarking, modeling, and advancing. DAC Nan Wu, Hang Yang, Yuan Xie, Pan Li, Cong Hao
2022	J	`jnl`	Hybrid Graph Models for Logic Optimization via Spatio-Temporal Information. CoRR Nan Wu, Jiwon Lee, Yuan Xie, Cong Hao
2022	A*	`conf`	Hyperscale FPGA-as-a-service architecture for large-scale distributed graph neural network. ISCA Shuangchen Li, Dimin Niu, Yuhao Wang, Wei Han, Zhe Zhang, Tianchan Guan, Yijin Guan, Heng Liu, Linyong Huang, Zhaoyang Du, Fei Xue, Yuanwei Fang, Hongzhong Zheng, Yuan Xie
2022	A*	`conf`	INSPIRE: in-storage private information retrieval via protocol and architecture co-design. ISCA Jilan Lin, Ling Liang, Zheng Qu, Ishtiyaque Ahmad, Liu Liu, Fengbin Tu, Trinabh Gupta, Yufei Ding, Yuan Xie
2022	—	`conf`	LOSTIN: Logic Optimization via Spatio-Temporal Information with Hybrid Graph Models. ASAP Nan Wu, Jiwon Lee, Yuan Xie, Cong Hao
2022	J	`jnl`	MILAN: Masked Image Pretraining on Language Assisted Representation. CoRR Zejiang Hou, Fei Sun, Yen-Kuang Chen, Yuan Xie, Sun-Yuan Kung
2022	J	`jnl`	MPU-Sim: A Simulator for In-DRAM Near-Bank Processing Architectures. IEEE Comput. Archit. Lett. Xinfeng Xie, Peng Gu, Jiayi Huang, Yufei Ding, Yuan Xie
2022	J	`jnl`	Multi-Node Acceleration for Large-Scale GCNs. IEEE Trans. Computers Gongjian Sun, Mingyu Yan, Duo Wang, Han Li, Wenming Li, Xiaochun Ye, Dongrui Fan, Yuan Xie
2022	J	`jnl`	Multi-node Acceleration for Large-scale GCNs. CoRR Gongjian Sun, Mingyu Yan, Duo Wang, Han Li, Wenming Li, Xiaochun Ye, Dongrui Fan, Yuan Xie
2022	J	`jnl`	OpSparse: A Highly Optimized Framework for Sparse General Matrix Multiplication on GPUs. IEEE Access Zhaoyang Du, Yijin Guan, Tianchan Guan, Dimin Niu, Linyong Huang, Hongzhong Zheng, Yuan Xie
2022	J	`jnl`	OpSparse: a Highly Optimized Framework for Sparse General Matrix Multiplication on GPUs. CoRR Zhaoyang Du, Yijin Guan, Tianchan Guan, Dimin Niu, Linyong Huang, Hongzhong Zheng, Yuan Xie
2022	A*	`conf`	Paulihedral: a generalized block-wise compiler optimization framework for Quantum simulation kernels. ASPLOS Gushu Li, Anbang Wu, Yunong Shi, Ali Javadi-Abhari, Yufei Ding, Yuan Xie
2022	J	`jnl`	Practical Near-Data-Processing Architecture for Large-Scale Distributed Graph Neural Network. IEEE Access Linyong Huang, Zhe Zhang, Shuangchen Li, Dimin Niu, Yijin Guan, Hongzhong Zheng, Yuan Xie
2022	B	`conf`	Predicting the Output Structure of Sparse Matrix Multiplication with Sampled Compression Ratio. ICPADS Zhaoyang Du, Yijin Guan, Tianchan Guan, Dimin Niu, Nianxiong Tan, Xiaopeng Yu, Hongzhong Zheng, Jianyi Meng, Xiaolang Yan, Yuan Xie
2022	J	`jnl`	Predicting the Output Structure of Sparse Matrix Multiplication with Sampled Compression Ratio. CoRR Zhaoyang Du, Yijin Guan, Tianchan Guan, Dimin Niu, Nianxiong Tan, Xiaopeng Yu, Hongzhong Zheng, Jianyi Meng, Xiaolang Yan, Yuan Xie
2022	J	`jnl`	Rubik: A Hierarchical Architecture for Efficient Graph Neural Network Training. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Xiaobing Chen, Yuke Wang, Xinfeng Xie, Xing Hu, Abanti Basak, Ling Liang, Mingyu Yan, Lei Deng, Yufei Ding, Zidong Du, Yuan Xie
2022	J	`jnl`	STPAcc: Structural TI-Based Pruning for Accelerating Distance-Related Algorithms on CPU-FPGA Platforms. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yuke Wang, Boyuan Feng, Gushu Li, Lei Deng, Yuan Xie, Yufei Ding
2022	J	`jnl`	SaARSP: An Architecture for Systolic-Array Acceleration of Recurrent Spiking Neural Networks. ACM J. Emerg. Technol. Comput. Syst. Jeong-Jun Lee, Wenrui Zhang, Yuan Xie, Peng Li
2022	J	`jnl`	Shfl-BW: Accelerating Deep Neural Network Inference with Tensor-Core Aware Weight Pruning. CoRR Guyue Huang, Haoran Li, Minghai Qin, Fei Sun, Yufei Ding, Yuan Xie
2022	A*	`conf`	Shfl-BW: accelerating deep neural network inference with tensor-core aware weight pruning. DAC Guyue Huang, Haoran Li, Minghai Qin, Fei Sun, Yufei Ding, Yuan Xie
2022	A*	`conf`	Survey on Graph Neural Network Acceleration: An Algorithmic Perspective. IJCAI Xin Liu, Mingyu Yan, Lei Deng, Guoqi Li, Xiaochun Ye, Dongrui Fan, Shirui Pan, Yuan Xie
2022	J	`jnl`	Survey on Graph Neural Network Acceleration: An Algorithmic Perspective. CoRR Xin Liu, Mingyu Yan, Lei Deng, Guoqi Li, Xiaochun Ye, Dongrui Fan, Shirui Pan, Yuan Xie
2022	J	`jnl`	The Spike Gating Flow: A Hierarchical Structure Based Spiking Neural Network for Online Gesture Recognition. CoRR Zihao Zhao, Yanhong Wang, Qiaosha Zou, Tie Xu, Fangbo Tao, Jiansong Zhang, Xiaoan Wang, Chuanjin Richard Shi, Junwen Luo, Yuan Xie
2022	A*	`conf`	Toward Robust Spiking Neural Network Against Adversarial Perturbation. NeurIPS Ling Liang, Kaidi Xu, Xing Hu, Lei Deng, Yuan Xie
2022	J	`jnl`	Toward Robust Spiking Neural Network Against Adversarial Perturbation. CoRR Ling Liang, Kaidi Xu, Xing Hu, Lei Deng, Yuan Xie
2022	—	`conf`	Understanding GNN Computational Graph: A Coordinated Computation, IO, and Memory Perspective. MLSys Hengrui Zhang, Zhongming Yu, Guohao Dai, Guyue Huang, Yufei Ding, Yuan Xie, Yu Wang
2021	J	`jnl`	A Case for 3D Integrated System Design for Neuromorphic Computing & AI Applications. CoRR Eren Kurshan, Hai Helen Li, Mingoo Seok, Yuan Xie
2021	J	`jnl`	A Novel, Efficient Implementation of a Local Binary Convolutional Neural Network. IEEE Trans. Circuits Syst. II Express Briefs Ing-Chao Lin, Chi-Huan Tang, Chi-Ting Ni, Xing Hu, Yu-Tong Shen, Pei-Yin Chen, Yuan Xie
2021	J	`jnl`	A Survey of Machine Learning for Computer Architecture and Systems. CoRR Nan Wu, Yuan Xie
2021	A	`conf`	Brain-Inspired Computing: Adventure from Beyond CMOS Technologies to Beyond von Neumann Architectures ICCAD Special Session Paper. ICCAD Hussam Amrouch, Jian-Jia Chen, Kaushik Roy, Yuan Xie, Indranil Chakraborty, Wenqin Huangfu, Ling Liang, Fengbin Tu, Cheng Wang, Mikail Yayla
2021	J	`jnl`	Compact Multi-level Sparse Neural Networks with Input Independent Dynamic Rerouting. CoRR Minghai Qin, Tianyun Zhang, Fei Sun, Yen-Kuang Chen, Makan Fardad, Yanzhi Wang, Yuan Xie
2021	J	`jnl`	Core Placement Optimization for Multi-chip Many-core Neural Network Systems with Reinforcement Learning. ACM Trans. Design Autom. Electr. Syst. Nan Wu, Lei Deng, Guoqi Li, Yuan Xie
2021	J	`jnl`	DLUX: A LUT-Based Near-Bank Accelerator for Data Center Deep Learning Training Workloads. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Peng Gu, Xinfeng Xie, Shuangchen Li, Dimin Niu, Hongzhong Zheng, Krishna T. Malladi, Yuan Xie
2021	B	`conf`	EGEMM-TC: accelerating scientific computing on tensor cores with extended precision. PPoPP Boyuan Feng, Yuke Wang, Guoyang Chen, Weifeng Zhang, Yuan Xie, Yufei Ding
2021	A*	`conf`	ENMC: Extreme Near-Memory Classification via Approximate Screening. MICRO Liu Liu, Jilan Lin, Zheng Qu, Yufei Ding, Yuan Xie
2021	J	`jnl`	Effective Model Sparsification by Scheduled Grow-and-Prune Methods. CoRR Xiaolong Ma, Minghai Qin, Fei Sun, Zejiang Hou, Kun Yuan, Yi Xu, Yanzhi Wang, Yen-Kuang Chen, Rong Jin, Yuan Xie
2021	J	`jnl`	Effective and Efficient Batch Normalization Using a Few Uncorrelated Data for Statistics Estimation. IEEE Trans. Neural Networks Learn. Syst. Zhaodong Chen, Lei Deng, Guoqi Li, Jiawei Sun, Xing Hu, Ling Liang, Yufei Ding, Yuan Xie
2021	J	`jnl`	Efficient Sparse Matrix Kernels based on Adaptive Workload-Balancing and Parallel-Reduction. CoRR Guyue Huang, Guohao Dai, Yu Wang, Yufei Ding, Yuan Xie
2021	A	`conf`	Efficient tensor core-based GPU kernels for structured sparsity under reduced precision. SC Zhaodong Chen, Zheng Qu, Liu Liu, Yufei Ding, Yuan Xie
2021	J	`jnl`	Erratum to "Evolver: a Deep Learning Processor With On-Device Quantization-Voltage-Frequency Tuning". IEEE J. Solid State Circuits Fengbin Tu, Weiwei Wu, Yang Wang, Hongjiang Chen, Feng Xiong, Man Shi, Ning Li, Jinyi Deng, Tianbao Chen, Leibo Liu, Shaojun Wei, Yuan Xie, Shouyi Yin
2021	J	`jnl`	Evolver: A Deep Learning Processor With On-Device Quantization-Voltage-Frequency Tuning. IEEE J. Solid State Circuits Fengbin Tu, Weiwei Wu, Yang Wang, Hongjiang Chen, Feng Xiong, Man Shi, Ning Li, Jinyi Deng, Tianbao Chen, Leibo Liu, Shaojun Wei, Yuan Xie, Shouyi Yin
2021	J	`jnl`	Fast Search of the Optimal Contraction Sequence in Tensor Networks. IEEE J. Sel. Top. Signal Process. Ling Liang, Jianyu Xu, Lei Deng, Mingyu Yan, Xing Hu, Zheng Zhang, Guoqi Li, Yuan Xie
2021	A*	`conf`	GNNAdvisor: An Adaptive and Efficient Runtime System for GNN Acceleration on GPUs. OSDI Yuke Wang, Boyuan Feng, Gushu Li, Shuangchen Li, Lei Deng, Yuan Xie, Yufei Ding
2021	J	`jnl`	H2Learn: High-Efficiency Learning Accelerator for High-Accuracy Spiking Neural Networks. CoRR Ling Liang, Zheng Qu, Zhaodong Chen, Fengbin Tu, Yujie Wu, Lei Deng, Guoqi Li, Peng Li, Yuan Xie
2021	J	`jnl`	Hardware Acceleration for GCNs via Bidirectional Fusion. IEEE Comput. Archit. Lett. Han Li, Mingyu Yan, Xiaocheng Yang, Lei Deng, Wenming Li, Xiaochun Ye, Dongrui Fan, Yuan Xie
2021	—	`conf`	IRONMAN: GNN-assisted Design Space Exploration in High-Level Synthesis via Reinforcement Learning. ACM Great Lakes Symposium on VLSI Nan Wu, Yuan Xie, Cong Hao
2021	A*	`conf`	Improving Streaming Graph Processing Performance using Input Knowledge. MICRO Abanti Basak, Zheng Qu, Jilan Lin, Alaa R. Alameldeen, Zeshan Chishti, Yufei Ding, Yuan Xie
2021	J	`jnl`	IronMan: GNN-assisted Design Space Exploration in High-Level Synthesis via Reinforcement Learning. CoRR Nan Wu, Yuan Xie, Cong Hao
2021	J	`jnl`	Load-balanced Gather-scatter Patterns for Sparse Deep Neural Networks. CoRR Fei Sun, Minghai Qin, Tianyun Zhang, Xiaolong Ma, Haoran Li, Junwen Luo, Zihao Zhao, Yen-Kuang Chen, Yuan Xie
2021	J	`jnl`	MPU: Towards Bandwidth-abundant SIMT Processor via Near-bank Computing. CoRR Xinfeng Xie, Peng Gu, Yufei Ding, Dimin Niu, Hongzhong Zheng, Yuan Xie
2021	J	`jnl`	Mapping Surface Code to Superconducting Quantum Processors. CoRR Anbang Wu, Gushu Li, Hezi Zhang, Gian Giacomo Guerreschi, Yufei Ding, Yuan Xie
2021	J	`jnl`	Mitigating Noise-Induced Gradient Vanishing in Variational Quantum Algorithm Training. CoRR Anbang Wu, Gushu Li, Yufei Ding, Yuan Xie
2021	A*	`conf`	NeuroMeter: An Integrated Power, Area, and Timing Modeling Framework for Machine Learning Accelerators Industry Track Paper. HPCA Tianqi Tang, Sheng Li, Lifeng Nai, Norman P. Jouppi, Yuan Xie
2021	—	`conf`	On the Co-Design of Quantum Software and Hardware. NANOCOM Gushu Li, Anbang Wu, Yunong Shi, Ali Javadi-Abhari, Yufei Ding, Yuan Xie
2021	A	`conf`	Overcoming the Memory Hierarchy Inefficiencies in Graph Processing Applications. ICCAD Jilan Lin, Shuangchen Li, Yufei Ding, Yuan Xie
2021	—	`conf`	Palleon: A Runtime System for Efficient Video Processing toward Dynamic Class Skew. USENIX ATC Boyuan Feng, Yuke Wang, Gushu Li, Yuan Xie, Yufei Ding
2021	J	`jnl`	Practical Attacks on Deep Neural Networks by Memory Trojaning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Xing Hu, Yang Zhao, Lei Deng, Ling Liang, Pengfei Zuo, Jing Ye, Yingyan Lin, Yuan Xie
2021	J	`jnl`	Program-to-Circuit: Exploiting GNNs for Program Representation and Circuit Translation. CoRR Nan Wu, Huake He, Yuan Xie, Pan Li, Cong Hao
2021	J	`jnl`	QECV: Quantum Error Correction Verification. CoRR Anbang Wu, Gushu Li, Hezi Zhang, Gian Giacomo Guerreschi, Yuan Xie, Yufei Ding
2021	J	`jnl`	Recap of the 39th Edition of the International Conference on Computer-Aided Design (ICCAD 2020). IEEE Des. Test Yuan Xie
2021	J	`jnl`	Rescuing RRAM-Based Computing From Static and Dynamic Faults. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jilan Lin, Cheng-Da Wen, Xing Hu, Tianqi Tang, Ing-Chao Lin, Yu Wang, Yuan Xie
2021	A*	`conf`	SEALing Neural Network Models in Encrypted Deep Learning Accelerators. DAC Pengfei Zuo, Yu Hua, Ling Liang, Xinfeng Xie, Xing Hu, Yuan Xie
2021	A*	`conf`	SpaceA: Sparse Matrix Vector Multiplication on Processing-in-Memory Accelerator. HPCA Xinfeng Xie, Zheng Liang, Peng Gu, Abanti Basak, Lei Deng, Ling Liang, Xing Hu, Yuan Xie
2021	J	`jnl`	Tensor train decomposition for solving large-scale linear equations. Neurocomputing Hengnu Chen, Lei Deng, Zheng Qu, Ling Liang, Tianyi Yan, Yuan Xie, Guoqi Li
2021	B	`conf`	TiAcc: Triangle-inequality based Hardware Accelerator for K-means on FPGAs. CCGRID Yuke Wang, Boyuan Feng, Gushu Li, Georgios Tzimpragos, Lei Deng, Yuan Xie, Yufei Ding
2021	J	`jnl`	Towards Efficient Ansatz Architecture for Variational Quantum Algorithms. CoRR Anbang Wu, Gushu Li, Yuke Wang, Boyuan Feng, Yufei Ding, Yuan Xie
2021	J	`jnl`	Training and inference for integer-based semantic segmentation network. Neurocomputing Jiayi Yang, Lei Deng, Yukuan Yang, Yuan Xie, Guoqi Li
2021	J	`jnl`	Transformer Acceleration with Dynamic Sparse Attention. CoRR Liu Liu, Zheng Qu, Zhaodong Chen, Yufei Ding, Yuan Xie
2021	J	`jnl`	Understanding GNN Computational Graph: A Coordinated Computation, IO, and Memory Perspective. CoRR Hengrui Zhang, Zhongming Yu, Guohao Dai, Guyue Huang, Yufei Ding, Yuan Xie, Yu Wang
2021	J	`jnl`	Π-RT: A Runtime Framework to Enable Energy-Efficient Real-Time Robotic Vision Applications on Heterogeneous Architectures. Computer Liu Liu, Jie Tang, Shaoshan Liu, Bo Yu, Yuan Xie, Jean-Luc Gaudiot
2020	J	`jnl`	A Case for 3D Integrated System Design for Neuromorphic Computing and AI Applications. Int. J. Semantic Comput. Eren Kurshan, Hai Li, Mingoo Seok, Yuan Xie
2020	J	`jnl`	A Comprehensive and Modularized Statistical Framework for Gradient Norm Equality in Deep Neural Networks. CoRR Zhaodong Chen, Lei Deng, Bangyan Wang, Guoqi Li, Yuan Xie
2020	A*	`conf`	Boosting Deep Neural Network Efficiency with Dual-Module Inference. ICML Liu Liu, Lei Deng, Zhaodong Chen, Yuke Wang, Shuangchen Li, Jingwei Zhang, Yihua Yang, Zhenyu Gu, Yufei Ding, Yuan Xie
2020	J	`jnl`	Characterizing and Understanding GCNs on GPU. IEEE Comput. Archit. Lett. Mingyu Yan, Zhaodong Chen, Lei Deng, Xiaochun Ye, Zhimin Zhang, Dongrui Fan, Yuan Xie
2020	J	`jnl`	Characterizing and Understanding GCNs on GPU. CoRR Mingyu Yan, Zhaodong Chen, Lei Deng, Xiaochun Ye, Zhimin Zhang, Dongrui Fan, Yuan Xie
2020	J	`jnl`	Comparing SNNs and RNNs on Neuromorphic Vision Datasets: Similarities and Differences. CoRR Weihua He, Yujie Wu, Lei Deng, Guoqi Li, Haoyu Wang, Yang Tian, Wei Ding, Wenhui Wang, Yuan Xie
2020	J	`jnl`	Comparing SNNs and RNNs on neuromorphic vision datasets: Similarities and differences. Neural Networks Weihua He, Yujie Wu, Lei Deng, Guoqi Li, Haoyu Wang, Yang Tian, Wei Ding, Wenhui Wang, Yuan Xie
2020	J	`jnl`	Computation on Sparse Neural Networks: an Inspiration for Future Hardware. CoRR Fei Sun, Minghai Qin, Tianyun Zhang, Liu Liu, Yen-Kuang Chen, Yuan Xie
2020	J	`jnl`	Crane: Mitigating Accelerator Under-utilization Caused by Sparsity Irregularities in CNNs. IEEE Trans. Computers Yijin Guan, Guangyu Sun, Zhihang Yuan, Xingchen Li, Ningyi Xu, Shu Chen, Jason Cong, Yuan Xie
2020	A*	`conf`	DARB: A Density-Adaptive Regular-Block Pruning for Deep Neural Networks. AAAI Ao Ren, Tao Zhang, Yuhao Wang, Sheng Lin, Peiyan Dong, Yen-Kuang Chen, Yuan Xie, Yanzhi Wang
2020	A*	`conf`	DUET: Boosting Deep Neural Network Efficiency on Dual-Module Architecture. MICRO Liu Liu, Zheng Qu, Lei Deng, Fengbin Tu, Shuangchen Li, Xing Hu, Zhenyu Gu, Yufei Ding, Yuan Xie
2020	A*	`conf`	DeepSniffer: A DNN Model Extraction Framework Based on Learning Architectural Hints. ASPLOS Xing Hu, Ling Liang, Shuangchen Li, Lei Deng, Pengfei Zuo, Yu Ji, Xinfeng Xie, Yufei Ding, Chang Liu, Timothy Sherwood, Yuan Xie
2020	A*	`conf`	Eliminating Redundant Computation in Noisy Quantum Computing Simulation. DAC Gushu Li, Yufei Ding, Yuan Xie
2020	J	`jnl`	Exploring Adversarial Attack in Spiking Neural Networks with Spike-Compatible Gradient. CoRR Ling Liang, Xing Hu, Lei Deng, Yujie Wu, Guoqi Li, Yufei Ding, Peng Li, Yuan Xie
2020	A*	`conf`	Fulcrum: A Simplified Control and Access Mechanism Toward Flexible and Practical In-Situ Accelerators. HPCA Marzieh Lenjani, Patricia Gonzalez-Guerrero, Elaheh Sadredini, Shuangchen Li, Yuan Xie, Ameen Akel, Sean Eilert, Mircea R. Stan, Kevin Skadron
2020	J	`jnl`	GNNAdvisor: An Efficient Runtime System for GNN Acceleration on GPUs. CoRR Yuke Wang, Boyuan Feng, Gushu Li, Shuangchen Li, Lei Deng, Yuan Xie, Yufei Ding
2020	A*	`conf`	HyGCN: A GCN Accelerator with Hybrid Architecture. HPCA Mingyu Yan, Lei Deng, Xing Hu, Ling Liang, Yujing Feng, Xiaochun Ye, Zhimin Zhang, Dongrui Fan, Yuan Xie
2020	J	`jnl`	HyGCN: A GCN Accelerator with Hybrid Architecture. CoRR Mingyu Yan, Lei Deng, Xing Hu, Ling Liang, Yujing Feng, Xiaochun Ye, Zhimin Zhang, Dongrui Fan, Yuan Xie
2020	A*	`conf`	INVITED: Computation on Sparse Neural Networks and its Implications for Future Hardware. DAC Fei Sun, Minghai Qin, Tianyun Zhang, Liu Liu, Yen-Kuang Chen, Yuan Xie
2020	—	`conf`	MNSIM 2.0: A Behavior-Level Modeling Tool for Memristor-based Neuromorphic Computing Systems. ACM Great Lakes Symposium on VLSI Zhenhua Zhu, Hanbo Sun, Kaizhong Qiu, Lixue Xia, Gokul Krishnan, Guohao Dai, Dimin Niu, Xiaoming Chen, Xiaobo Sharon Hu, Yu Cao, Yuan Xie, Yu Wang, Huazhong Yang
2020	J	`jnl`	Memristor Hardware-Friendly Reinforcement Learning. CoRR Nan Wu, Adrien F. Vincent, Dmitri B. Strukov, Yuan Xie
2020	J	`jnl`	Model Compression and Hardware Acceleration for Neural Networks: A Comprehensive Survey. Proc. IEEE Lei Deng, Guoqi Li, Song Han, Luping Shi, Yuan Xie
2020	A	`conf`	NEST: DIMM based Near-Data-Processing Accelerator for K-mer Counting. ICCAD Wenqin Huangfu, Krishna T. Malladi, Shuangchen Li, Peng Gu, Yuan Xie
2020	J	`jnl`	NMTSim: Transaction-Command Based Simulator for New Memory Technology Devices. IEEE Comput. Archit. Lett. Peng Gu, Benjamin S. Lim, Wenqin Huangfu, Krishna T. Malladi, Andrew Chang, Yuan Xie
2020	J	`jnl`	NNBench-X: A Benchmarking Methodology for Neural Network Accelerator Designs. ACM Trans. Archit. Code Optim. Xinfeng Xie, Xing Hu, Peng Gu, Shuangchen Li, Yu Ji, Yuan Xie
2020	J	`jnl`	Projection-based runtime assertions for testing and debugging Quantum programs. Proc. ACM Program. Lang. Gushu Li, Li Zhou, Nengkun Yu, Yufei Ding, Mingsheng Ying, Yuan Xie
2020	J	`jnl`	Rethinking the performance comparison between SNNS and ANNS. Neural Networks Lei Deng, Yujie Wu, Xing Hu, Ling Liang, Yufei Ding, Guoqi Li, Guangshe Zhao, Peng Li, Yuan Xie
2020	J	`jnl`	Rubik: A Hierarchical Architecture for Efficient Graph Learning. CoRR Xiaobing Chen, Yuke Wang, Xinfeng Xie, Xing Hu, Abanti Basak, Ling Liang, Mingyu Yan, Lei Deng, Yufei Ding, Zidong Du, Yunji Chen, Yuan Xie
2020	B	`conf`	SAGA-Bench: Software and Hardware Characterization of Streaming Graph Analytics Workloads. ISPASS Abanti Basak, Jilan Lin, Ryan Lorica, Xinfeng Xie, Zeshan Chishti, Alaa R. Alameldeen, Yuan Xie
2020	J	`jnl`	SEALing Neural Network Models in Secure Deep Learning Accelerators. CoRR Pengfei Zuo, Yu Hua, Ling Liang, Xinfeng Xie, Xing Hu, Yuan Xie
2020	J	`jnl`	Scanning the Issue. Proc. IEEE H.-S. Philip Wong, Kerem Akarvardar, Dimitri A. Antoniadis, Jeffrey Bokor, Chenming Hu, Tsu-Jae King Liu, Subhasish Mitra, James D. Plummer, Sayeef S. Salahuddin, Lei Deng, Xin-Guo Li, Song Han, Luping Shi, Yuan Xie, Elias Yaacoub, Mohamed-Slim Alouini, Ahmed Douik, Hayssam Dahrouj, Tareq Y. Al-Naffouri
2020	J	`jnl`	SemiMap: A Semi-Folded Convolution Mapping for Speed-Overhead Balance on Crossbars. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Lei Deng, Yuan Xie, Ling Liang, Guanrui Wang, Liang Chang, Xing Hu, Xin Ma, Liu Liu, Jing Pei, Guoqi Li
2020	A*	`conf`	SmartExchange: Trading Higher-cost Memory Storage/Access for Lower-cost Computation. ISCA Yang Zhao, Xiaohan Chen, Yue Wang, Chaojian Li, Haoran You, Yonggan Fu, Yuan Xie, Zhangyang Wang, Yingyan Lin
2020	J	`jnl`	SmartExchange: Trading Higher-cost Memory Storage/Access for Lower-cost Computation. CoRR Yang Zhao, Xiaohan Chen, Yue Wang, Chaojian Li, Haoran You, Yonggan Fu, Yuan Xie, Zhangyang Wang, Yingyan Lin
2020	J	`jnl`	TIMELY: Pushing Data Movements and Interfaces in PIM Accelerators Towards Local and in Time Domain. CoRR Weitao Li, Pengfei Xu, Yang Zhao, Haitong Li, Yuan Xie, Yingyan Lin
2020	A*	`conf`	Taming Unstructured Sparsity on GPUs via Latency-Aware Optimization. DAC Maohua Zhu, Yuan Xie
2020	J	`jnl`	Tianjic: A Unified and Scalable Chip Bridging Spike-Based and Continuous Neural Computation. IEEE J. Solid State Circuits Lei Deng, Guanrui Wang, Guoqi Li, Shuangchen Li, Ling Liang, Maohua Zhu, Yujie Wu, Zheyu Yang, Zhe Zou, Jing Pei, Zhenzhi Wu, Xing Hu, Yufei Ding, Wei He, Yuan Xie, Luping Shi
2020	A*	`conf`	Timely: Pushing Data Movements And Interfaces In Pim Accelerators Towards Local And In Time Domain. ISCA Weitao Li, Pengfei Xu, Yang Zhao, Haitong Li, Yuan Xie, Yingyan Lin
2020	A*	`conf`	Towards Efficient Superconducting Quantum Processor Architecture Design. ASPLOS Gushu Li, Yufei Ding, Yuan Xie
2020	J	`jnl`	Training and Inference for Integer-Based Semantic Segmentation Network. CoRR Jiayi Yang, Lei Deng, Yukuan Yang, Yuan Xie, Guoqi Li
2020	J	`jnl`	Training high-performance and large-scale deep neural networks with full 8-bit integers. Neural Networks Yukuan Yang, Lei Deng, Shuang Wu, Tianyi Yan, Yuan Xie, Guoqi Li
2020	A*	`conf`	Xuantie-910: A Commercial Multi-Core 12-Stage Pipeline Out-of-Order 64-bit High Performance RISC-V Processor with Vector Extension : Industrial Product. ISCA Chen Chen, Xiaoyan Xiang, Chang Liu, Yunhai Shang, Ren Guo, Dongqi Liu, Yimin Lu, Ziyi Hao, Jiahui Luo, Zhijian Chen, Chunqiang Li, Yu Pu, Jianyi Meng, Xiaolang Yan, Yuan Xie, Xiaoning Qi
2020	—	`conf`	Xuantie-910: Innovating Cloud and Edge Computing by RISC-V. Hot Chips Symposium Chen Chen, Xiaoyan Xiang, Chang Liu, Yunhai Shang, Ren Guo, Dongqi Liu, Yimin Lu, Ziyi Hao, Jiahui Luo, Zhijian Chen, Chunqiang Li, Yu Pu, Jianyi Meng, Xiaolang Yan, Yuan Xie, Xiaoning Qi
2020	A	`conf`	fuseGNN: Accelerating Graph Convolutional Neural Network Training on GPGPU. ICCAD Zhaodong Chen, Mingyu Yan, Maohua Zhu, Lei Deng, Guoqi Li, Shuangchen Li, Yuan Xie
2020	A*	`conf`	iPIM: Programmable In-Memory Image Processing Accelerator Using Near-Bank Architecture. ISCA Peng Gu, Xinfeng Xie, Yufei Ding, Guoyang Chen, Weifeng Zhang, Dimin Niu, Yuan Xie
2019	J	`jnl`	A Secure and Persistent Memory System for Non-volatile Memory. CoRR Pengfei Zuo, Yu Hua, Yuan Xie
2019	J	`jnl`	AccD: A Compiler-based Framework for Accelerating Distance-related Algorithms on CPU-FPGA Platforms. CoRR Yuke Wang, Boyuan Feng, Gushu Li, Lei Deng, Yuan Xie, Yufei Ding
2019	A*	`conf`	Alleviating Irregularity in Graph Analytics Acceleration: a Hardware/Software Co-Design Approach. MICRO Mingyu Yan, Xing Hu, Shuangchen Li, Abanti Basak, Han Li, Xin Ma, Itir Akgun, Yujing Feng, Peng Gu, Lei Deng, Xiaochun Ye, Zhimin Zhang, Dongrui Fan, Yuan Xie
2019	A*	`conf`	Analysis and Optimization of the Memory Hierarchy for Graph Processing Workloads. HPCA Abanti Basak, Shuangchen Li, Xing Hu, Sang Min Oh, Xinfeng Xie, Li Zhao, Xiaowei Jiang, Yuan Xie
2019	A	`conf`	Balancing Memory Accesses for Energy-Efficient Graph Analytics Accelerators. ISLPED Mingyu Yan, Xing Hu, Shuangchen Li, Itir Akgun, Han Li, Xin Ma, Lei Deng, Xiaochun Ye, Zhimin Zhang, Dongrui Fan, Yuan Xie
2019	—	`conf`	CNNWire: Boosting Convolutional Neural Network with Winograd on ReRAM based Accelerators. ACM Great Lakes Symposium on VLSI Jilan Lin, Shuangchen Li, Xing Hu, Lei Deng, Yuan Xie
2019	A	`conf`	CORN: In-Buffer Computing for Binary Neural Network. DATE Liang Chang, Xin Ma, Zhaohao Wang, Youguang Zhang, Weisheng Zhao, Yuan Xie
2019	—	`conf`	CRISP: Center for Research on Intelligent Storage and Processing-in-Memory. VLSI-DAT Yuan Xie
2019	J	`jnl`	Comprehensive SNN Compression Using ADMM Optimization and Activity Regularization. CoRR Lei Deng, Yujie Wu, Yifan Hu, Ling Liang, Guoqi Li, Xing Hu, Yufei Ding, Peng Li, Yuan Xie
2019	J	`jnl`	DARB: A Density-Aware Regular-Block Pruning for Deep Neural Networks. CoRR Ao Ren, Tao Zhang, Yuhao Wang, Sheng Lin, Peiyan Dong, Yen-Kuang Chen, Yuan Xie, Yanzhi Wang
2019	J	`jnl`	DASM: Data-Streaming-Based Computing in Nonvolatile Memory Architecture for Embedded System. IEEE Trans. Very Large Scale Integr. Syst. Liang Chang, Xin Ma, Zhaohao Wang, Youguang Zhang, Yufei Ding, Weisheng Zhao, Yuan Xie
2019	A*	`conf`	Direct Training for Spiking Neural Networks: Faster, Larger, Better. AAAI Yujie Wu, Lei Deng, Guoqi Li, Jun Zhu, Yuan Xie, Luping Shi
2019	—	`conf`	Dynamic Sparse Graph for Efficient Deep Learning. ICLR (Poster) Liu Liu, Lei Deng, Xing Hu, Maohua Zhu, Guoqi Li, Yufei Ding, Yuan Xie
2019	A*	`conf`	Efficient System Architecture in the Era of Monolithic 3D: Dynamic Inter-tier Interconnect and Processing-in-Memory. DAC Dylan C. Stow, Itir Akgun, Wenqin Huangfu, Yuan Xie, Xueqi Li, Gabriel H. Loh
2019	J	`jnl`	Emerging Memory Technologies. IEEE Micro Yuan Xie, Jishen Zhao
2019	A*	`conf`	FPSA: A Full System Stack Solution for Reconfigurable ReRAM-based NN Accelerator Architecture. ASPLOS Yu Ji, Youyang Zhang, Xinfeng Xie, Shuangchen Li, Peiqi Wang, Xing Hu, Youhui Zhang, Yuan Xie
2019	J	`jnl`	FPSA: A Full System Stack Solution for Reconfigurable ReRAM-based NN Accelerator Architecture. CoRR Yu Ji, Youyang Zhang, Xinfeng Xie, Shuangchen Li, Peiqi Wang, Xing Hu, Youhui Zhang, Yuan Xie
2019	J	`jnl`	GraphH: A Processing-in-Memory Architecture for Large-Scale Graph Processing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Guohao Dai, Tianhao Huang, Yuze Chi, Jishen Zhao, Guangyu Sun, Yongpan Liu, Yu Wang, Yuan Xie, Huazhong Yang
2019	—	`conf`	Investigation of Cost-Optimal Network-on-Chip for Passive and Active Interposer Systems. SLIP Dylan C. Stow, Itir Akgun, Yuan Xie
2019	J	`jnl`	L1-Norm Batch Normalization for Efficient Training of Deep Neural Networks. IEEE Trans. Neural Networks Learn. Syst. Shuang Wu, Guoqi Li, Lei Deng, Liu Liu, Dong Wu, Yuan Xie, Luping Shi
2019	—	`conf`	Learning the sparsity for ReRAM: mapping and pruning sparse neural network for ReRAM based accelerator. ASP-DAC Jilan Lin, Zhenhua Zhu, Yu Wang, Yuan Xie
2019	A*	`conf`	MEDAL: Scalable DIMM based Near Data Processing Accelerator for DNA Seeding Algorithm. MICRO Wenqin Huangfu, Xueqi Li, Shuangchen Li, Xing Hu, Peng Gu, Yuan Xie
2019	A	`conf`	Memory Trojan Attack on Neural Network Accelerators. DATE Yang Zhao, Xing Hu, Shuangchen Li, Jing Ye, Lei Deng, Yu Ji, Jianyu Xu, Dong Wu, Yuan Xie
2019	A*	`conf`	Memory-Bound Proof-of-Work Acceleration for Blockchain Applications. DAC Kun Wu, Guohao Dai, Xing Hu, Shuangchen Li, Xinfeng Xie, Yu Wang, Yuan Xie
2019	—	`conf`	NNBench-X: A Benchmarking Methodology for Neural Network Accelerator Designs. EMC2@HPCA/CVPR/ISCA Xinfeng Xie, Xing Hu, Peng Gu, Shuangchen Li, Yu Ji, Yuan Xie
2019	J	`jnl`	NNBench-X: Benchmarking and Understanding Neural Network Workloads for Accelerator Designs. IEEE Comput. Archit. Lett. Xinfeng Xie, Xing Hu, Peng Gu, Shuangchen Li, Yu Ji, Yuan Xie
2019	A	`conf`	Near-Data Acceleration of Privacy-Preserving Biomarker Search with 3D-Stacked Memory. DATE Alvin Oliver Glova, Itir Akgun, Shuangchen Li, Xing Hu, Yuan Xie
2019	J	`jnl`	Network-on-Chip Design Guidelines for Monolithic 3-D Integration. IEEE Micro Itir Akgun, Dylan C. Stow, Yuan Xie
2019	J	`jnl`	Neural Network Model Extraction Attacks in Edge Devices by Hearing Architectural Hints. CoRR Xing Hu, Ling Liang, Lei Deng, Shuangchen Li, Xinfeng Xie, Yu Ji, Yufei Ding, Chang Liu, Timothy Sherwood, Yuan Xie
2019	—	`conf`	Ouroboros: An Inference Engine for Deep Learning Based TTS on Embedded Devices. Hot Chips Symposium Jiansong Zhang, Lixue Xia, Zhao Jiang, Hao Liang, Jiaoyan Chen, Shouda Liu, Wei Lin, Yuan Xie
2019	J	`jnl`	PXNOR-BNN: In/With Spin-Orbit Torque MRAM Preset-XNOR Operation-Based Binary Neural Networks. IEEE Trans. Very Large Scale Integr. Syst. Liang Chang, Xin Ma, Zhaohao Wang, Youguang Zhang, Yuan Xie, Weisheng Zhao
2019	J	`jnl`	Parana: A Parallel Neural Architecture Considering Thermal Problem of 3D Stacked Memory. IEEE Trans. Parallel Distributed Syst. Shouyi Yin, Shibin Tang, Xinhan Lin, Peng Ouyang, Fengbin Tu, Leibo Liu, Jishen Zhao, Cong Xu, Shuangchen Li, Yuan Xie, Shaojun Wei
2019	J	`jnl`	Poq: Projection-based Runtime Assertions for Debugging on a Quantum Computer. CoRR Gushu Li, Li Zhou, Nengkun Yu, Yufei Ding, Mingsheng Ying, Yuan Xie
2019	J	`jnl`	Power Profiling of Modern Die-Stacked Memory. IEEE Comput. Archit. Lett. Dylan C. Stow, Amin Farmahini Farahani, Sudhanva Gurumurthi, Michael Ignatowski, Yuan Xie
2019	J	`jnl`	QGAN: Quantized Generative Adversarial Networks. CoRR Peiqi Wang, Dongsheng Wang, Yu Ji, Xinfeng Xie, Haoxuan Song, XuXin Liu, Yongqiang Lyu, Yuan Xie
2019	J	`jnl`	SANQ: A Simulation Framework for Architecting Noisy Intermediate-Scale Quantum Computing System. CoRR Gushu Li, Yufei Ding, Yuan Xie
2019	A*	`conf`	Sparse Tensor Core: Algorithm and Hardware Co-Design for Vector-wise Sparse Neural Networks on Modern GPUs. MICRO Maohua Zhu, Tao Zhang, Zhenyu Gu, Yuan Xie
2019	A*	`conf`	SuperMem: Enabling Application-transparent Secure Persistent Memory with Low Overheads. MICRO Pengfei Zuo, Yu Hua, Yuan Xie
2019	J	`jnl`	TIME: A Training-in-Memory Architecture for RRAM-Based Deep Neural Networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ming Cheng, Lixue Xia, Zhenhua Zhu, Yi Cai, Yuan Xie, Yu Wang, Huazhong Yang
2019	A*	`conf`	Tackling the Qubit Mapping Problem for NISQ-Era Quantum Devices. ASPLOS Gushu Li, Yufei Ding, Yuan Xie
2019	J	`jnl`	Towards Efficient Superconducting Quantum Processor Architecture Design. CoRR Gushu Li, Yufei Ding, Yuan Xie
2019	J	`jnl`	Training High-Performance and Large-Scale Deep Neural Networks with Full 8-bit Integers. CoRR Yukuan Yang, Shuang Wu, Lei Deng, Tianyi Yan, Yuan Xie, Guoqi Li
2018	A	`conf`	AIM: Fast and energy-efficient AES in-memory implementation for emerging non-volatile main memory. DATE Mimi Xie, Shuangchen Li, Alvin Oliver Glova, Jingtong Hu, Yuangang Wang, Yuan Xie
2018	J	`jnl`	An Adaptive 3T-3MTJ Memory Cell Design for STT-MRAM-Based LLCs. IEEE Trans. Very Large Scale Integr. Syst. Linuo Xue, Bi Wu, Beibei Zhang, Yuanqing Cheng, Peiyuan Wang, Chando Park, Jimmy J. Kan, Seung-Hyuk Kang, Yuan Xie
2018	J	`jnl`	An Instruction Set Architecture for Machine Learning. ACM Trans. Comput. Syst. Yunji Chen, Huiying Lan, Zidong Du, Shaoli Liu, Jinhua Tao, Dong Han, Tao Luo, Qi Guo, Ling Li, Yuan Xie, Tianshi Chen
2018	J	`jnl`	Batch Normalization Sampling. CoRR Zhaodong Chen, Lei Deng, Guoqi Li, Jiawei Sun, Xing Hu, Xin Ma, Yuan Xie
2018	A*	`conf`	Bridge the Gap between Neural Networks and Neuromorphic Hardware with a Neural Network Compiler. ASPLOS Yu Ji, Youhui Zhang, Wenguang Chen, Yuan Xie
2018	J	`jnl`	Bridging the Gap Between Neural Networks and Neuromorphic Hardware with A Neural Network Compiler. CoRR Yu Ji, Youhui Zhang, Wenguang Chen, Yuan Xie
2018	—	`conf`	Cost-efficient 3D Integration to Hinder Reverse Engineering During and After Manufacturing. AsianHOST Peng Gu, Dylan C. Stow, Prashansa Mukim, Shuangchen Li, Yuan Xie
2018	J	`jnl`	Crossbar-Aware Neural Network Pruning. IEEE Access Ling Liang, Lei Deng, Yueling Zeng, Xing Hu, Yu Ji, Xin Ma, Guoqi Li, Yuan Xie
2018	J	`jnl`	Crossbar-aware neural network pruning. CoRR Ling Liang, Lei Deng, Yueling Zeng, Xing Hu, Yu Ji, Xin Ma, Guoqi Li, Yuan Xie
2018	J	`jnl`	Die Stacking Is Happening. IEEE Micro Xing Hu, Dylan C. Stow, Yuan Xie
2018	J	`jnl`	Dynamic Sparse Graph for Efficient Deep Learning. CoRR Liu Liu, Lei Deng, Xing Hu, Maohua Zhu, Guoqi Li, Yufei Ding, Yuan Xie
2018	J	`jnl`	Exploring Core and Cache Hierarchy Bottlenecks in Graph Processing Workloads. IEEE Comput. Archit. Lett. Abanti Basak, Xing Hu, Shuangchen Li, Sang Min Oh, Yuan Xie
2018	—	`conf`	GraphIA: an in-situ accelerator for large-scale graph processing. MEMSYS Gushu Li, Guohao Dai, Shuangchen Li, Yu Wang, Yuan Xie
2018	A*	`conf`	HitNet: Hybrid Ternary Recurrent Neural Network. NeurIPS Peiqi Wang, Xinfeng Xie, Lei Deng, Guoqi Li, Dongsheng Wang, Yuan Xie
2018	J	`jnl`	IAA: Incidental Approximate Architectures for Extremely Energy-Constrained Energy Harvesting Scenarios using IoT Nonvolatile Processors. IEEE Micro Kaisheng Ma, Jinyang Li, Xueqing Li, Yongpan Liu, Yuan Xie, Mahmut T. Kandemir, Jack Sampson, Vijaykrishnan Narayanan
2018	J	`jnl`	In-memory multiplication engine with SOT-MRAM based stochastic computing. CoRR Xin Ma, Liang Chang, Shuangchen Li, Lei Deng, Yufei Ding, Yuan Xie
2018	J	`jnl`	L1-Norm Batch Normalization for Efficient Training of Deep Neural Networks. CoRR Shuang Wu, Guoqi Li, Lei Deng, Liu Liu, Yuan Xie, Luping Shi
2018	J	`jnl`	MNSIM: Simulation Platform for Memristor-Based Neuromorphic Computing System. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Lixue Xia, Boxun Li, Tianqi Tang, Peng Gu, Pai-Yu Chen, Shimeng Yu, Yu Cao, Yu Wang, Yuan Xie, Huazhong Yang
2018	J	`jnl`	Mitigating BTI-Induced Degradation in STT-MRAM Sensing Schemes. IEEE Trans. Very Large Scale Integr. Syst. Ing-Chao Lin, Yun Kae Law, Yuan Xie
2018	A*	`conf`	NEOFog: Nonvolatility-Exploiting Optimizations for Fog Computing. ASPLOS Kaisheng Ma, Xueqing Li, Mahmut Taylan Kandemir, Jack Sampson, Vijaykrishnan Narayanan, Jinyang Li, Tongda Wu, Zhibo Wang, Yongpan Liu, Yuan Xie
2018	J	`jnl`	PIRT: A Runtime Framework to Enable Energy-Efficient Real-Time Robotic Applications on Heterogeneous Architectures. CoRR Liu Liu, Shaoshan Liu, Zhe Zhang, Bo Yu, Jie Tang, Yuan Xie
2018	A*	`conf`	Packet pump: overcoming network bottleneck in on-chip interconnects for GPGPUs. DAC Xianwei Cheng, Yang Zhao, Hui Zhao, Yuan Xie
2018	J	`jnl`	Performance Evaluation and Optimization of HBM-Enabled GPU for Data-Intensive Applications. IEEE Trans. Very Large Scale Integr. Syst. Maohua Zhu, Youwei Zhuo, Chao Wang, Wenguang Chen, Yuan Xie
2018	A*	`conf`	Persistence Parallelism Optimization: A Holistic Approach from Memory Bus to RDMA Network. MICRO Xing Hu, Matheus Ogleari, Jishen Zhao, Shuangchen Li, Abanti Basak, Yuan Xie
2018	A*	`conf`	RADAR: a 3D-reRAM based DNA alignment accelerator architecture. DAC Wenqin Huangfu, Shuangchen Li, Xing Hu, Yuan Xie
2018	A*	`conf`	SCOPE: A Stochastic Computing Engine for DRAM-Based In-Situ Accelerator. MICRO Shuangchen Li, Alvin Oliver Glova, Xing Hu, Peng Gu, Dimin Niu, Krishna T. Malladi, Hongzhong Zheng, Bob Brennan, Yuan Xie
2018	A*	`conf`	SNrram: an efficient sparse neural network computation architecture based on resistive random-access memory. DAC Peiqi Wang, Yu Ji, Chi Hong, Yongqiang Lyu, Dongsheng Wang, Yuan Xie
2018	J	`jnl`	Securing Emerging Nonvolatile Main Memory With Fast and Energy-Efficient AES In-Memory Implementation. IEEE Trans. Very Large Scale Integr. Syst. Mimi Xie, Shuangchen Li, Alvin Oliver Glova, Jingtong Hu, Yuan Xie
2018	J	`jnl`	Structurally Sparsified Backward Propagation for Faster Long Short-Term Memory Training. CoRR Maohua Zhu, Jason Clemons, Jeff Pool, Minsoo Rhu, Stephen W. Keckler, Yuan Xie
2018	J	`jnl`	Stuck-at Fault Tolerance in RRAM Computing Systems. IEEE J. Emerg. Sel. Topics Circuits Syst. Lixue Xia, Wenqin Huangfu, Tianqi Tang, Xiling Yin, Krishnendu Chakrabarty, Yuan Xie, Yu Wang, Huazhong Yang
2018	A*	`conf`	TETRIS: TilE-matching the TRemendous Irregular Sparsity. NeurIPS Yu Ji, Ling Liang, Lei Deng, Youyang Zhang, Youhui Zhang, Yuan Xie
2018	J	`jnl`	Tackling the Qubit Mapping Problem for NISQ-Era Quantum Devices. CoRR Gushu Li, Yufei Ding, Yuan Xie
2017	—	`conf`	Building energy-efficient multi-level cell STT-RAM caches with data compression. ASP-DAC Liu Liu, Ping Chi, Shuangchen Li, Yuanqing Cheng, Yuan Xie
2017	—	`conf`	Computation-oriented fault-tolerance schemes for RRAM computing systems. ASP-DAC Wenqin Huangfu, Lixue Xia, Ming Cheng, Xiling Yin, Tianqi Tang, Boxun Li, Krishnendu Chakrabarty, Yuan Xie, Yu Wang, Huazhong Yang
2017	A	`conf`	Cost-effective design of scalable high-performance systems using active and passive interposers. ICCAD Dylan C. Stow, Yuan Xie, Taniya Siddiqua, Gabriel H. Loh
2017	J	`jnl`	DLAU: A Scalable Deep Learning Accelerator Unit on FPGA. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Chao Wang, Lei Gong, Qi Yu, Xi Li, Yuan Xie, Xuehai Zhou
2017	A*	`conf`	DRISA: a DRAM-based reconfigurable in-situ accelerator. MICRO Shuangchen Li, Dimin Niu, Krishna T. Malladi, Hongzhong Zheng, Bob Brennan, Yuan Xie
2017	J	`jnl`	Dynamic Power and Energy Management for Energy Harvesting Nonvolatile Processor Systems. ACM Trans. Embed. Comput. Syst. Kaisheng Ma, Xueqing Li, Huichu Liu, Xiao Sheng, Yiqun Wang, Karthik Swaminathan, Yongpan Liu, Yuan Xie, John Sampson, Vijaykrishnan Narayanan
2017	A*	`conf`	Incidental computing on IoT nonvolatile processors. MICRO Kaisheng Ma, Xueqing Li, Jinyang Li, Yongpan Liu, Yuan Xie, Jack Sampson, Mahmut Taylan Kandemir, Vijaykrishnan Narayanan
2017	J	`jnl`	Overview of 3-D Architecture Design Opportunities and Techniques. IEEE Des. Test Jishen Zhao, Qiaosha Zou, Yuan Xie
2017	B	`conf`	POSTER: Bridge the Gap Between Neural Networks and Neuromorphic Hardware. PACT Yu Ji, Youhui Zhang, Wenguang Chen, Yuan Xie
2017	A	`conf`	PRESCOTT: Preset-based cross-point architecture for spin-orbit-torque magnetic random access memory. ICCAD Liang Chang, Zhaohao Wang, Alvin Oliver Glova, Jishen Zhao, Youguang Zhang, Yuan Xie, Weisheng Zhao
2017	A	`conf`	Performance evaluation and optimization of HBM-Enabled GPU for data-intensive applications. DATE Maohua Zhu, Youwei Zhuo, Chao Wang, Wenguang Chen, Yuan Xie
2017	—	`conf`	Security Threats and Countermeasures in Three-Dimensional Integrated Circuits. ACM Great Lakes Symposium on VLSI Jaya Dofe, Peng Gu, Dylan C. Stow, Qiaoyan Yu, Eren Kursun, Yuan Xie
2017	J	`jnl`	Software-Hardware Codesign for Efficient Neural Network Acceleration. IEEE Micro Kaiyuan Guo, Song Han, Song Yao, Yu Wang, Yuan Xie, Huazhong Yang
2017	—	`conf`	Spendthrift: Machine learning based resource and frequency scaling for ambient energy harvesting nonvolatile processors. ASP-DAC Kaisheng Ma, Xueqing Li, Srivatsa Rangachar Srinivasa, Yongpan Liu, John Sampson, Yuan Xie, Vijaykrishnan Narayanan
2017	A*	`conf`	TIME: A Training-in-memory Architecture for Memristor-based Deep Neural Networks. DAC Ming Cheng, Lixue Xia, Zhenhua Zhu, Yi Cai, Yuan Xie, Yu Wang, Huazhong Yang
2017	A*	`conf`	There and Back Again: Optimizing the Interconnect in Networks of Memory Cubes. ISCA Matthew Poremba, Itir Akgun, Jieming Yin, Onur Kayiran, Yuan Xie, Gabriel H. Loh
2017	J	`jnl`	Thermomechanical Stress-Aware Management for 3-D IC Designs. IEEE Trans. Very Large Scale Integr. Syst. Qiaosha Zou, Eren Kursun, Yuan Xie
2016	—	`conf`	A Real-Time and Energy-Efficient Implementation of Difference-of-Gaussian with Flexible Thin-Film Transistors. ISVLSI Nan Wu, Zheyu Liu, Fei Qiao, Qi Wei, Xiaojun Guo, Yuan Xie, Huazhong Yang
2016	J	`jnl`	A Real-Time and Energy-Efficient Implementation of Difference-of-Gaussian with Flexible Thin-Film Transistors. CoRR Nan Wu, Zheyu Liu, Fei Qiao, Xiaojun Guo, Qi Wei, Yuan Xie, Huazhong Yang
2016	A*	`conf`	A unified memory network architecture for in-memory computing in commodity servers. MICRO Jia Zhan, Itir Akgun, Jishen Zhao, Al Davis, Paolo Faraboschi, Yuangang Wang, Yuan Xie
2016	J	`jnl`	Adapting B IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ping Chi, Wang-Chien Lee, Yuan Xie
2016	—	`conf`	Architecture design with STT-RAM: Opportunities and challenges. ASP-DAC Ping Chi, Shuangchen Li, Yuanqing Cheng, Yu Lu, Seung-Hyuk Kang, Yuan Xie
2016	J	`jnl`	BACH: A Bandwidth-Aware Hybrid Cache Hierarchy Design with Nonvolatile Memories. J. Comput. Sci. Technol. Jishen Zhao, Cong Xu, Tao Zhang, Yuan Xie
2016	C	`conf`	Building a Low Latency, Highly Associative DRAM Cache with the Buffered Way Predictor. SBAC-PAD Zhe Wang, Daniel A. Jiménez, Tao Zhang, Gabriel H. Loh, Yuan Xie
2016	J	`jnl`	CNNLab: a Novel Parallel Framework for Neural Networks using GPU and FPGA-a Practical Study with Trade-off Analysis. CoRR Maohua Zhu, Liu Liu, Chao Wang, Yuan Xie
2016	A*	`conf`	Cambricon: An Instruction Set Architecture for Neural Networks. ISCA Shaoli Liu, Zidong Du, Jinhua Tao, Dong Han, Tao Luo, Yuan Xie, Yunji Chen, Tianshi Chen
2016	A	`conf`	Cost analysis and cost-driven IP reuse methodology for SoC design based on 2.5D/3D integration. ICCAD Dylan C. Stow, Itir Akgun, Russell Barnes, Peng Gu, Yuan Xie
2016	—	`conf`	Cost and Thermal Analysis of High-Performance 2.5D and 3D Integrated Circuit Design Space. ISVLSI Dylan C. Stow, Itir Akgun, Russell Barnes, Peng Gu, Yuan Xie
2016	J	`jnl`	DLAU: A Scalable Deep Learning Accelerator Unit on FPGA. CoRR Chao Wang, Qi Yu, Lei Gong, Xi Li, Yuan Xie, Xuehai Zhou
2016	A*	`conf`	Fine-granularity tile-level parallelism in non-volatile memory architecture with two-dimensional bank subdivision. DAC Matthew Poremba, Tao Zhang, Yuan Xie
2016	J	`jnl`	Hybrid Drowsy SRAM and STT-RAM Buffer Designs for Dark-Silicon-Aware NoC. IEEE Trans. Very Large Scale Integr. Syst. Jia Zhan, Jin Ouyang, Fen Ge, Jishen Zhao, Yuan Xie
2016	A*	`conf`	LAP: Loop-Block Aware Inclusion Properties for Energy-Efficient Asymmetric Last Level Caches. ISCA Hsiang-Yun Cheng, Jishen Zhao, Jack Sampson, Mary Jane Irwin, Aamer Jaleel, Yu Lu, Yuan Xie
2016	—	`conf`	Leveraging 3D Technologies for Hardware Security: Opportunities and Challenges. ACM Great Lakes Symposium on VLSI Peng Gu, Shuangchen Li, Dylan C. Stow, Russell Barnes, Liu Liu, Yuan Xie, Eren Kursun
2016	A	`conf`	MNSIM: Simulation platform for memristor-based neuromorphic computing system. DATE Lixue Xia, Boxun Li, Tianqi Tang, Peng Gu, Xiling Yin, Wenqin Huangfu, Pai-Yu Chen, Shimeng Yu, Yu Cao, Yu Wang, Yuan Xie, Huazhong Yang
2016	A*	`conf`	Mellow Writes: Extending Lifetime in Resistive Memories through Selective Slow Write Backs. ISCA Lunkai Zhang, Brian Neely, Diana Franklin, Dmitri B. Strukov, Yuan Xie, Frederic T. Chong
2016	A*	`conf`	NEUTRAMS: Neural network transformation and co-design under neuromorphic hardware constraints. MICRO Yu Ji, Youhui Zhang, Shuangchen Li, Ping Chi, Cihang Jiang, Peng Qu, Yuan Xie, Wenguang Chen
2016	A	`conf`	NVSim-CAM: a circuit-level simulator for emerging nonvolatile memory based content-addressable memory. ICCAD Shuangchen Li, Liu Liu, Peng Gu, Cong Xu, Yuan Xie
2016	A*	`conf`	NVSim-VX DAC Enes Eken, Linghao Song, Ismail Bayram, Cong Xu, Wujie Wen, Yuan Xie, Yiran Chen
2016	Misc	`conf`	Neural network transformation under hardware constraints. CASES Youhui Zhang, Yu Ji, Wenguang Chen, Yuan Xie
2016	J	`jnl`	Nonvolatile Processor Architectures: Efficient, Reliable Progress with Unstable Power. IEEE Micro Kaisheng Ma, Xueqing Li, Karthik Swaminathan, Yang Zheng, Shuangchen Li, Yongpan Liu, Yuan Xie, John (Jack) Morgan Sampson, Vijaykrishnan Narayanan
2016	A	`conf`	ODESY: a novel 3T-3MTJ cell design with optimized area DEnsity, scalability and latencY. ICCAD Linuo Xue, Yuanqing Cheng, Jianlei Yang, Peiyuan Wang, Yuan Xie
2016	A*	`conf`	OSCAR: Orchestrating STT-RAM cache traffic for heterogeneous CPU-GPU architectures. MICRO Jia Zhan, Onur Kayiran, Gabriel H. Loh, Chita R. Das, Yuan Xie
2016	A*	`conf`	PRIME: A Novel Processing-in-Memory Architecture for Neural Network Computation in ReRAM-Based Main Memory. ISCA Ping Chi, Shuangchen Li, Cong Xu, Tao Zhang, Jishen Zhao, Yongpan Liu, Yu Wang, Yuan Xie
2016	A*	`conf`	Pinatubo: a processing-in-memory architecture for bulk bitwise operations in emerging non-volatile memories. DAC Shuangchen Li, Cong Xu, Qiaosha Zou, Jishen Zhao, Yu Lu, Yuan Xie
2016	C	`conf`	Redesigning software and systems for non-volatile processors on self-powered devices. VLSI-SoC Mengying Zhao, Keni Qiu, Yuan Xie, Jingtong Hu, Chun Jason Xue
2016	C	`conf`	Scalable memory fabric for silicon interposer-based multi-core systems. ICCD Itir Akgun, Jia Zhan, Yuangang Wang, Yuan Xie
2016	J	`jnl`	TSocket: Thermal Sustainable Power Budgeting. ACM Trans. Design Autom. Electr. Syst. Guoqing Chen, Yi Xu, Xing Hu, Xiangyang Guo, Jun Ma, Yu Hu, Yuan Xie
2016	C	`conf`	Thermal-aware 3D design for side-channel information leakage. ICCD Peng Gu, Dylan C. Stow, Russell Barnes, Eren Kursun, Yuan Xie
2015	J	`jnl`	A Write-Aware STTRAM-Based Register File Architecture for GPGPU. ACM J. Emerg. Technol. Comput. Syst. Jue Wang, Yuan Xie
2015	J	`jnl`	Adaptive Burst-Writes (ABW): Memory Requests Scheduling to Reduce Write-Induced Interference. ACM Trans. Design Autom. Electr. Syst. Hsiang-Yun Cheng, Mary Jane Irwin, Yuan Xie
2015	A*	`conf`	Ambient energy harvesting nonvolatile processors: from circuit to system. DAC Yongpan Liu, Zewei Li, Hehe Li, Yiqun Wang, Xueqing Li, Kaisheng Ma, Shuangchen Li, Meng-Fan Chang, John Sampson, Yuan Xie, Jiwu Shu, Huazhong Yang
2015	A*	`conf`	Architecture exploration for ambient energy harvesting nonvolatile processors. HPCA Kaisheng Ma, Yang Zheng, Shuangchen Li, Karthik Swaminathan, Xueqing Li, Yongpan Liu, Jack Sampson, Yuan Xie, Vijaykrishnan Narayanan
2015	J	`jnl`	Buri: Scaling Big-Memory Computing with Hardware-Based Memory Expansion. ACM Trans. Archit. Code Optim. Jishen Zhao, Sheng Li, Jichuan Chang, John L. Byrne, Laura L. Ramirez, Kevin T. Lim, Yuan Xie, Paolo Faraboschi
2015	A*	`conf`	Core vs. uncore: the heart of darkness. DAC Hsiang-Yun Cheng, Jia Zhan, Jishen Zhao, Yuan Xie, Jack Sampson, Mary Jane Irwin
2015	A	`conf`	DESTINY: a tool for modeling emerging 3D NVM and eDRAM caches. DATE Matt Poremba, Sparsh Mittal, Dong Li, Jeffrey S. Vetter, Yuan Xie
2015	—	`book`	Die-stacking Architecture Yuan Xie, Jishen Zhao
2015	A*	`conf`	DimNoC: a dim silicon approach towards power-efficient on-chip network. DAC Jia Zhan, Jin Ouyang, Fen Ge, Jishen Zhao, Yuan Xie
2015	A	`conf`	Dynamic Machine Learning Based Matching of Nonvolatile Processor Microarchitecture to Harvested Energy Profile. ICCAD Kaisheng Ma, Xueqing Li, Yongpan Liu, John Sampson, Yuan Xie, Vijaykrishnan Narayanan
2015	J	`jnl`	EECache: A Comprehensive Study on the Architectural Design for Energy-Efficient Last-Level Caches in Chip Multiprocessors. ACM Trans. Archit. Code Optim. Hsiang-Yun Cheng, Matt Poremba, Narges Shahidi, Ivan Stalev, Mary Jane Irwin, Mahmut T. Kandemir, Jack Sampson, Yuan Xie
2015	—	`conf`	Energy Efficient RRAM Spiking Neural Network for Real Time Classification. ACM Great Lakes Symposium on VLSI Yu Wang, Tianqi Tang, Lixue Xia, Boxun Li, Peng Gu, Huazhong Yang, Hai Li, Yuan Xie
2015	—	`conf`	Exploring memory controller configurations for many-core systems with 3D stacked DRAMs. ISQED Fen Ge, Jia Zhan, Yuan Xie, Vijaykrishnan Narayanan
2015	—	`conf`	Heterogeneous architecture design with emerging 3D and non-volatile memory technologies. ASP-DAC Qiaosha Zou, Matthew Poremba, Rui He, Wei Yang, Junfeng Zhao, Yuan Xie
2015	A	`conf`	History-Assisted Adaptive-Granularity Caches (HAAG$) for High Performance 3D DRAM Architectures. ICS Ke Chen, Sheng Li, Jung Ho Ahn, Naveen Muralimanohar, Jishen Zhao, Cong Xu, Seongil O, Yuan Xie, Jay B. Brockman, Norman P. Jouppi
2015	J	`jnl`	Impact of Cell Failure on Reliable Cross-Point Resistive Memory Design. ACM Trans. Design Autom. Electr. Syst. Cong Xu, Dimin Niu, Yang Zheng, Shimeng Yu, Yuan Xie
2015	J	`jnl`	Impact of Write Pulse and Process Variation on 22 nm FinFET-Based STT-RAM Design: A Device-Architecture Co-Optimization Approach. IEEE Trans. Multi Scale Comput. Syst. Cong Xu, Yang Zheng, Dimin Niu, Xiaochun Zhu, Seung-Hyuk Kang, Yuan Xie
2015	J	`jnl`	Introduction to the Special Issue on Reliable, Resilient, and Robust Design of Circuits and Systems. ACM Trans. Design Autom. Electr. Syst. R. Iris Bahar, Alex K. Jones, Yuan Xie
2015	A	`conf`	Leveraging emerging nonvolatile memory in high-level synthesis with loop transformations. ISLPED Shuangchen Li, Ang Li, Yuan Zhe, Yongpan Liu, Peng Li, Guangyu Sun, Yu Wang, Huazhong Yang, Yuan Xie
2015	—	`conf`	Leveraging nonvolatility for architecture design with emerging NVM. NVMSA Shuangchen Li, Ping Chi, Jishen Zhao, Kwang-Ting Cheng, Yuan Xie
2015	J	`jnl`	Memory and Storage System Design with Nonvolatile Memory Technologies. Inf. Media Technol. Jishen Zhao, Cong Xu, Ping Chi, Yuan Xie
2015	J	`jnl`	Memory and Storage System Design with Nonvolatile Memory Technologies. IPSJ Trans. Syst. LSI Des. Methodol. Jishen Zhao, Cong Xu, Ping Chi, Yuan Xie
2015	—	`conf`	Modeling framework for cross-point resistive memory design emphasizing reliability and variability issues. ASP-DAC Yang Zheng, Cong Xu, Yuan Xie
2015	J	`jnl`	NVMain 2.0: A User-Friendly Memory Simulator to Model (Non-)Volatile Memory Systems. IEEE Comput. Archit. Lett. Matthew Poremba, Tao Zhang, Yuan Xie
2015	J	`jnl`	Nonvolatile Processor Architecture Exploration for Energy-Harvesting Applications. IEEE Micro Kaisheng Ma, Xueqing Li, Shuangchen Li, Yongpan Liu, John (Jack) Morgan Sampson, Yuan Xie, Vijaykrishnan Narayanan
2015	—	`conf`	Nonvolatile memory allocation and hierarchy optimization for high-level synthesis. ASP-DAC Shuangchen Li, Ang Li, Yongpan Liu, Yuan Xie, Huazhong Yang
2015	A*	`conf`	Overcoming the challenges of crossbar resistive memory architectures. HPCA Cong Xu, Dimin Niu, Naveen Muralimanohar, Rajeev Balasubramonian, Tao Zhang, Shimeng Yu, Yuan Xie
2015	Misc	`conf`	Self-powered wearable sensor node: Challenges and opportunities. CASES Yongpan Liu, Hehe Li, Xueqing Li, Chun Jason Xue, Yuan Xie, Huazhong Yang
2015	—	`conf`	Using Multiple-Input NEMS for Parallel A/D Conversion and Image Processing. ISVLSI Kaisheng Ma, Nandhini Chandramoorthy, Xueqing Li, Sumeet Kumar Gupta, John Sampson, Yuan Xie, Vijaykrishnan Narayanan
2015	J	`jnl`	Whitespace-Aware TSV Arrangement in 3-D Clock Tree Synthesis. IEEE Trans. Very Large Scale Integr. Syst. Wulong Liu, Yu Wang, Guoqing Chen, Yuchun Ma, Yuan Xie, Huazhong Yang
2014	—	`conf`	3D-SWIFT: a high-performance 3D-stacked wide IO DRAM. ACM Great Lakes Symposium on VLSI Tao Zhang, Cong Xu, Ke Chen, Guangyu Sun, Yuan Xie
2014	—	`conf`	3DLAT: TSV-based 3D ICs crosstalk minimization utilizing Less Adjacent Transition code. ASP-DAC Qiaosha Zou, Dimin Niu, Yan Cao, Yuan Xie
2014	—	`conf`	A cost benefit analysis: The impact of defect clustering on the necessity of pre-bond tests. 3DIC Qiaosha Zou, Matt Poremba, Yuan Xie
2014	A*	`conf`	Adaptive placement and migration policy for an STT-RAM-based hybrid cache. HPCA Zhe Wang, Daniel A. Jiménez, Cong Xu, Guangyu Sun, Yuan Xie
2014	J	`jnl`	An Embedded Co-AdaBoost based construction of software document relation coupled resource spaces for cyber-physical society. Future Gener. Comput. Syst. Jin Liu, Juan Li, Xiaoping Sun, Yuan Xie, Jeff Yu Lei, Qiping Hu
2014	A	`conf`	Architecting 3D vertical resistive memory for next-generation storage systems. ICCAD Cong Xu, Pai-Yu Chen, Dimin Niu, Yang Zheng, Shimeng Yu, Yuan Xie
2014	J	`jnl`	Building and Optimizing MRAM-Based Commodity Memories. ACM Trans. Archit. Code Optim. Jue Wang, Xiangyu Dong, Yuan Xie
2014	—	`conf`	Building energy-efficient multi-level cell STT-MRAM based cache through dynamic data-resistance encoding. ISQED Ping Chi, Cong Xu, Xiaochun Zhu, Yuan Xie
2014	A*	`conf`	CREAM: A Concurrent-Refresh-Aware DRAM Memory architecture. HPCA Tao Zhang, Matthew Poremba, Cong Xu, Guangyu Sun, Yuan Xie
2014	—	`conf`	Compact models and model standard for 2.5D and 3D integration. SLIP Qiaosha Zou, Yuan Xie
2014	A*	`conf`	Design Methodologies for 3D Mixed Signal Integrated Circuits: a Practical 12-bit SAR ADC Design Case. DAC Wulong Liu, Guoqing Chen, Xue Han, Yu Wang, Yuan Xie, Huazhong Yang
2014	—	`conf`	Designing vertical bandwidth reconfigurable 3D NoCs for many core systems. 3DIC Qiaosha Zou, Jia Zhan, Fen Ge, Matt Poremba, Yuan Xie
2014	A	`conf`	EECache: exploiting design choices in energy-efficient last-level caches for chip multiprocessors. ISLPED Hsiang-Yun Cheng, Matthew Poremba, Narges Shahidi, Ivan Stalev, Mary Jane Irwin, Mahmut T. Kandemir, Jack Sampson, Yuan Xie
2014	J	`jnl`	Editorial: ACM Transactions on Design Automation of Electronics Systems and Beyond. ACM Trans. Design Autom. Electr. Syst. Naehyuck Chang, David Z. Pan, Yuan Xie
2014	—	`conf`	Efficient region-aware P/G TSV planning for 3D ICs. ISQED Song Yao, Xiaoming Chen, Yu Wang, Yuchun Ma, Yuan Xie, Huazhong Yang
2014	A	`conf`	Enabling high-performance LPDDRx-compatible MRAM. ISLPED Jue Wang, Xiangyu Dong, Yuan Xie
2014	J	`jnl`	Endurance-aware cache line management for non-volatile caches. ACM Trans. Archit. Code Optim. Jue Wang, Xiangyu Dong, Yuan Xie, Norman P. Jouppi
2014	J	`jnl`	Exploration of Electrical and Novel Optical Chip-to-Chip Interconnects. IEEE Des. Test Wulong Liu, Yu Wang, Xue Feng, Yidong Huang, Huazhong Yang, Yuan Xie, Guoqing Chen
2014	A*	`conf`	FIRM: Fair and High-Performance Memory Control for Persistent Memory Systems. MICRO Jishen Zhao, Onur Mutlu, Yuan Xie
2014	A*	`conf`	Half-DRAM: A high-bandwidth and low-power DRAM architecture from the rethinking of fine-grained activation. ISCA Tao Zhang, Ke Chen, Cong Xu, Guangyu Sun, Tao Wang, Yuan Xie
2014	—	`conf`	Independently-Controlled-Gate FinFET 6T SRAM Cell Design for Leakage Current Reduction and Enhanced Read Access Speed. ISVLSI Kaisheng Ma, Huichu Liu, Yang Xiao, Yang Zheng, Xueqing Li, Sumeet Kumar Gupta, Yuan Xie, Vijaykrishnan Narayanan
2014	A	`ed.`	International Symposium on Low Power Electronics and Design, ISLPED'14, La Jolla, CA, USA - August 11 - 13, 2014 ISLPED Yuan Xie, Tanay Karnik, Muhammad M. Khellah, Renu Mehra
2014	A	`conf`	Making B ISLPED Ping Chi, Wang-Chien Lee, Yuan Xie
2014	—	`conf`	Modeling and design analysis of 3D vertical resistive memory - A low cost cross-point architecture. ASP-DAC Cong Xu, Dimin Niu, Shimeng Yu, Yuan Xie
2014	A*	`conf`	NoC-Sprinting: Interconnect for Fine-Grained Sprinting in the Dark Silicon Era. DAC Jia Zhan, Yuan Xie, Guangyu Sun
2014	—	`conf`	NoΔ: Leveraging delta compression for end-to-end memory access in NoC based multicores. ASP-DAC Jia Zhan, Matthew Poremba, Yi Xu, Yuan Xie
2014	J	`jnl`	On-Chip Hybrid Power Supply System for Wireless Sensor Nodes. ACM J. Emerg. Technol. Comput. Syst. Wulong Liu, Yu Wang, Yuchun Ma, Yuan Xie, Huazhong Yang
2014	J	`jnl`	Optimizing the NoC Slack Through Voltage and Frequency Scaling in Hard Real-Time Embedded Systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jia Zhan, Nikolay Stoimenov, Jin Ouyang, Lothar Thiele, Vijaykrishnan Narayanan, Yuan Xie
2014	J	`jnl`	PS3-RAM: A Fast Portable and Scalable Statistical STT-RAM Reliability/Energy Analysis Method. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Wujie Wen, Yaojun Zhang, Yiran Chen, Yu Wang, Yuan Xie
2014	J	`jnl`	Preventing STT-RAM Last-Level Caches from Port Obstruction. ACM Trans. Archit. Code Optim. Jue Wang, Xiangyu Dong, Yuan Xie
2014	C	`conf`	ProactiveDRAM: A DRAM-initiated retention management scheme. ICCD Jue Wang, Xiangyu Dong, Yuan Xie
2014	—	`conf`	Reliability-aware cross-point resistive memory design. ACM Great Lakes Symposium on VLSI Cong Xu, Dimin Niu, Yang Zheng, Shimeng Yu, Yuan Xie
2014	A*	`conf`	Run-Time Technique for Simultaneous Aging and Power Optimization in GPGPUs. DAC Xiaoming Chen, Yu Wang, Yun Liang, Yuan Xie, Huazhong Yang
2014	—	`conf`	SwimmingLane: A composite approach to mitigate voltage droop effects in 3D power delivery network. ASP-DAC Xing Hu, Yi Xu, Yu Hu, Yuan Xie
2014	—	`conf`	TSV power supply array electromigration lifetime analysis in 3D ICS. ACM Great Lakes Symposium on VLSI Qiaosha Zou, Tao Zhang, Cong Xu, Yuan Xie
2014	J	`jnl`	Testable cross-power domain interface (CPDI) circuit design in monolithic 3D technology. ACM J. Emerg. Technol. Comput. Syst. Jing Xie, Yang Du, Yuan Xie
2014	A*	`conf`	Thermal-Sustainable Power Budgeting for Dynamic Threading. DAC Xing Hu, Yi Xu, Jun Ma, Guoqing Chen, Yu Hu, Yuan Xie
2014	A	`conf`	Using multi-level cell STT-RAM for fast and energy-efficient local checkpointing. ICCAD Ping Chi, Cong Xu, Tao Zhang, Xiangyu Dong, Yuan Xie
2013	J	`jnl`	A Synthesis Algorithm for Reconfigurable Single-Electron Transistor Arrays. ACM J. Emerg. Technol. Comput. Syst. Yung-Chih Chen, Soumya Eachempati, Chun-Yao Wang, Suman Datta, Yuan Xie, Vijaykrishnan Narayanan
2013	B	`conf`	A circuit-architecture co-optimization framework for evaluating emerging memory hierarchies. ISPASS Xiangyu Dong, Norman P. Jouppi, Yuan Xie
2013	J	`jnl`	A circuit-architecture co-optimization framework for exploring nonvolatile memory hierarchies. ACM Trans. Archit. Code Optim. Xiangyu Dong, Norman P. Jouppi, Yuan Xie
2013	J	`jnl`	Assessment of Circuit Optimization Techniques Under NBTI. IEEE Des. Test Xiaoming Chen, Yu Wang, Huazhong Yang, Yuan Xie, Yu Cao
2013	—	`conf`	CPDI: Cross-power-domain interface circuit design in monolithic 3D technology. ISQED Jing Xie, Yang Du, Yuan Xie
2013	—	`conf`	Cost-driven 3D design optimization with metal layer reduction technique. ISQED Qiaosha Zou, Jing Xie, Yuan Xie
2013	A	`conf`	Design of cross-point metal-oxide ReRAM emphasizing reliability and cost. ICCAD Dimin Niu, Cong Xu, Naveen Muralimanohar, Norman P. Jouppi, Yuan Xie
2013	A*	`conf`	Designing energy-efficient NoC for real-time embedded systems through slack optimization. DAC Jia Zhan, Nikolay Stoimenov, Jin Ouyang, Lothar Thiele, Vijaykrishnan Narayanan, Yuan Xie
2013	C	`conf`	Designing scratchpad memory architecture with emerging STT-RAM memory technologies. ISCAS Peng Wang, Guangyu Sun, Tao Wang, Yuan Xie, Jason Cong
2013	J	`jnl`	Evaluation and mitigation of performance degradation under random telegraph noise for digital circuits. IET Circuits Devices Syst. Xiaoming Chen, Hong Luo, Yu Wang, Yu Cao, Yuan Xie, Yuchun Ma, Huazhong Yang
2013	J	`jnl`	Exploring the vulnerability of CMPs to soft errors with 3D stacked nonvolatile memory. ACM J. Emerg. Technol. Comput. Syst. Guangyu Sun, Eren Kursun, Jude A. Rivers, Yuan Xie
2013	A	`conf`	Future memory and interconnect technologies. DATE Yuan Xie
2013	J	`jnl`	Guest Editorial. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yuan Xie, Gabriel H. Loh
2013	A	`ed.`	International Symposium on Low Power Electronics and Design (ISLPED), Beijing, China, September 4-6, 2013 ISLPED Pai H. Chou, Ru Huang, Yuan Xie, Tanay Karnik
2013	A*	`conf`	Kiln: closing the performance gap between systems with and without persistence support. MICRO Jishen Zhao, Sheng Li, Doe Hyun Yoon, Yuan Xie, Norman P. Jouppi
2013	C	`conf`	Lazy Precharge: An overhead-free method to reduce precharge overhead for memory parallelism improvement of DRAM system. ICCD Tao Zhang, Cong Xu, Yuan Xie, Guangyu Sun
2013	C	`conf`	Low power multi-level-cell resistive memory design with incomplete data mapping. ICCD Dimin Niu, Qiaosha Zou, Cong Xu, Yuan Xie
2013	A	`conf`	OAP: an obstruction-aware cache management policy for STT-RAM last-level caches. DATE Jue Wang, Xiangyu Dong, Yuan Xie
2013	J	`jnl`	Optimizing GPU energy efficiency with 3D die-stacking graphics memory and reconfigurable memory interface. ACM Trans. Archit. Code Optim. Jishen Zhao, Guangyu Sun, Gabriel H. Loh, Yuan Xie
2013	A*	`conf`	TS-Router: On maximizing the Quality-of-Allocation in the On-Chip Network. HPCA Yuan-Ying Chang, Yoshi Shih-Chieh Huang, Matthew Poremba, Vijaykrishnan Narayanan, Yuan Xie, Chung-Ta King
2013	—	`conf`	TSV-aware topology generation for 3D Clock Tree Synthesis. ISQED Wulong Liu, Haixiao Du, Yu Wang, Yuchun Ma, Yuan Xie, Jinguo Quan, Huazhong Yang
2013	J	`jnl`	Thermal-aware P/G TSV planning for IR drop reduction in 3D ICs. Integr. Zuowei Li, Yuchun Ma, Qiang Zhou, Yici Cai, Yuan Xie, Tingting Huang
2013	A	`conf`	Thermomechanical stress-aware management for 3D IC designs. DATE Qiaosha Zou, Tao Zhang, Eren Kursun, Yuan Xie
2013	J	`jnl`	Through Silicon Via Aware Design Planning for Thermally Efficient 3-D Integrated Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yibo Chen, Eren Kursun, Dave Motschman, Charles Johnson, Yuan Xie
2013	A*	`conf`	Understanding the trade-offs in multi-level cell ReRAM memory design. DAC Cong Xu, Dimin Niu, Naveen Muralimanohar, Norman P. Jouppi, Yuan Xie
2013	J	`jnl`	WADE: Writeback-aware dynamic cache management for NVM-based main memory system. ACM Trans. Archit. Code Optim. Zhe Wang, Shuchang Shan, Ting Cao, Junli Gu, Yi Xu, Shuai Mu, Yuan Xie, Daniel A. Jiménez
2013	A*	`conf`	i HPCA Jue Wang, Xiangyu Dong, Yuan Xie, Norman P. Jouppi
2012	A	`conf`	3DHLS: Incorporating high-level synthesis in physical planning of three-dimensional (3D) ICs. DATE Yibo Chen, Guangyu Sun, Qiaosha Zou, Yuan Xie
2012	—	`conf`	An Embedded Co-AdaBoost and Its Application in Classification of Software Document Relation. SKG Jin Liu, Juan Li, Yuan Xie, Jeff Yu Lei, Qiping Hu
2012	A*	`conf`	Cache revive: architecting volatile STT-RAM caches for enhanced performance in CMPs. DAC Adwait Jog, Asit K. Mishra, Cong Xu, Yuan Xie, Vijaykrishnan Narayanan, Ravishankar R. Iyer, Chita R. Das
2012	A	`conf`	Design trade-offs for high density cross-point resistive memory. ISLPED Dimin Niu, Cong Xu, Naveen Muralimanohar, Norman P. Jouppi, Yuan Xie
2012	J	`jnl`	ESL Design Methodology. J. Electr. Comput. Eng. Deming Chen, Kiyoung Choi, Philippe Coussy, Yuan Xie, Zhiru Zhang
2012	J	`jnl`	Electrical Characterization for Intertier Connections and Timing Analysis for 3-D ICs. IEEE Trans. Very Large Scale Integr. Syst. Xiaoxia Wu, Wei Zhao, Mark Nakamoto, Chandra Nimmagadda, Durodami Lisk, Sam Gu, Riko Radojcic, Matt Nowak, Yuan Xie
2012	A	`conf`	Energy-efficient GPU design with reconfigurable in-package graphics memory. ISLPED Jishen Zhao, Guangyu Sun, Gabriel H. Loh, Yuan Xie
2012	—	`conf`	Low power memristor-based ReRAM design with Error Correcting Code. ASP-DAC Dimin Niu, Yang Xiao, Yuan Xie
2012	—	`ch.`	Low-Power Design of Emerging Memory Technologies. Handbook of Energy-Aware and Green Computing Yiran Chen, Hai Li, Yuan Xie, Dimin Niu
2012	A	`conf`	MAGE: adaptive granularity and ECC for resilient and power efficient memory systems. SC Sheng Li, Doe Hyun Yoon, Ke Chen, Jishen Zhao, Jung Ho Ahn, Jay B. Brockman, Yuan Xie, Norman P. Jouppi
2012	—	`conf`	Mitigating electromigration of power supply networks using bidirectional current stress. ACM Great Lakes Symposium on VLSI Jing Xie, Vijaykrishnan Narayanan, Yuan Xie
2012	A	`conf`	Modeling and design exploration of FBDRAM as on-chip memory. DATE Guangyu Sun, Cong Xu, Yuan Xie
2012	—	`conf`	NVMain: An Architectural-Level Main Memory Simulator for Emerging Non-volatile Memories. ISVLSI Matthew Poremba, Yuan Xie
2012	J	`jnl`	NVSim: A Circuit-Level Performance, Energy, and Area Model for Emerging Nonvolatile Memory. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Xiangyu Dong, Cong Xu, Yuan Xie, Norman P. Jouppi
2012	A	`conf`	Optimizing bandwidth and power of graphics memory with hybrid memory technologies and adaptive data migration. ICCAD Jishen Zhao, Yuan Xie
2012	A*	`conf`	PS3-RAM: a fast portable and scalable statistical STT-RAM reliability analysis method. DAC Wujie Wen, Yaojun Zhang, Yiran Chen, Yu Wang, Yuan Xie
2012	J	`jnl`	Parametric Yield-Driven Resource Binding in High-Level Synthesis with Multi-Vth/Vdd Library and Device Sizing. J. Electr. Comput. Eng. Yibo Chen, Yu Wang, Yuan Xie, Andrés Takach
2012	J	`jnl`	Performance/Thermal-Aware Design of 3D-Stacked L2 Caches for CMPs. ACM Trans. Design Autom. Electr. Syst. Guangyu Sun, Huazhong Yang, Yuan Xie
2012	A*	`conf`	Point and discard: a hard-error-tolerant architecture for non-volatile last level caches. DAC Jue Wang, Xiangyu Dong, Yuan Xie
2012	J	`jnl`	Power Analysis Attack Resistance Engineering by Dynamic Voltage and Frequency Scaling. ACM Trans. Embed. Comput. Syst. Shengqi Yang, Pallav Gupta, Marilyn Wolf, Dimitrios N. Serpanos, Vijaykrishnan Narayanan, Yuan Xie
2012	—	`conf`	Temporal Performance Degradation under RTN: Evaluation and Mitigation for Nanoscale Circuits. ISVLSI Hong Luo, Yu Wang, Yu Cao, Yuan Xie, Yuchun Ma, Huazhong Yang
2012	—	`conf`	Thermal-aware power network design for IR drop reduction in 3D ICs. ASP-DAC Zuowei Li, Yuchun Ma, Qiang Zhou, Yici Cai, Yu Wang, Tingting Huang, Yuan Xie
2012	—	`conf`	Yield-aware time-efficient testing and self-fixing design for TSV-based 3D ICs. ASP-DAC Jing Xie, Yu Wang, Yuan Xie
2011	—	`conf`	A frequent-value based PRAM memory architecture. ASP-DAC Guangyu Sun, Dimin Niu, Jin Ouyang, Yuan Xie
2011	—	`conf`	AdaMS: Adaptive MLC/SLC phase-change memory design for file storage. ASP-DAC Xiangyu Dong, Yuan Xie
2011	A	`conf`	An energy-efficient 3D CMP design with fine-grained voltage scaling. DATE Jishen Zhao, Xiangyu Dong, Yuan Xie
2011	A	`conf`	Analysis and mitigation of lateral thermal blockage effect of through-silicon-via in 3D IC designs. ISLPED Yibo Chen, Eren Kursun, Dave Motschman, Charles Johnson, Yuan Xie
2011	A*	`conf`	Architecting on-chip interconnects for stacked 3D STT-RAM caches in CMPs. ISCA Asit K. Mishra, Xiangyu Dong, Guangyu Sun, Yuan Xie, Narayanan Vijaykrishnan, Chita R. Das
2011	A*	`conf`	Automated mapping for reconfigurable single-electron transistor arrays. DAC Yung-Chih Chen, Soumya Eachempati, Chun-Yao Wang, Suman Datta, Yuan Xie, Vijaykrishnan Narayanan
2011	A	`conf`	Bandwidth-aware reconfigurable cache design with hybrid memory technologies. ICCAD Jishen Zhao, Cong Xu, Yuan Xie
2011	A	`conf`	Design implications of memristor-based RRAM cross-point structures. DATE Cong Xu, Xiangyu Dong, Norman P. Jouppi, Yuan Xie
2011	A	`conf`	Device-architecture co-optimization of STT-RAM based memory for low power embedded systems. ICCAD Cong Xu, Dimin Niu, Xiaochun Zhu, Seung-Hyuk Kang, Matt Nowak, Yuan Xie
2011	J	`jnl`	Editorial- three-dimensional integrated circuits design. IET Comput. Digit. Tech. Yuan Xie, Pol Marchal
2011	—	`conf`	Enabling architectural innovations using non-volatile memory. ACM Great Lakes Symposium on VLSI Vijaykrishnan Narayanan, Vinay Saripalli, Karthik Swaminathan, Ravindhiran Mukundrajan, Guangyu Sun, Yuan Xie, Suman Datta
2011	—	`conf`	Enabling quality-of-service in nanophotonic network-on-chip. ASP-DAC Jin Ouyang, Yuan Xie
2011	C	`conf`	Energy-efficient multi-level cell phase-change memory system with data encoding. ICCD Jue Wang, Xiangyu Dong, Guangyu Sun, Dimin Niu, Yuan Xie
2011	J	`jnl`	Exploiting Heterogeneity for Energy Efficiency in Chip Multiprocessors. IEEE J. Emerg. Sel. Topics Circuits Syst. Vinay Saripalli, Guangyu Sun, Asit K. Mishra, Yuan Xie, Suman Datta, Vijaykrishnan Narayanan
2011	C	`conf`	Exploring the vulnerability of CMPs to soft errors with 3D stacked non-volatile memory. ICCD Guangyu Sun, Eren Kursun, Jude A. Rivers, Yuan Xie
2011	A	`conf`	F ICS Jin Ouyang, Chuan Yang, Dimin Niu, Yuan Xie, Zhiwen Liu
2011	J	`jnl`	Hybrid checkpointing using emerging nonvolatile memories for future exascale systems. ACM Trans. Archit. Code Optim. Xiangyu Dong, Yuan Xie, Naveen Muralimanohar, Norman P. Jouppi
2011	—	`conf`	Impact of Circuit Degradation on FPGA Design Security. ISVLSI Han-Wei Chen, Suresh Srinivasan, Yuan Xie, Vijaykrishnan Narayanan
2011	—	`ch.`	Influence of Stacked 3D Memory/Cache Architectures on GPUs. 3D Integration for NoC-based SoC Architectures Ahmed Al-Maashri, Guangyu Sun, Xiangyu Dong, Yuan Xie, Narayanan Vijaykrishnan
2011	J	`jnl`	Leakage Power and Circuit Aging Cooptimization by Gate Replacement Techniques. IEEE Trans. Very Large Scale Integr. Syst. Yu Wang, Xiaoming Chen, Wenping Wang, Yu Cao, Yuan Xie, Huazhong Yang
2011	J	`jnl`	Modeling, Architecture, and Applications for Emerging Memory Technologies. IEEE Des. Test Comput. Yuan Xie
2011	A*	`conf`	Moguls: a model to explore the memory hierarchy for bandwidth improvements. ISCA Guangyu Sun, Christopher J. Hughes, Changkyu Kim, Jishen Zhao, Cong Xu, Yuan Xie, Yen-Kuang Chen
2011	A*	`conf`	MorphCache: A Reconfigurable Adaptive Multi-level Cache hierarchy. HPCA Shekhar Srikantaiah, Emre Kultursay, Tao Zhang, Mahmut T. Kandemir, Mary Jane Irwin, Yuan Xie
2011	—	`conf`	On-chip hybrid power supply system for wireless sensor nodes. ASP-DAC Wulong Liu, Yu Wang, Wei Liu, Yuchun Ma, Yuan Xie, Huazhong Yang
2011	—	`ed.`	Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, Lausanne, Switzerland, May 2-6, 2011 ACM Great Lakes Symposium on VLSI David Atienza, Yuan Xie, José L. Ayala, Ken S. Stevens
2011	J	`jnl`	Soft Error Rate Analysis for Combinational Logic Using an Accurate Electrical Masking Model. IEEE Trans. Dependable Secur. Comput. Feng Wang, Yuan Xie
2011	J	`jnl`	Stacking magnetic random access memory atop microprocessors: an architecture-level evaluation. IET Comput. Digit. Tech. Xiangyu Dong, Xiaoxia Wu, Yuan Xie, Yiran Chen, Hai (Helen) Li
2011	Misc	`conf`	System-level design space exploration for three-dimensional (3D) SoCs. CODES+ISSS Qiaosha Zou, Yibo Chen, Yuan Xie, Alan Su
2011	J	`jnl`	Temperature-Aware NBTI Modeling and the Impact of Standby Leakage Reduction Techniques on Circuit Performance Degradation. IEEE Trans. Dependable Secur. Comput. Yu Wang, Hong Luo, Ku He, Rong Luo, Huazhong Yang, Yuan Xie
2011	J	`jnl`	Three-dimensional Integrated Circuits: Design, EDA, and Architecture. Found. Trends Electron. Des. Autom. Guangyu Sun, Yibo Chen, Xiangyu Dong, Jin Ouyang, Yuan Xie
2011	J	`jnl`	Variation-Aware Task and Communication Mapping for MPSoC Architecture. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Feng Wang, Yibo Chen, Chrysostomos Nicopoulos, Xiaoxia Wu, Yuan Xie, Narayanan Vijaykrishnan
2010	J	`jnl`	3D Stacked Microprocessor: Are We There Yet? IEEE Micro Gabriel H. Loh, Yuan Xie
2010	—	`conf`	3D memory stacking for fast checkpointing/restore applications. 3DIC Jing Xie, Xiangyu Dong, Yuan Xie
2010	A	`conf`	3D-nonFAR: three-dimensional non-volatile FPGA architecture using phase change memory. ISLPED Yibo Chen, Jishen Zhao, Yuan Xie
2010	—	`conf`	A 3D SoC design for H.264 application with on-chip DRAM stacking. 3DIC Tao Zhang, Kui Wang, Yi Feng, Yan Chen, Qun Li, Bing Shao, Jing Xie, Xiaodi Song, Lian Duan, Yuan Xie, Xu Cheng, Youn-Long Lin
2010	A*	`conf`	A Hybrid solid-state storage architecture for the performance, energy consumption, and lifetime improvement. HPCA Guangyu Sun, Yongsoo Joo, Yibo Chen, Dimin Niu, Yuan Xie, Yiran Chen, Hai Li
2010	—	`conf`	A customized design of DRAM controller for on-chip 3D DRAM stacking. CICC Tao Zhang, Kui Wang, Yi Feng, Xiaodi Song, Lian Duan, Yuan Xie, Xu Cheng, Youn-Long Lin
2010	—	`conf`	Architectural benefits and design challenges for three-dimensional integrated circuits. APCCAS Jing Xie, Jishen Zhao, Xiangyu Dong, Yuan Xie
2010	A*	`conf`	Cost-aware three-dimensional (3D) many-core multiprocessor design. DAC Jishen Zhao, Xiangyu Dong, Yuan Xie
2010	A*	`conf`	Cost-driven 3D integration with interconnect layers. DAC Xiaoxia Wu, Guangyu Sun, Xiangyu Dong, Reetuparna Das, Yuan Xie, Chita R. Das, Jian Li
2010	A	`conf`	Cost-effective integration of three-dimensional (3D) ICs emphasizing testing cost analysis. ICCAD Yibo Chen, Dimin Niu, Yuan Xie, Krishnendu Chakrabarty
2010	J	`jnl`	Design exploration of hybrid caches with disparate memory technologies. ACM Trans. Archit. Code Optim. Xiaoxia Wu, Jian Li, Lixin Zhang, Evan Speight, Ramakrishnan Rajamony, Yuan Xie
2010	—	`conf`	Energy and performance driven circuit design for emerging phase-change memory. ASP-DAC Dimin Niu, Yibo Chen, Xiangyu Dong, Yuan Xie
2010	A	`conf`	Energy- and endurance-aware design of phase change memory caches. DATE Yongsoo Joo, Dimin Niu, Xiangyu Dong, Guangyu Sun, Naehyuck Chang, Yuan Xie
2010	A	`conf`	Evaluation of using inductive/capacitive-coupling vertical interconnects in 3D network-on-chip. ICCAD Jin Ouyang, Jing Xie, Matthew Poremba, Yuan Xie
2010	J	`jnl`	Fabrication Cost Analysis and Cost-Aware Design Space Exploration for 3-D ICs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Xiangyu Dong, Jishen Zhao, Yuan Xie
2010	A*	`conf`	Impact of process variations on emerging memristor. DAC Dimin Niu, Yiran Chen, Cong Xu, Yuan Xie
2010	A*	`conf`	LOFT: A High Performance Network-on-Chip Providing Quality-of-Service Support. MICRO Jin Ouyang, Yuan Xie
2010	A	`conf`	Low-power dual-element memristor based memory design. ISLPED Dimin Niu, Yiran Chen, Yuan Xie
2010	—	`conf`	Minimizing leakage power in aging-bounded high-level synthesis with design time multi- ASP-DAC Yibo Chen, Yuan Xie, Yu Wang, Andrés Takach
2010	A	`conf`	Modeling TSV open defects in 3D-stacked DRAM. ITC Li Jiang, Yuxi Liu, Lian Duan, Yuan Xie, Qiang Xu
2010	—	`conf`	Parametric yield driven resource binding in behavioral synthesis with multi- ASP-DAC Yibo Chen, Yuan Xie, Yu Wang, Andrés Takach
2010	Misc	`conf`	Processor Architecture Design Using 3D Integration Technology. VLSI Design Yuan Xie
2010	A	`conf`	Simple but Effective Heterogeneous Main Memory with On-Chip Memory Controller Support. SC Xiangyu Dong, Yuan Xie, Naveen Muralimanohar, Norman P. Jouppi
2010	J	`jnl`	Test-access mechanism optimization for core-based three-dimensional SOCs. Microelectron. J. Xiaoxia Wu, Yibo Chen, Krishnendu Chakrabarty, Yuan Xie
2010	—	`conf`	Three-dimensional integrated circuits (3D IC) floorplan and power/ground network co-synthesis. ASP-DAC Paul Falkenstern, Yuan Xie, Yao-Wen Chang, Yu Wang
2010	J	`jnl`	Total Power Optimization for Combinational Logic Using Genetic Algorithms. J. Signal Process. Syst. Wei-Lun Hung, Yuan Xie, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin
2010	J	`jnl`	Variable-Latency Adder (VL-Adder) Designs for Low Power and NBTI Tolerance. IEEE Trans. Very Large Scale Integr. Syst. Yiran Chen, Hai Li, Cheng-Kok Koh, Guangyu Sun, Jing Li, Yuan Xie, Kaushik Roy
2009	C	`conf`	3D GPU architecture using cache stacking: Performance, cost, power and thermal analysis. ICCD Ahmed Al-Maashri, Guangyu Sun, Xiangyu Dong, Vijay Narayanan, Yuan Xie
2009	—	`conf`	3D optical networks-on-chip (NoC) for multiprocessor systems-on-chip (MPSoC). 3DIC Yaoyao Ye, Lian Duan, Jiang Xu, Jin Ouyang, Mo Kwai Hung, Yuan Xie
2009	—	`conf`	A criticality-driven microarchitectural three dimensional (3D) floorplanner. ASP-DAC Srinath Sridharan, Michael DeBole, Guangyu Sun, Yuan Xie, Vijaykrishnan Narayanan
2009	—	`conf`	A framework for estimating NBTI degradation of microarchitectural components. ASP-DAC Michael DeBole, Krishnan Ramakrishnan, Varsha Balakrishnan, Wenping Wang, Hong Luo, Yu Wang, Yuan Xie, Yu Cao, Narayanan Vijaykrishnan
2009	A*	`conf`	A novel architecture of the 3D stacked MRAM L2 cache for CMPs. HPCA Guangyu Sun, Xiangyu Dong, Yuan Xie, Jian Li, Yiran Chen
2009	—	`conf`	Arithmetic unit design using 180nm TSV-based 3D stacking technology. 3DIC Jin Ouyang, Guangyu Sun, Yibo Chen, Lian Duan, Tao Zhang, Yuan Xie, Mary Jane Irwin
2009	Misc	`conf`	CheckerCore: enhancing an FPGA soft core to capture worst-case execution times. CASES Jin Ouyang, Raghuveer Raghavendra, Sibin Mohan, Tao Zhang, Yuan Xie, Frank Mueller
2009	A	`conf`	Emerging technologies and their impact on system design. ISLPED Norman P. Jouppi, Yuan Xie
2009	A	`conf`	Exploration of 3D stacked L2 cache design for high performance and efficient thermal control. ISLPED Guangyu Sun, Xiaoxia Wu, Yuan Xie
2009	A	`conf`	Gate replacement techniques for simultaneous leakage and aging optimization. DATE Yu Wang, Xiaoming Chen, Wenping Wang, Yu Cao, Yuan Xie, Huazhong Yang
2009	J	`jnl`	Guest Editors' Introduction: Opportunities and Challenges of 3D Integration. IEEE Des. Test Comput. David S. Kung, Yuan Xie
2009	A*	`conf`	Hybrid cache architecture with disparate memory technologies. ISCA Xiaoxia Wu, Jian Li, Lixin Zhang, Evan Speight, Ramakrishnan Rajamony, Yuan Xie
2009	A	`conf`	Intrinsic NBTI-variability aware statistical pipeline performance assessment and tuning. ICCAD Balaji Vaidyanathan, Anthony S. Oates, Yuan Xie
2009	—	`conf`	Investigation and comparison of thermal distribution in synchronous and asynchronous 3D ICs. 3DIC Brent Hollosi, Tao Zhang, Ravi Sankar Parameswaran Nair, Yuan Xie, Jia Di, Scott C. Smith
2009	A	`conf`	Leveraging 3D PCRAM technologies to reduce checkpoint overhead for future exascale systems. SC Xiangyu Dong, Naveen Muralimanohar, Norman P. Jouppi, Richard Kaufmann, Yuan Xie
2009	J	`jnl`	Modeling Soft Errors at the Device and Logic Levels for Combinational Circuits. IEEE Trans. Dependable Secur. Comput. Rajaraman Ramanarayanan, Vijay Degalahal, Krishnan Ramakrishnan, Jungsub Kim, Vijaykrishnan Narayanan, Yuan Xie, Mary Jane Irwin, Kenan Unlu
2009	—	`conf`	NBTI-aware statistical circuit delay assessment. ISQED Balaji Vaidyanathan, Anthony S. Oates, Yuan Xie, Yu Wang
2009	—	`conf`	Networks-on-chip in emerging interconnect paradigms: Advantages and challenges. NOCS Luca P. Carloni, Partha Pande, Yuan Xie
2009	—	`conf`	On the efficacy of input Vector Control to mitigate NBTI effects and leakage power. ISQED Yu Wang, Xiaoming Chen, Wenping Wang, Varsha Balakrishnan, Yu Cao, Yuan Xie, Huazhong Yang
2009	A	`conf`	PCRAMsim: System-level performance, energy, and area modeling for Phase-Change RAM. ICCAD Xiangyu Dong, Norman P. Jouppi, Yuan Xie
2009	—	`conf`	Power and area reduction using carbon nanotube bundle interconnect in global clock tree distribution network. NANOARCH Yuan Xie, Soumya Eachempati, Aditya Yanamandra, Vijaykrishnan Narayanan, Mary Jane Irwin
2009	A	`conf`	Power and performance of read-write aware Hybrid Caches with non-volatile memories. DATE Xiaoxia Wu, Jian Li, Lixin Zhang, Evan Speight, Yuan Xie
2009	J	`jnl`	Process-Variation-Aware Adaptive Cache Architecture and Management. IEEE Trans. Computers Madhu Mutyam, Feng Wang, Krishnan Ramakrishnan, Vijaykrishnan Narayanan, Mahmut T. Kandemir, Yuan Xie, Mary Jane Irwin
2009	J	`jnl`	Scan-chain design and optimization for three-dimensional integrated circuits. ACM J. Emerg. Technol. Comput. Syst. Xiaoxia Wu, Paul Falkenstern, Krishnendu Chakrabarty, Yuan Xie
2009	J	`jnl`	Statistical High-Level Synthesis under Process Variability. IEEE Des. Test Comput. Yuan Xie, Yibo Chen
2009	—	`conf`	System-level cost analysis and design exploration for three-dimensional integrated circuits (3D ICs). ASP-DAC Xiangyu Dong, Yuan Xie
2009	J	`jnl`	Temperature-Aware NBTI Modeling Techniques in Digital Circuits. IEICE Trans. Electron. Hong Luo, Yu Wang, Rong Luo, Huazhong Yang, Yuan Xie
2009	C	`conf`	Test-wrapper optimization for embedded cores in TSV-based three-dimensional SOCs. ICCD Brandon Noia, Krishnendu Chakrabarty, Yuan Xie
2009	—	`conf`	Tolerating process variations in high-level synthesis using transparent latches. ASP-DAC Yibo Chen, Yuan Xie
2009	—	`conf`	Variation-aware resource sharing and binding in behavioral synthesis. ASP-DAC Feng Wang, Yuan Xie, Andrés Takach
2008	A	`conf`	A Variation Aware High Level Synthesis Framework. DATE Feng Wang, Guangyu Sun, Yuan Xie
2008	—	`conf`	A low-power phase change memory based hybrid cache architecture. ACM Great Lakes Symposium on VLSI Prasanth Mangalagiri, Karthik Sarpatwari, Aditya Yanamandra, Vijaykrishnan Narayanan, Yuan Xie, Mary Jane Irwin, Osama Awadel Karim
2008	J	`jnl`	Case Study of Reliability-Aware and Low-Power Design. IEEE Trans. Very Large Scale Integr. Syst. Shengqi Yang, Wenping Wang, Tiehan Lv, Wayne H. Wolf, Narayanan Vijaykrishnan, Yuan Xie
2008	A*	`conf`	Circuit and microarchitecture evaluation of 3D stacking magnetic RAM (MRAM) as a universal memory replacement. DAC Xiangyu Dong, Xiaoxia Wu, Guangyu Sun, Yuan Xie, Hai Li, Yiran Chen
2008	C	`conf`	Comparative analysis of NBTI effects on low power and high performance flip-flops. ICCD Krishnan Ramakrishnan, Xiaoxia Wu, Narayanan Vijaykrishnan, Yuan Xie
2008	J	`jnl`	Design Space Exploration for 3-D Cache. IEEE Trans. Very Large Scale Integr. Syst. Yuh-Fang Tsai, Feng Wang, Yuan Xie, Narayanan Vijaykrishnan, Mary Jane Irwin
2008	J	`jnl`	Editorial: Special issue on 3D integrated circuits and microarchitectures. ACM J. Emerg. Technol. Comput. Syst. Yuan Xie, Jason Cong, Paul D. Franzon
2008	A	`conf`	Embedded Multi-Processor System-on-chip (MPSoC) design considering process variations. IPDPS Feng Wang, Yuan Xie
2008	—	`conf`	Hierarchical Soft Error Estimation Tool (HSEET). ISQED Krishnan Ramakrishnan, R. Rajaraman, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin, Kenan Unlu
2008	—	`conf`	ILP-based scheme for timing variation-aware scheduling and resource binding. SoCC Yibo Chen, Jin Ouyang, Yuan Xie
2008	A*	`conf`	MIRA: A Multi-layered On-Chip Interconnect Router Architecture. ISCA Dongkook Park, Soumya Eachempati, Reetuparna Das, Asit K. Mishra, Yuan Xie, Narayanan Vijaykrishnan, Chita R. Das
2008	—	`conf`	Power optimization for FinFET-based circuits using genetic algorithms. SoCC Jin Ouyang, Yuan Xie
2008	—	`conf`	Technology, CAD tools, and designs for emerging 3D integration technology. ACM Great Lakes Symposium on VLSI Syed M. Alam, Mike Ignatowski, Yuan Xie
2008	A	`conf`	Test-Access Solutions for Three-Dimensional SOCs. ITC Xiaoxia Wu, Yibo Chen, Krishnendu Chakrabarty, Yuan Xie
2008	C	`conf`	Test-access mechanism optimization for core-based three-dimensional SOCs. ICCD Xiaoxia Wu, Yibo Chen, Krishnendu Chakrabarty, Yuan Xie
2008	—	`conf`	Thermal-aware Design Considerations for Application-Specific Instruction Set Processor. SASP Hai Lin, Guangyu Sun, Yunsi Fei, Yuan Xie, Anand Sivasubramaniam
2008	A	`conf`	Thermal-aware reliability analysis for platform FPGAs. ICCAD Prasanth Mangalagiri, Sungmin Bae, Krishnan Ramakrishnan, Yuan Xie, Vijaykrishnan Narayanan
2008	J	`jnl`	Toward Increasing FPGA Lifetime. IEEE Trans. Dependable Secur. Comput. Suresh Srinivasan, Krishnan Ramakrishnan, Prasanth Mangalagiri, Yuan Xie, Vijaykrishnan Narayanan, Mary Jane Irwin, Karthik Sarpatwari
2008	—	`conf`	Two-dimensional crosstalk avoidance codes. SiPS Xuebin Wu, Zhiyuan Yan, Yuan Xie
2008	—	`conf`	Variability-driven module selection with joint design time optimization and post-silicon tuning. ASP-DAC Feng Wang, Xiaoxia Wu, Yuan Xie
2007	—	`conf`	A Novel Gate-Level NBTI Delay Degradation Model with Stacking Effect. PATMOS Hong Luo, Yu Wang, Ku He, Rong Luo, Huazhong Yang, Yuan Xie
2007	A	`conf`	A novel criticality computation method in statistical timing analysis. DATE Feng Wang, Yuan Xie, Hai Ju
2007	A*	`conf`	A novel dimensionally-decomposed router for on-chip communication in 3D architectures. ISCA Jongman Kim, Chrysostomos Nicopoulos, Dongkook Park, Reetuparna Das, Yuan Xie, Narayanan Vijaykrishnan, Mazin S. Yousif, Chita R. Das
2007	Misc	`conf`	Architecting Microprocessor Components in 3D Design Space. VLSI Design Balaji Vaidyanathan, Wei-Lun Hung, Feng Wang, Yuan Xie, Narayanan Vijaykrishnan, Mary Jane Irwin
2007	J	`jnl`	Code Compression for VLIW Embedded Systems Using a Self-Generating Table. IEEE Trans. Very Large Scale Integr. Syst. Chang Hong Lin, Yuan Xie, Wayne H. Wolf
2007	J	`jnl`	Code Decompression Unit Design for VLIW Embedded Processors. IEEE Trans. Very Large Scale Integr. Syst. Yuan Xie, Wayne H. Wolf, Haris Lekatsas
2007	—	`conf`	Collaborative VLSI-CAD Instruction in the Digital Sandbox. MSE Alex K. Jones, Steven P. Levitan, Rob A. Rutenbar, Yuan Xie
2007	C	`conf`	FPGA routing architecture analysis under variations. ICCD Suresh Srinivasan, Prasanth Mangalagiri, Yuan Xie, Narayanan Vijaykrishnan
2007	J	`jnl`	Leakage-Aware Interconnect for On-Chip Network CoRR Yuh-Fang Tsai, Vijaykrishnan Narayanan, Yuan Xie, Mary Jane Irwin
2007	—	`conf`	Modeling of PMOS NBTI Effect Considering Temperature Variation. ISQED Hong Luo, Yu Wang, Ku He, Rong Luo, Huazhong Yang, Yuan Xie
2007	J	`jnl`	On-chip bus thermal analysis and optimisation. IET Comput. Digit. Tech. Feng Wang, Michael DeBole, Xiaoxia Wu, Yuan Xie, Narayanan Vijaykrishnan, Mary Jane Irwin
2007	J	`jnl`	Processor Design in 3D Die-Stacking Technologies. IEEE Micro Gabriel H. Loh, Yuan Xie, Bryan Black
2007	J	`jnl`	Reliability-Centric High-Level Synthesis CoRR Suleyman Tosun, Nazanin Mansouri, Ercument Arvas, Mahmut T. Kandemir, Yuan Xie
2007	J	`jnl`	Reliability-aware Co-synthesis for Embedded Systems. J. VLSI Signal Process. Yuan Xie, Lin Li, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin
2007	C	`conf`	Scan chain design for three-dimensional integrated circuits (3D ICs). ICCD Xiaoxia Wu, Paul Falkenstern, Yuan Xie
2007	Misc	`conf`	Soft Error Rate Analysis for Combinational Logic Using An Accurate Electrical Masking Model. VLSI Design Feng Wang, Yuan Xie, R. Rajaraman, Balaji Vaidyanathan
2007	A	`conf`	Temperature-aware NBTI modeling and the impact of input vector control on performance degradation. DATE Yu Wang, Hong Luo, Ku He, Rong Luo, Huazhong Yang, Yuan Xie
2007	J	`jnl`	Thermal-Aware Task Allocation and Scheduling for Embedded Systems CoRR Wei-Lun Hung, Yuan Xie, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin
2007	—	`conf`	Variation Analysis of CAM Cells. ISQED Amol Mupid, Madhu Mutyam, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin
2007	—	`conf`	Variation Impact on SER of Combinational Circuits. ISQED Krishnan Ramakrishnan, R. Rajaraman, Sivaprakasam Suresh, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin
2007	A	`conf`	Variation-aware task allocation and scheduling for MPSoC. ICCAD Feng Wang, Chrysostomos Nicopoulos, Xiaoxia Wu, Yuan Xie, Narayanan Vijaykrishnan
2006	Misc	`conf`	A Hybrid SoC Interconnect with Dynamic TDMA-Based Transaction-Less Buses and On-Chip Networks. VLSI Design Thomas D. Richardson, Chrysostomos Nicopoulos, Dongkook Park, Narayanan Vijaykrishnan, Yuan Xie, Chita R. Das, Vijay Degalahal
2006	—	`conf`	Analysis of Subthreshold Finfet Circuits for Ultra-Low Power Design. SoCC Xiaoxia Wu, Feng Wang, Yuan Xie
2006	J	`jnl`	Code Compression for Embedded VLIW Processors Using Variable-to-Fixed Coding. IEEE Trans. Very Large Scale Integr. Syst. Yuan Xie, Wayne H. Wolf, Haris Lekatsas
2006	—	`conf`	Crosstalk-Aware Energy Efficient Encoding for Instruction Bus through Code Compression. SoCC Balaji Vaidyanathan, Yuan Xie
2006	—	`conf`	Delay and Energy Efficient Data Transmission for On-Chip Buses. ISVLSI Madhu Mutyam, Melvin Eze, Narayanan Vijaykrishnan, Yuan Xie
2006	—	`conf`	Dependability Analysis of Nano-scale FinFET circuits. ISVLSI Feng Wang, Yuan Xie, Kerry Bernstein, Yan Luo
2006	A*	`conf`	Design and Management of 3D Chip Multiprocessors Using Network-in-Memory. ISCA Feihui Li, Chrysostomos Nicopoulos, Thomas D. Richardson, Yuan Xie, Narayanan Vijaykrishnan, Mahmut T. Kandemir
2006	J	`jnl`	Design space exploration for 3D architectures. ACM J. Emerg. Technol. Comput. Syst. Yuan Xie, Gabriel H. Loh, Bryan Black, Kerry Bernstein
2006	A*	`conf`	FLAW: FPGA lifetime awareness. DAC Suresh Srinivasan, Prasanth Mangalagiri, Yuan Xie, Narayanan Vijaykrishnan, Karthik Sarpatwari
2006	A	`conf`	Guaranteeing performance yield in high-level synthesis. ICCAD Wei-Lun Hung, Xiaoxia Wu, Yuan Xie
2006	—	`conf`	Interconnect and Thermal-aware Floorplanning for 3D Microprocessors. ISQED Wei-Lun Hung, Greg M. Link, Yuan Xie, Narayanan Vijaykrishnan, Mary Jane Irwin
2006	—	`conf`	Leakage Optimized DECAP Design for FPGAs. APCCAS Balaji Vaidyanathan, Suresh Srinivasan, Yuan Xie, Narayanan Vijaykrishnan, Rong Luo
2006	—	`conf`	Modeling the Impact of Process Variation on Critical Charge Distribution. SoCC Qian Ding, Rong Luo, Hui Wang, Huazhong Yang, Yuan Xie
2006	A	`conf`	On-chip bus thermal analysis and optimization. DATE Feng Wang, Yuan Xie, Narayanan Vijaykrishnan, Mary Jane Irwin
2006	—	`conf`	Optimal topology exploration for application-specific 3D architectures. ASP-DAC Ozcan Ozturk, Feng Wang, Mahmut T. Kandemir, Yuan Xie
2006	J	`jnl`	Reliability Concerns in Embedded System Designs. Computer Narayanan Vijaykrishnan, Yuan Xie
2006	—	`conf`	Reliability-Aware SOC Voltage Islands Partition and Floorplan. ISVLSI Shengqi Yang, Wayne H. Wolf, Narayanan Vijaykrishnan, Yuan Xie
2006	Misc	`conf`	SEAT-LA: A Soft Error Analysis Tool for Combinational Logic. VLSI Design R. Rajaraman, Jungsub Kim, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin
2006	J	`jnl`	Temperature-Aware Task Allocation and Scheduling for Embedded Multiprocessor Systems-on-Chip (MPSoC) Design. J. VLSI Signal Process. Yuan Xie, Wei-Lun Hung
2005	Misc	`conf`	Accurate Stacking Effect Macro-Modeling of Leakage Power in Sub-100nm Circuits. VLSI Design Shengqi Yang, Wayne H. Wolf, Narayanan Vijaykrishnan, Yuan Xie, Wenping Wang
2005	—	`conf`	Adaptive Power Management in Software Radios Using Resolution Adaptive Analog to Digital Converters. ISVLSI Daniel Hostetler, Yuan Xie
2005	—	`conf`	An ILP Formulation for Reliability-Oriented High-Level Synthesis. ISQED Suleyman Tosun, Ozcan Ozturk, Nazanin Mansouri, Ercument Arvas, Mahmut T. Kandemir, Yuan Xie, Wei-Lun Hung
2005	—	`conf`	Designing reliable circuit in the presence of soft errors. ASP-DAC Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin
2005	—	`conf`	FD-HGAC: a hybrid heuristic/genetic algorithm hardware/software co-synthesis framework with fault detection. ASP-DAC John Conner, Yuan Xie, Mahmut T. Kandemir, Robert P. Dick, Greg M. Link
2005	Misc	`conf`	Influence of Leakage Reduction Techniques on Delay/Leakage Uncertainty. VLSI Design Yuh-Fang Tsai, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin
2005	A	`conf`	Leakage-Aware Interconnect for On-Chip Network. DATE Yuh-Fang Tsai, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin
2005	—	`conf`	Low-leakage robust SRAM cell design for sub-100nm technologies. ASP-DAC Shengqi Yang, Wayne H. Wolf, Wenping Wang, Narayanan Vijaykrishnan, Yuan Xie
2005	A	`conf`	Power Attack Resistant Cryptosystem Design: A Dynamic Voltage and Frequency Switching Approach. DATE Shengqi Yang, Wayne H. Wolf, Narayanan Vijaykrishnan, Dimitrios N. Serpanos, Yuan Xie
2005	—	`conf`	Reliability-Centric Hardware/Software Co-Design. ISQED Suleyman Tosun, Nazanin Mansouri, Ercument Arvas, Mahmut T. Kandemir, Yuan Xie, Wei-Lun Hung
2005	A	`conf`	Reliability-Centric High-Level Synthesis. DATE Suleyman Tosun, Nazanin Mansouri, Ercument Arvas, Mahmut T. Kandemir, Yuan Xie
2005	C	`conf`	Temperature-Aware Voltage Islands Architecting in System-on-Chip Design. ICCD Wei-Lun Hung, Greg M. Link, Yuan Xie, Narayanan Vijaykrishnan, Nagu R. Dhanwada, John Conner
2005	C	`conf`	Temperature-Sensitive Loop Parallelization for Chip Multiprocessors. ICCD Sri Hari Krishna Narayanan, Guilin Chen, Mahmut T. Kandemir, Yuan Xie
2005	—	`conf`	Thermal-Aware Floorplanning Using Genetic Algorithms. ISQED Wei-Lun Hung, Yuan Xie, Narayanan Vijaykrishnan, Charles Addo-Quaye, Theo Theocharides, Mary Jane Irwin
2005	A	`conf`	Thermal-Aware Task Allocation and Scheduling for Embedded Systems. DATE Wei-Lun Hung, Yuan Xie, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin
2005	C	`conf`	Three-Dimensional Cache Design Exploration Using 3DCacti. ICCD Yuh-Fang Tsai, Yuan Xie, Narayanan Vijaykrishnan, Mary Jane Irwin
2004	—	`conf`	Design of a nanosensor array architecture. ACM Great Lakes Symposium on VLSI Wei Xu, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin
2004	A	`conf`	Improving soft-error tolerance of FPGA configuration bits. ICCAD Suresh Srinivasan, Aman Gayasen, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Yuan Xie, Mary Jane Irwin
2004	A	`conf`	LZW-Based Code Compression for VLIW Embedded Systems. DATE Chang Hong Lin, Yuan Xie, Wayne H. Wolf
2004	—	`conf`	Reliability-Aware Co-Synthesis for Embedded Systems. ASAP Yuan Xie, Lin Li, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin
2004	—	`conf`	The Effect of Threshold Voltages on the Soft Error Rate. ISQED Vijay Degalahal, Rajaraman Ramanarayanan, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin
2004	C	`conf`	Thermal-Aware IP Virtualization and Placement for Networks-on-Chip Architecture. ICCD Wei-Lun Hung, Charles Addo-Quaye, Theo Theocharides, Yuan Xie, Narayanan Vijaykrishnan, Mary Jane Irwin
2003	J	`jnl`	Augmenting Platform-Based Design with Synthesis Tools. J. Circuits Syst. Comput. Yuan Xie, Jiang Xu, Wayne H. Wolf
2003	B	`conf`	Code Compression Using Variable-to-fixed Coding Based on Arithmetic Coding. DCC Yuan Xie, Wayne H. Wolf, Haris Lekatsas
2003	—	`conf`	Effect of Power Optimizations on Soft Error Rate. VLSI-SoC (Selected Papers) Vijay Degalahal, Rajaraman Ramanarayanan, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin
2003	A	`conf`	Profile-Driven Selective Code Compression. DATE Yuan Xie, Wayne H. Wolf, Haris Lekatsas
2002	—	`conf`	Code Compression for VLIW Processors Using Variable-to-Fixed Coding. ISSS Haris Lekatsas, Wayne H. Wolf, Yuan Xie
2001	A*	`conf`	A code decompression architecture for VLIW processors. MICRO Yuan Xie, Wayne H. Wolf, Haris Lekatsas
2001	A	`conf`	Allocation and scheduling of conditional task graph in hardware/software co-synthesis. DATE Yuan Xie, Wayne H. Wolf
2001	B	`conf`	Code Compression for VLIW Processors. Data Compression Conference Yuan Xie, Haris Lekatsas, Wayne H. Wolf
2000	—	`conf`	Co-synthesis with custom ASICs. ASP-DAC Yuan Xie, Wayne H. Wolf