Yuan Wang - RankMe

173 papers A* 5A 12B 1C 25Journal 81Unranked 49

Year	Rank	Type	Title / Venue / Authors
2026	—	`conf`	32.3 An 85.1dB-SNDR 8MS/s Incremental Pipeline ADC with Dual-Residue-Assisted Exponential Quantization. ISSCC Zongnan Wang, Bingrui Li, Haoyang Luo, Chenyuan Chu, Jiachang Yang, Yuan Wang, Xiyuan Tang
2026	J	`jnl`	A 1131-kb/mm IEEE J. Solid State Circuits Jiahao Song, Xiyuan Tang, Bocheng Xu, Haikang Diao, Haoyang Luo, Zihan Wu, Yuan Wang, Runsheng Wang, Ru Huang
2026	—	`conf`	A 28nm Mode-Reconfigurable CAM-CIM Hybrid Complete 3-SAT Solver Supporting Conflict-Driven Clause Learning with 100% Solvability. ISSCC Zihan Wu, Xiyuan Tang, Lishan Lin, Youming Yang, Haoyang Luo, Bocheng Xu, Yitao Liang, Xiaochen Bo, Yuan Wang
2026	J	`jnl`	A RISC-V based heterogeneous neuromorphic system with dynamic reconfigurable computing for edge AI. Microelectron. J. Zhaoxiang Zhang, Yi Zhong, Zilin Wang, Youming Yang, Tao Zhang, Jinhao Ruan, Yipeng Gao, Yuan Wang
2026	J	`jnl`	An Easy-Driving Incremental Zoom ADC With Skipped Sampling Scheme and NS-SAR Quantizer. IEEE J. Solid State Circuits Zongnan Wang, Lu Jie, Zichen Kong, Mingtao Zhan, Yi Zhong, Yuan Wang, Xiyuan Tang
2026	—	`conf`	CREATE: Cross-Layer Resilience Characterization and Optimization for Efficient yet Reliable Embodied AI Systems. ASPLOS (2) Tong Xie, Yijiahao Qi, Jinqi Wen, Zishen Wan, Yanchi Dong, Zihao Wang, Shaofei Cai, Yitao Liang, Tianyu Jia, Yuan Wang, Runsheng Wang, Meng Li
2026	J	`jnl`	CREATE: Cross-Layer Resilience Characterization and Optimization for Efficient yet Reliable Embodied AI Systems. CoRR Tong Xie, Yijiahao Qi, Jinqi Wen, Zishen Wan, Yanchi Dong, Zihao Wang, Shaofei Cai, Yitao Liang, Tianyu Jia, Yuan Wang, Runsheng Wang, Meng Li
2026	J	`jnl`	EA-HWP: An Efficient CNN/SNN Accelerator With Hybrid Weight Precision. IEEE Trans. Circuits Syst. II Express Briefs Zilin Wang, Zehong Ou, Yi Zhong, Tao Zhang, Youming Yang, Zhaoxiang Zhang, Shuo Feng, Yipeng Gao, Jinhao Ruan, Yuan Wang
2026	J	`jnl`	PAICar: a prototype of an embodied neuromorphic intelligent robot platform. Sci. China Inf. Sci. Shuo Feng, Mingkai Liu, Jingyi Zhong, Guang Chen, Yi Zhong, Zilin Wang, Chenglong Zou, Xiaoxin Cui, Jian Cao, Yuan Wang
2026	J	`jnl`	SKADI: A 28-nm Complete K-SAT Solver Featuring Bidirectional In-Memory Deduction and Incremental Updating. IEEE J. Solid State Circuits Zihan Wu, Xiyuan Tang, Tao Zhang, Lishan Lin, Haoyang Luo, Bocheng Xu, Zhongyi Wu, Jiahao Song, Yitao Liang, Xiaochen Bo, Yuan Wang
2025	—	`conf`	37.5 SKADI: A 28nm Complete K-SAT Solver Featuring Dual-Path SRAM-Based Macro and Incremental Update with 100% Solvability. ISSCC Zihan Wu, Xiyuan Tang, Tao Zhang, Lishan Lin, Haoyang Luo, Bocheng Xu, Zhongyi Wu, Jiahao Song, Yitao Liang, Xiaochen Bo, Yuan Wang
2025	—	`conf`	A 184.8dB-FoMs 1.6MS/s Incremental Noise-Shaping Pipeline ADC with Single-Amplification-Based kT/C Noise Cancellation Technique. ISSCC Zongnan Wang, Bingrui Li, Jiajun Tang, Zhongyi Wu, Haoyang Luo, Yuan Wang, Xiyuan Tang
2025	—	`conf`	A 185.2dB-FoMs 8.7aFrms Zoomed Capacitance-to-Digital Converter with Chopping-Based kT/C Noise Cancellation and Add-Then-Subtract Phase-Domain Lead-Compensation Technique. ISSCC Bingrui Li, Zilong Shen, Haoyang Luo, Jiachang Yang, Zongnan Wang, Yuan Wang, Xiyuan Tang
2025	—	`conf`	A 4.82-µW 183.4dB-FoMSNDR CT Incremental Tracking-Zoom Sensor Readout Frontend with Floating-Gm-CCO Integrator. CICC Haoyang Luo, Zongnan Wang, Jiarui Wang, Bingrui Li, Zilong Shen, Yang Liu, Xiaojie Duan, Yuan Wang, Xiyuan Tang
2025	J	`jnl`	A Bit-Partitioned Floating-Point 6T SRAM Computing-in-Memory Macro Based on Dual-Edge Time-Domain Structure. IEEE Trans. Circuits Syst. I Regul. Pap. Chang Xue, Youming Yang, Siyuan He, Gang Du, Yuan Wang, Yandong He
2025	J	`jnl`	A Computing-in-Memory Engine Supporting One-Shot Floating-Point NN Inference and On-Device Fine-Tuning for Edge AI. IEEE J. Solid State Circuits Haikang Diao, Haoyang Luo, Jiahao Song, Bocheng Xu, Runsheng Wang, Yuan Wang, Xiyuan Tang
2025	J	`jnl`	A Multiply-Less Approximate SRAM Compute-In-Memory Macro for Neural-Network Inference. IEEE J. Solid State Circuits Haikang Diao, Yifan He, Xuan Li, Chen Tang, Wenbin Jia, Jinshan Yue, Haoyang Luo, Jiahao Song, Xueqing Li, Huazhong Yang, Hongyang Jia, Yongpan Liu, Yuan Wang, Xiyuan Tang
2025	J	`jnl`	A Segmented Precision Configurable Computing-in-Memory Macro With Dual-Edge Time-Domain Structure. IEEE Solid State Circuits Lett. Chang Xue, Youming Yang, Siyuan He, Gang Du, Yuan Wang, Yandong He
2025	J	`jnl`	A Variation-Tolerant Continuous-Time Ising Machine With eDRAM-Based Spin Interaction and Leaked Negative Feedback Annealing. IEEE J. Solid State Circuits Zihan Wu, Jiahao Song, Xiyuan Tang, Bocheng Xu, Haoyang Luo, Youming Yang, Runsheng Wang, Xiaochen Bo, Yuan Wang
2025	A	`conf`	Adder-DCIM: A Parallel Bit-Flexible Digital CIM Accelerator Joint Model Compression Framework for AdderNet Inference. ICCAD Haikang Diao, Chuyue Tang, Bocheng Xu, Haoyang Luo, Meng Li, Yuan Wang, Xiyuan Tang
2025	C	`conf`	CROSSCUT: A Multi-Core Neuromorphic Accelerator Improving Resource-Utilization. ISCAS Youming Yang, Yi Zhong, Zilin Wang, Tao Zhang, Li Lun, Yingying Cui, Xiaoxin Cui, Song Jia, Yuan Wang
2025	J	`jnl`	Cactus: A Multicore Spiking Neural Network Accelerator With Fine-Grained Structured Weight Sparsity. IEEE Trans. Very Large Scale Integr. Syst. Zilin Wang, Zehong Ou, Yi Zhong, Yuan Wang
2025	C	`conf`	Enabling Fault Isolation in Fault Injection for Automotive-grade Circuits Simulation. ISCAS Yulong Liu, Junhao Lin, Yuheng Li, Pingsheng Zhang, Zenan Yan, Yuan Wang, Song Jia
2025	A	`conf`	FLASH: An Efficient Hardware Accelerator Leveraging Approximate and Sparse FFT for Homomorphic Encryption. DATE Tengyu Zhang, Yufei Xue, Ling Liang, Zhen Gu, Yuan Wang, Runsheng Wang, Ru Huang, Meng Li
2025	C	`conf`	HyNITA: A Neuromorphic Inference and Training Accelerator for Hybrid ANN-SNN Fusion Models. ISCAS Yi Zhong, Li Lun, Zilin Wang, Jinhao Ruan, Yipeng Gao, Xiaoxin Cui, Xing Zhang, Yuan Wang
2025	J	`jnl`	LightMamba: Efficient Mamba Acceleration on FPGA with Quantization and Hardware Co-design. CoRR Renjie Wei, Songqiang Xu, Linfeng Zhong, Zebin Yang, Qingyu Guo, Yuan Wang, Runsheng Wang, Meng Li
2025	A	`conf`	NeuroHexa: A 2D/3D-Scalable Model-Adaptive NoC Architecture for Neuromorphic Computing. DATE Yi Zhong, Zilin Wang, Yipeng Gao, Xiaoxin Cui, Xing Zhang, Yuan Wang
2025	J	`jnl`	PAICORE: A 1.9-Million-Neuron 5.181-TSOPS/W Digital Neuromorphic Processor With Unified SNN-ANN and On-Chip Learning Paradigm. IEEE J. Solid State Circuits Yi Zhong, Yisong Kuang, Kefei Liu, Zilin Wang, Shuo Feng, Guang Chen, Youming Yang, Xiuping Cui, Qiankun Wang, Jian Cao, Song Jia, Yun Liang, Guangyu Sun, Xiaoxin Cui, Ru Huang, Yuan Wang
2025	A*	`conf`	ReaLM: Reliable and Efficient Large Language Model Inference with Statistical Algorithm-Based Fault Tolerance. DAC Tong Xie, Jiawang Zhao, Zishen Wan, Zuodong Zhang, Yuan Wang, Runsheng Wang, Ru Huang, Meng Li
2025	J	`jnl`	ReaLM: Reliable and Efficient Large Language Model Inference with Statistical Algorithm-Based Fault Tolerance. CoRR Tong Xie, Jiawang Zhao, Zishen Wan, Zuodong Zhang, Yuan Wang, Runsheng Wang, Ru Huang, Meng Li
2025	A	`conf`	SEGA-DCIM: Design Space Exploration-Guided Automatic Digital CIM Compiler with Multiple Precision Support. DATE Haikang Diao, Haoyi Zhang, Jiahao Song, Haoyang Luo, Yibo Lin, Runsheng Wang, Yuan Wang, Xiyuan Tang
2025	J	`jnl`	SEGA-DCIM: Design Space Exploration-Guided Automatic Digital CIM Compiler with Multiple Precision Support. CoRR Haikang Diao, Haoyi Zhang, Jiahao Song, Haoyang Luo, Yibo Lin, Runsheng Wang, Yuan Wang, Xiyuan Tang
2025	A	`conf`	SpecMamba: Accelerating Mamba Inference on FPGA with Speculative Decoding. ICCAD Linfeng Zhong, Songqiang Xu, Huifeng Wen, Tong Xie, Qingyu Guo, Yuan Wang, Meng Li
2025	J	`jnl`	TopoSizing: An LLM-aided Framework of Topology-based Understanding and Sizing for AMS Circuits. CoRR Ziming Wei, Zichen Kong, Yuan Wang, David Z. Pan, Xiyuan Tang
2025	A*	`conf`	Towards Effective and Sparse Adversarial Attack on Spiking Neural Networks via Breaking Invisible Surrogate Gradients. CVPR Li Lun, Kunyu Feng, Qinglong Ni, Ling Liang, Yuan Wang, Ying Li, Dunshan Yu, Xiaoxin Cui
2025	J	`jnl`	Towards Effective and Sparse Adversarial Attack on Spiking Neural Networks via Breaking Invisible Surrogate Gradients. CoRR Li Lun, Kunyu Feng, Qinglong Ni, Ling Liang, Yuan Wang, Ying Li, Dunshan Yu, Xiaoxin Cui
2025	J	`jnl`	UniPRE: An SNN-ANN Accelerator With Unified Max-Pooling Prediction and Redundancy Elimination. IEEE Trans. Circuits Syst. II Express Briefs Tao Zhang, Yi Zhong, Youming Yang, Zilin Wang, Zhaotong Zhang, Yuan Wang
2024	—	`conf`	30.5 A Variation-Tolerant In-eDRAM Continuous-Time Ising Machine Featuring 15-Level Coefficients and Leaked Negative-Feedback Annealing. ISSCC Jiahao Song, Zihan Wu, Xiyuan Tang, Bocheng Xu, Haoyang Luo, Youming Yang, Yuan Wang, Runsheng Wang, Ru Huang
2024	J	`jnl`	A 16.38TOPS and 4.55POPS/W SRAM Computing-in-Memory Macro for Signed Operands Computation and Batch Normalization Implementation. IEEE Trans. Circuits Syst. I Regul. Pap. Xin Qiao, Qingyu Guo, Xiyuan Tang, Jiahao Song, Renjie Wei, Meng Li, Runsheng Wang, Yuan Wang
2024	—	`conf`	A 181.8dB FoMs Zoom Capacitance-to-Digital Converter with kT/C Noise Cancellation and Dead Band Operation. CICC Zilong Shen, Jiajun Tang, Haoyang Luo, Zhongyi Wu, Zongnan Wang, Xing Zhang, Xiyuan Tang, Yuan Wang
2024	J	`jnl`	A 266F IEEE Trans. Circuits Syst. II Express Briefs Haoyi Zhang, Jiahao Song, Haoyang Luo, Xiyuan Tang, Yuan Wang, Runsheng Wang, Ru Huang
2024	—	`conf`	A 28nm 128TFLOPS/W Computing-In-Memory Engine Supporting One-Shot Floating-Point NN Inference and On-Device Fine-Tuning for Edge AI. CICC Haikang Diao, Haoyang Luo, Jiahao Song, Bocheng Xu, Runsheng Wang, Yuan Wang, Xiyuan Tang
2024	J	`jnl`	A 28nm 8Kb Reconfigurable SRAM Computing-In-Memory Macro With Input-Sparsity Optimized DTC for Multi-Mode MAC Operations. IEEE Trans. Circuits Syst. II Express Briefs Kanglin Xiao, Xin Qiao, Xiaoxin Cui, Jiahao Song, Haoyang Luo, Xin'an Wang, Yuan Wang
2024	J	`jnl`	A 4-bit Calibration-Free Computing-In-Memory Macro With 3T1C Current-Programed Dynamic-Cascode Multi-Level-Cell eDRAM. IEEE J. Solid State Circuits Jiahao Song, Xiyuan Tang, Haoyang Luo, Haoyi Zhang, Xin Qiao, Zixuan Sun, Xiangxing Yang, Zihan Wu, Yuan Wang, Runsheng Wang, Ru Huang
2024	J	`jnl`	A 768.7-2124.2 TOPS/W Time-Domain Computing-in-Memory Macro With Low Static Leakage and Precision-Configurable TDC. IEEE Trans. Circuits Syst. II Express Briefs Chang Xue, Xin Qiao, Xu Ren, Gang Du, Yuan Wang, Yandong He
2024	—	`conf`	A Hybrid Heterogeneous Neural Network Accelerator based on Systolic Array. AICAS Zilin Wang, Yi Zhong, Guang Chen, Shuo Feng, Youming Yang, Xiaoxin Cui, Yuan Wang
2024	—	`conf`	A cascaded timestamp-free event camera image compression method for gesture recognition. ISIE Lindong Wu, Xuefei Lv, Shaoning Jin, Chaoyi Ban, Zongwei Wang, Yuan Wang, Yimao Cai
2024	A	`conf`	ASCEND: Accurate yet Efficient End-to-End Stochastic Computing Acceleration of Vision Transformer. DATE Tong Xie, Yixuan Hu, Renjie Wei, Meng Li, Yuan Wang, Runsheng Wang, Ru Huang
2024	J	`jnl`	ASCEND: Accurate yet Efficient End-to-End Stochastic Computing Acceleration of Vision Transformer. CoRR Tong Xie, Yixuan Hu, Renjie Wei, Meng Li, Yuan Wang, Runsheng Wang, Ru Huang
2024	A	`conf`	AdapMoE: Adaptive Sensitivity-based Expert Gating and Management for Efficient MoE Inference. ICCAD Shuzhang Zhong, Ling Liang, Yuan Wang, Runsheng Wang, Ru Huang, Meng Li
2024	J	`jnl`	AdapMoE: Adaptive Sensitivity-based Expert Gating and Management for Efficient MoE Inference. CoRR Shuzhang Zhong, Ling Liang, Yuan Wang, Runsheng Wang, Ru Huang, Meng Li
2024	—	`conf`	An Efficient Spiking Convolutional Architecture with Compressed Address Event Representation and Adaptive Delay Asynchronous Clocks. BioCAS Zhenhui Dai, Li Lun, Zilin Wang, Jiawei Wang, Kunyu Feng, Yuan Wang, Dunshan Yu, Xiaoxin Cui
2024	C	`conf`	An End-to-End SoC for Brain-Inspired CNN-SNN Hybrid Applications. ISCAS Zhaotong Zhang, Yi Zhong, Yingying Cui, Yawei Ding, Yukun Xue, Qibin Li, Ruining Yang, Jian Cao, Yuan Wang
2024	C	`conf`	An Energy-Efficient Differential Frame Convolutional Accelerator with on-Chip Fusion Storage Architecture and Pixel-Level Pipeline Data Flow. ISCAS Zhenhui Dai, Jiawei Wang, Yi Zhong, Kunyu Feng, Cheng Zhao, Yuanyuan Jiang, Peiyu Chen, Yuan Wang, Dunshan Yu, Xiaoxin Cui
2024	J	`jnl`	An eDRAM-Based Computing-in-Memory Macro With Full-Valid-Storage and Channel-Wise-Parallelism for Depthwise Neural Network. IEEE Trans. Circuits Syst. II Express Briefs Xin Qiao, Youming Yang, Chang Xue, Yandong He, Xiaoxin Cui, Song Jia, Yuan Wang
2024	J	`jnl`	BrainQN: Enhancing the Robustness of Deep Reinforcement Learning with Spiking Neural Networks. Adv. Intell. Syst. Shuo Feng, Jian Cao, Zehong Ou, Guang Chen, Yi Zhong, Zilin Wang, Juntong Yan, Jue Chen, Bingsen Wang, Chenglong Zou, Zebang Feng, Yuan Wang
2024	J	`jnl`	CASCADE: A Framework for CNN Accelerator Synthesis With Concatenation and Refreshing Dataflow. IEEE Trans. Circuits Syst. I Regul. Pap. Qingyu Guo, Haoyang Luo, Meng Li, Xiyuan Tang, Yuan Wang
2024	A	`conf`	HG-PIPE: Vision Transformer Acceleration with Hybrid-Grained Pipeline. ICCAD Qingyu Guo, Jiayong Wan, Songqiang Xu, Meng Li, Yuan Wang
2024	J	`jnl`	How the Brain Achieves Real-Time Vision: A Spiking Position Perception Model. IEEE Trans. Cogn. Dev. Syst. Kefei Liu, Jingjie Shang, Xiaoxin Cui, Chenglong Zou, Yisong Kuang, Kanglin Xiao, Yi Zhong, Yuan Wang
2024	J	`jnl`	Investigation and mitigation of Mott neuronal oscillation fluctuation in spiking neural network. Sci. China Inf. Sci. Lindong Wu, Zongwei Wang, Lin Bao, Linbo Shan, Zhizhen Yu, Yunfan Yang, Shuangjie Zhang, Guandong Bai, Cuimei Wang, John Robertson, Yuan Wang, Yimao Cai, Ru Huang
2024	J	`jnl`	Marmotini: A Weight Density Adaptation Architecture With Hybrid Compression Method for Spiking Neural Network. IEEE Trans. Very Large Scale Integr. Syst. Zilin Wang, Yi Zhong, Zehong Ou, Youming Yang, Shuo Feng, Guang Chen, Xiaoxin Cui, Song Jia, Yuan Wang
2024	—	`conf`	MixCIM: A Hybrid-Cell-Based Computing-in-Memory Macro with Less-Data-Movement and Activation-Memory-Reuse for Depthwise Separable Neural Networks. CICC Xin Qiao, Jiahao Song, Youming Yang, Renjie Wei, Xiyuan Tang, Meng Li, Runsheng Wang, Yuan Wang
2024	J	`jnl`	NeuroREC: A 28-nm Efficient Neuromorphic Processor for Radar Emitter Classification. IEEE Trans. Circuits Syst. I Regul. Pap. Zilin Wang, Zehong Ou, Yi Zhong, Youming Yang, Li Lun, Hufei Li, Jian Cao, Xiaoxin Cui, Song Jia, Yuan Wang
2024	J	`jnl`	OASIS: A 28-nm 32-kb SRAM-Based Computing-in-Memory Design With Output Activation Sparsity Support. IEEE Trans. Circuits Syst. II Express Briefs Qingyu Guo, Nanbing Pan, Xin Qiao, Xiaoxin Cui, Yuan Wang
2024	A	`conf`	OSCA: End-to-end Serial Stochastic Computing Neural Acceleration with Fine-grained Scaling and Piecewise Activation. ICCAD Yixuan Hu, Yikang Jia, Meng Li, Yuan Wang, Runsheng Wang, Ru Huang
2024	—	`conf`	On-Chip Incremental Learning based on Unsupervised STDP Implementation. AICAS Guang Chen, Jian Cao, Shuo Feng, Zilin Wang, Yi Zhong, Qibin Li, Xiongbo Zhao, Xing Zhang, Yuan Wang
2024	A*	`conf`	PVTSizing: A TuRBO-RL-Based Batch-Sampling Optimization Framework for PVT-Robust Analog Circuit Synthesis. DAC Zichen Kong, Xiyuan Tang, Wei Shi, Yiheng Du, Yibo Lin, Yuan Wang
2023	—	`conf`	A 150kHz-BW 15-ENOB Incremental Zoom ADC with Skipped Sampling and Single Buffer Embedded Noise-Shaping SAR Quantizer. ISSCC Zongnan Wang, Lu Jie, Zichen Kong, Mingtao Zhan, Yi Zhong, Yuan Wang, Xiyuan Tang
2023	J	`jnl`	A 28 nm 16 Kb Bit-Scalable Charge-Domain Transpose 6T SRAM In-Memory Computing Macro. IEEE Trans. Circuits Syst. I Regul. Pap. Jiahao Song, Xiyuan Tang, Xin Qiao, Yuan Wang, Runsheng Wang, Ru Huang
2023	J	`jnl`	A 28nm 32Kb SRAM Computing-in-Memory Macro With Hierarchical Capacity Attenuator and Input Sparsity-Optimized ADC for 4b Mac Operation. IEEE Trans. Circuits Syst. II Express Briefs Kanglin Xiao, Xiaoxin Cui, Xin Qiao, Jiahao Song, Haoyang Luo, Xin'an Wang, Yuan Wang
2023	—	`conf`	A 28nm 38-to-102-TOPS/W 8b Multiply-Less Approximate Digital SRAM Compute-In-Memory Macro for Neural-Network Inference. ISSCC Yifan He, Haikang Diao, Chen Tang, Wenbin Jia, Xiyuan Tang, Yuan Wang, Jinshan Yue, Xueqing Li, Huazhong Yang, Hongyang Jia, Yongpan Liu
2023	—	`conf`	A 9.7fJ/Conv.-Step Capacitive Sensor Readout Circuit with Incremental Zoomed Time Domain Quantization. CICC Zilong Shen, Xiyuan Tang, Zhongyi Wu, Haoyang Luo, Zongnan Wang, Mingjie Liu, Xing Zhang, Yuan Wang
2023	—	`conf`	A Calibration-Free 15-level/Cell eDRAM Computing-in-Memory Macro with 3T1C Current-Programmed Dynamic-Cascoded MLC achieving 233-to-304-TOPS/W 4b MAC. CICC Jiahao Song, Xiyuan Tang, Haoyang Luo, Haoyi Zhang, Xin Qiao, Zixuan Sun, Xiangxing Yang, Yuan Wang, Runsheng Wang, Ru Huang
2023	A*	`conf`	A New ANN-SNN Conversion Method with High Accuracy, Low Latency and Good Robustness. IJCAI Bingsen Wang, Jian Cao, Jue Chen, Shuo Feng, Yuan Wang
2023	C	`conf`	A Spiking Neural Network Accelerator based on Ping-Pong Architecture with Sparse Spike and Weight. ISCAS Zilin Wang, Yi Zhong, Xiaoxin Cui, Yisong Kuang, Yuan Wang
2023	J	`jnl`	ALEGO: Towards Cost-Aware Architecture and Integration Co-Design for Chiplet-based Spatial Accelerators. CoRR Xiaochen Hao, Zijian Ding, Jieming Yin, Yuan Wang, Yun Liang
2023	A	`conf`	Accurate yet Efficient Stochastic Computing Neural Acceleration with High Precision Residual Fusion. DATE Yixuan Hu, Tengyu Zhang, Renjie Wei, Meng Li, Runsheng Wang, Yuan Wang, Ru Huang
2023	J	`jnl`	An Efficient Neuromorphic Implementation of Temporal Coding-Based On-Chip STDP Learning. IEEE Trans. Circuits Syst. II Express Briefs Yi Zhong, Zilin Wang, Xiaoxin Cui, Jian Cao, Yuan Wang
2023	—	`conf`	An Efficient Spiking Neural Network Accelerator with Sparse Weight. BioCAS Zilin Wang, Yi Zhong, Youming Yang, Xiaoxin Cui, Yuan Wang
2023	B	`conf`	Channel Pruning Via Attention Module And Memory Curve. ICIP Hufei Li, Jian Cao, Xiangcheng Liu, Jue Chen, Jingjie Shang, Yu Qian, Yuan Wang
2023	A*	`conf`	Efficient Non-Linear Adder for Stochastic Computing with Approximate Spatial-Temporal Sorting Network. DAC Yixuan Hu, Tengyu Zhang, Meng Li, Renjie Wei, Liangzhen Lai, Yuan Wang, Runsheng Wang, Ru Huang
2023	—	`conf`	Linear Leakage: Better Robustness for Spiking Neural Network. ICACT Jinming Che, Jian Cao, Shuo Feng, Jue Chen, Yuan Wang
2023	A	`conf`	Monad: Towards Cost-Effective Specialization for Chiplet-Based Spatial Accelerators. ICCAD Xiaochen Hao, Zijian Ding, Jieming Yin, Yuan Wang, Yun Liang
2023	J	`jnl`	Multi-Competitive Virus Spread over a Time-Varying Networked SIS Model with an Infrastructure Network. CoRR Sebin Gracy, Yuan Wang, Philip E. Pare, César A. Uribe
2023	—	`conf`	Razor SNN: Efficient Spiking Neural Network with Temporal Embeddings. ICANN (5) Yuan Zhang, Jian Cao, Jue Chen, Wenyu Sun, Yuan Wang
2023	J	`jnl`	Razor SNN: Efficient Spiking Neural Network with Temporal Embeddings. CoRR Yuan Zhang, Jian Cao, Ling Zhang, Jue Chen, Wenyu Sun, Yuan Wang
2023	J	`jnl`	Real-Time Target Tracking System With Spiking Neural Networks Implemented on Neuromorphic Chips. IEEE Trans. Circuits Syst. II Express Briefs Kefei Liu, Xiaoxin Cui, Xiang Ji, Yisong Kuang, Chenglong Zou, Yi Zhong, Kanglin Xiao, Yuan Wang
2023	J	`jnl`	Toward a Lossless Conversion for Spiking Neural Networks with Negative-Spike Dynamics. Adv. Intell. Syst. Chenglong Zou, Xiaoxin Cui, Guang Chen, Yuanyuan Jiang, Yuan Wang
2023	—	`conf`	Unsupervised Learning of Spike-Timing-Dependent Plasticity Based on a Neuromorphic Implementation. AICAS Yi Zhong, Zilin Wang, Xiaoxin Cui, Jian Cao, Yuan Wang
2022	J	`jnl`	A 128 Kb DAC-less 6T SRAM computing-in-memory macro with prioritized subranging ADC for AI edge applications. Microelectron. J. Kanglin Xiao, Xiaoxin Cui, Xin Qiao, Xin'an Wang, Yuan Wang
2022	C	`conf`	A 28nm 64Kb SRAM based Inference-Training Tri-Mode Computing-in-Memory Macro. ISCAS Nanbing Pan, Xiaoxin Cui, Xin Qiao, Kanglin Xiao, Qingyu Guo, Yuan Wang
2022	C	`conf`	A 4-bit Integer-Only Neural Network Quantization Method Based on Shift Batch Normalization. ISCAS Qingyu Guo, Xiaoxin Cui, Jian Zhang, Aifei Zhang, Xinjie Guo, Yuan Wang
2022	J	`jnl`	A 65 nm 73 kb SRAM-Based Computing-In-Memory Macro With Dynamic-Sparsity Controlling. IEEE Trans. Circuits Syst. II Express Briefs Xin Qiao, Jiahao Song, Xiyuan Tang, Haoyang Luo, Nanbing Pan, Xiaoxin Cui, Runsheng Wang, Yuan Wang
2022	C	`conf`	A Computing-in-Memory SRAM Macro Based on Fully-Capacitive-Coupling With Hierarchical Capacity Attenuator for 4-b MAC Operation. ISCAS Kanglin Xiao, Xiaoxin Cui, Xin Qiao, Nanbing Pan, Xin'an Wang, Yuan Wang
2022	—	`conf`	A Full-Neuron Memory Model Designed for Neuromorphic Systems. AICAS Kefei Liu, Xiaoxin Cui, Chenglong Zou, Yisong Kuang, Yi Zhong, Kanglin Xiao, Yuan Wang
2022	—	`conf`	A Hybrid Spiking Recurrent Neural Network on Hardware for Efficient Emotion Recognition. AICAS Chenglong Zou, Xiaoxin Cui, Yisong Kuang, Yuan Wang, Xinan Wang
2022	—	`conf`	A Mapping Model of SNNs to Neuromorphic Hardware. AICAS Xiuping Cui, Xiaochen Hao, Yun Liang, Guangyu Sun, Xiaoxin Cui, Yuan Wang, Ru Huang
2022	C	`conf`	A Novel Low-Leakage ESD Power Clamp Circuit with Adjustable Transient Response Time. ISCAS Zilong Shen, Yize Wang, Xing Zhang, Yuan Wang
2022	—	`conf`	A Reconfigurable SRAM Computing-in-Memory Macro Supporting Ping-Pong Operation and CIM pipeline for Multi-mode MAC operations. ICTA Kanglin Xiao, Xiaoxin Cui, Xin Qiao, Xin'an Wang, Yuan Wang
2022	—	`conf`	A Sample-Based Algorithm for Approximately Testing r-Robustness of a Digraph. CDC Yuhao Yi, Yuan Wang, Xingkang He, Stacy Patterson, Karl Henrik Johansson
2022	J	`jnl`	A Sample-Based Algorithm for Approximately Testing r-Robustness of a Digraph. CoRR Yuhao Yi, Yuan Wang, Xingkang He, Stacy Patterson, Karl Henrik Johansson
2022	J	`jnl`	A Scalable Model for Snapback Characteristics of Circuit-Level ESD Simulation. IEEE Trans. Circuits Syst. II Express Briefs Zilong Shen, Yize Wang, Yunhao Li, Xing Zhang, Yuan Wang
2022	J	`jnl`	A State Feedback Controller for Mitigation of Continuous-Time Networked SIS Epidemics. CoRR Yuan Wang, Sebin Gracy, César A. Uribe, Hideaki Ishii, Karl Henrik Johansson
2022	C	`conf`	An Event-driven Spiking Neural Network Accelerator with On-chip Sparse Weight. ISCAS Yisong Kuang, Xiaoxin Cui, Chenglong Zou, Yi Zhong, Zhenhui Dai, Zilin Wang, Kefei Liu, Dunshan Yu, Yuan Wang
2022	—	`conf`	An Once-for-All Budgeted Pruning Framework for ConvNets Considering Input Resolution. CVPR Workshops Wenyu Sun, Jian Cao, Pengtao Xu, Xiangcheng Liu, Yuan Zhang, Yuan Wang
2022	—	`conf`	Boosting Dense Long-Tailed Object Detection from Data-Centric View. ACCV (3) Weichen Xu, Jian Cao, Tianhao Fu, Hongyi Yao, Yuan Wang
2022	J	`jnl`	ESSA: Design of a Programmable Efficient Sparse Spiking Neural Network Accelerator. IEEE Trans. Very Large Scale Integr. Syst. Yisong Kuang, Xiaoxin Cui, Zilin Wang, Chenglong Zou, Yi Zhong, Kefei Liu, Zhenhui Dai, Dunshan Yu, Yuan Wang, Ru Huang
2022	J	`jnl`	Modular building blocks for mapping spiking neural networks onto a programmable neuromorphic processor. Microelectron. J. Chenglong Zou, Xiaoxin Cui, Guang Chen, Shuo Feng, Kefei Liu, Xinan Wang, Yuan Wang
2021	—	`conf`	A 16Kb Transpose 6T SRAM In-Memory-Computing Macro based on Robust Charge-Domain Computing. A-SSCC Jiahao Song, Yuan Wang, Xiyuan Tang, Runsheng Wang, Ru Huang
2021	C	`conf`	A 28-nm 0.34-pJ/SOP Spike-Based Neuromorphic Processor for Efficient Artificial Neural Network Implementations. ISCAS Yisong Kuang, Xiaoxin Cui, Yi Zhong, Kefei Liu, Chenglong Zou, Zhenhui Dai, Dunshan Yu, Yuan Wang, Ru Huang
2021	J	`jnl`	A 64K-Neuron 64M-1b-Synapse 2.64pJ/SOP Neuromorphic Chip With All Memory on Chip for Spike-Based Models in 65nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs Yisong Kuang, Xiaoxin Cui, Yi Zhong, Kefei Liu, Chenglong Zou, Zhenhui Dai, Yuan Wang, Dunshan Yu, Ru Huang
2021	C	`conf`	A Spike-Event-Based Neuromorphic Processor with Enhanced On-Chip STDP Learning in 28nm CMOS. ISCAS Yi Zhong, Xiaoxin Cui, Yisong Kuang, Kefei Liu, Yuan Wang, Ru Huang
2021	J	`jnl`	Integer-Only Neural Network Quantization Scheme Based on Shift-Batch-Normalization. CoRR Qingyu Guo, Yuan Wang, Xiaoxin Cui
2021	J	`jnl`	Suppressing the endemic equilibrium in SIS epidemics: A state dependent approach. CoRR Yuan Wang, Sebin Gracy, Hideaki Ishii, Karl Henrik Johansson
2021	J	`jnl`	TD-SRAM: Time-Domain-Based In-Memory Computing Macro for Binary Neural Networks. IEEE Trans. Circuits Syst. I Regul. Pap. Jiahao Song, Yuan Wang, Minguang Guo, Xiang Ji, Kaili Cheng, Yixuan Hu, Xiyuan Tang, Runsheng Wang, Ru Huang
2020	J	`jnl`	A New Behavioral Model of Gate-Grounded NMOS for Simulating Snapback Characteristics. IEEE Access Yize Wang, Guangyi Lu, Yuan Wang
2020	C	`conf`	Accurate and Energy-Efficient Implementation of Non-Linear Adder in Parallel Stochastic Computing using Sorting Network. ISCAS Yawen Zhang, Runsheng Wang, Yixuan Hu, Weikang Qian, Yanzhi Wang, Yuan Wang, Ru Huang
2020	J	`jnl`	Parallel Hybrid Stochastic-Binary-Based Neural Network Accelerators. IEEE Trans. Circuits Syst. Yawen Zhang, Runsheng Wang, Xinyue Zhang, Yuan Wang, Ru Huang
2020	A	`conf`	When Sorting Network Meets Parallel Bitstreams: A Fault-Tolerant Parallel Ternary Neural Network Accelerator based on Stochastic Computing. DATE Yawen Zhang, Sheng Lin, Runsheng Wang, Yanzhi Wang, Yuan Wang, Weikang Qian, Ru Huang
2019	J	`jnl`	A Parallel Bitstream Generator for Stochastic Computing. CoRR Yawen Zhang, Runsheng Wang, Xinyue Zhang, Zherui Zhang, Jiahao Song, Zuodong Zhang, Yuan Wang, Ru Huang
2019	—	`conf`	A Sparse Event-Driven Unsupervised Learning Network with Adaptive Exponential Integrate-and-Fire Model. ICICDT Zhao Zhao, Yuan Wang, Cheng Li, Xiaoxin Cui, Ru Huang
2019	—	`conf`	A Survey of Computation-Driven Data Encoding. SiPS Weikang Qian, Runsheng Wang, Yuan Wang, Marc D. Riedel, Ru Huang
2019	—	`conf`	An Energy-Efficient Computing-in-Memory Neuromorphic System with On-Chip Training. BioCAS Zhao Zhao, Yuan Wang, Xinyue Zhang, Xiaoxin Cui, Ru Huang
2019	—	`conf`	An Energy-Efficient Mixed-Signal Parallel Multiply-Accumulate (MAC) Engine Based on Stochastic Computing. ASICON Xinyue Zhang, Jiahao Song, Yuan Wang, Yawen Zhang, Zuodong Zhang, Runsheng Wang, Ru Huang
2019	J	`jnl`	Improved turn-on behavior in a diode-triggered silicon-controlled rectifier for high-speed electrostatic discharge protection. Sci. China Inf. Sci. Lizhong Zhang, Yuan Wang, Yize Wang, Xing Zhang, Yandong He
2019	—	`conf`	Memory System Designed for Multiply-Accumulate (MAC) Engine Based on Stochastic Computing. ICICDT Xinyue Zhang, Yuan Wang, Yawen Zhang, Jiahao Song, Zuodong Zhang, Kaili Cheng, Runsheng Wang, Ru Huang
2019	—	`conf`	Parallel Convolutional Neural Network (CNN) Accelerators Based on Stochastic Computing. SiPS Yawen Zhang, Xinyue Zhang, Jiahao Song, Yuan Wang, Ru Huang, Runsheng Wang
2018	J	`jnl`	A 1-Gbps reference-less burst-mode CDR with embedded TDC in a 65-nm CMOS process. Int. J. Circuit Theory Appl. Yuan Wang, Mengyin Jiang, Baoguang Liu, Song Jia, Xing Zhang
2018	—	`conf`	A Compact and Accelerated Spike-based Neuromorphic VLSI Chip for Pattern Recognition. BioCAS Cheng Li, Yuan Wang, Jin Zhang, Xiaoxin Cui, Ru Huang
2018	C	`conf`	A Multi-Mode Silicon Neuron Circuit With High Robustness Against PVT Variation. ISCAS Lu Zhang, Jin Zhang, Yuan Wang, Xing Zhang, Ru Huang
2018	C	`conf`	Investigation on the Gate Bias Voltage of BigFET in Power-rail ESD Clamp Circuit for Enhanced Transient Noise Immunity. ISCAS Guangyi Lu, Yuan Wang, Lizhong Zhang, Yize Wang, Ru Huang, Xing Zhang
2017	J	`jnl`	A novel TLP-based method to deliver IEC 61000-4-2 ESD stress. IEICE Electron. Express Yize Wang, Yuan Wang, Guangyi Lu, Jian Cao, Xing Zhang
2017	—	`conf`	A novel equivalent circuit model of the surge wave generator. ASICON Yukuai Chen, Jian Cao, Zhang Qihui, Yuan Wang, Xing Zhang
2017	C	`conf`	A reliable true random number generator based on novel chaotic ring oscillator. ISCAS Yunfan Yang, Song Jia, Yuan Wang, Shaonan Zhang, Chao Liu
2017	C	`conf`	Compact digital-controlled neuromorphic circuit with low power consumption. ISCAS Jin Zhang, Yuan Wang, Xing Zhang, Ru Huang
2017	J	`jnl`	Delay-locked loop based clock and data recovery with wide operating range and low jitter in a 65-nm CMOS process. Int. J. Circuit Theory Appl. Yuan Wang, Yuequan Liu, Song Jia, Xing Zhang
2017	J	`jnl`	Power-Rail ESD Clamp Circuit with Parasitic-BJT and Channel Parallel Shunt Paths to Achieve Enhanced Robustness. IEICE Trans. Electron. Yuan Wang, Guangyi Lu, Yize Wang, Xing Zhang
2017	C	`conf`	Power-rail ESD clamp circuit with hybrid-detection enhanced triggering in a 65-nm, 1.2-V CMOS process. ISCAS Guangyi Lu, Yuan Wang, Yize Wang, Xing Zhang
2016	J	`jnl`	A 4.8-6.8 GHz low phase noise LC VCO in 0.13-µm CMOS technology. Int. J. Circuit Theory Appl. Yuan Wang, Shanliang Gan, Song Jia, Xing Zhang
2016	J	`jnl`	A Short-Time Three-Phase Single-Rail Precharge Logic against Differential Power Analysis. IEICE Trans. Electron. Wenyi Tang, Song Jia, Yuan Wang
2016	J	`jnl`	A compact SCR model using advanced BJT models and standard SPICE elements. Sci. China Inf. Sci. Jian Cao, Jingya Xu, Yuan Wang, Guangyi Lu, Xing Zhang
2016	J	`jnl`	A novel SPICE circuit model of electrostatic discharge (ESD) generator. IEICE Electron. Express Jian Cao, Yize Wang, Yuan Wang, Guangyi Lu, Xing Zhang
2016	C	`conf`	A novel low-leakage power-rail ESD clamp circuit with adjustable triggering voltage and superior false-triggering immunity for nanoscale applications. ISCAS Guangyi Lu, Yuan Wang, Jian Cao, Song Jia, Xing Zhang
2016	C	`conf`	A novel low-power and high-speed dual-modulus prescaler based on extended true single-phase clock logic. ISCAS Song Jia, Ziyi Wang, Zijin Li, Yuan Wang
2016	J	`jnl`	A true single-phase clock dual-modulus prescaler with enhanced robustness against leakage currents. Int. J. Circuit Theory Appl. Song Jia, Ziyi Wang, Shilin Yan, Yuan Wang
2016	J	`jnl`	Area-efficient transient power-rail electrostatic discharge clamp circuit with mis-triggering immunity in a 65-nm CMOS process. Sci. China Inf. Sci. Yuan Wang, Guangyi Lu, Haibing Guo, Jian Cao, Song Jia, Xing Zhang
2016	C	`conf`	Delay-locked loop based frequency quadrupler with wide operating range and fast locking characteristics. ISCAS Yuan Wang, Yuequan Liu, Mengyin Jiang, Song Jia, Xing Zhang
2016	J	`jnl`	Design of a novel static-triggered power-rail ESD clamp circuit in a 65-nm CMOS process. Sci. China Inf. Sci. Guangyi Lu, Yuan Wang, Lizhong Zhang, Jian Cao, Xing Zhang
2016	J	`jnl`	Optimization on Layout Strategy of Gate-Grounded NMOS for On-Chip ESD Protection in a 65-nm CMOS Process. IEICE Trans. Electron. Guangyi Lu, Yuan Wang, Xing Zhang
2015	C	`conf`	180.5Mbps-8Gbps DLL-based clock and data recovery circuit with low jitter performance. ISCAS Yuequan Liu, Yuan Wang, Song Jia, Xing Zhang
2015	—	`conf`	A 10b, 0.7ps resolution coarse-fine time-to-digital converter in 65nm CMOS using a time residue amplifier. ASICON Jiyu Chen, Song Jia, Yuan Wang
2015	—	`conf`	A low power and high speed CAM design using pulsed voltage for search-line. ASICON Song Jia, Weiting Li, Wenyi Tang, Yuan Wang
2015	—	`conf`	A low-leakage power clamp ESD protection circuit with prolonged ESD discharge time and compact detection network. ASICON Jian Cao, Zhenxu Ye, Yuan Wang, Guangyi Lu, Xing Zhang
2015	C	`conf`	A low-power high-speed 32/33 prescaler based on novel divide-by-4/5 unit with improved true single-phase clock logic. ISCAS Song Jia, Shilin Yan, Yuan Wang, Ganggang Zhang
2015	—	`conf`	A reference-less all-digital burst-mode CDR with embedded TDC. ASICON Mengyin Jiang, Yuan Wang, Baoguang Liu, Yuequan Liu, Song Jia, Xing Zhang
2015	—	`conf`	Design on multi-bit adder using sense amplifier-based pass transistor logic for near-threshold voltage operation. ASICON Fangyuan Dang, Yuan Wang, Yuequan Liu, Song Jia, Xing Zhang
2015	—	`conf`	Four-bit transient-to-digital converter with a single RC-based detection circuit for system-level ESD protection. ASICON Nan Han, Yuan Wang, Guangyi Lu, Jian Cao, Xing Zhang
2015	J	`jnl`	Investigation on the layout strategy of ggNMOS ESD protection devices for uniform conduction behavior and optimal width scaling. Sci. China Inf. Sci. Guangyi Lu, Yuan Wang, Lizhong Zhang, Jian Cao, Song Jia, Xing Zhang
2015	J	`jnl`	Novel DEM Technique for Current-Steering DAC in 65-nm CMOS Technology. IEICE Trans. Electron. Yuan Wang, Wei Su, Guangliang Guo, Xing Zhang
2014	J	`jnl`	Novel silicon-controlled rectifier (SCR) for digital and high-voltage ESD power supply clamp. Sci. China Inf. Sci. Peng Zhang, Yuan Wang, Xing Zhang, Xiaohua Ma, Yue Hao
2013	J	`jnl`	A Current-Mirror Winner-Take-All Sense Amplifier for Low Voltage SRAMs. IEICE Trans. Electron. Song Jia, Heqing Xu, Fengfeng Wu, Yuan Wang
2013	—	`conf`	A current mode sense amplifier with self-compensation circuit for SRAM application. ASICON Heqing Xu, Song Jia, Jiyu Chen, Yuan Wang, Gang Du
2013	—	`conf`	A novel dynamic element match technique in current-steering DAC. ASICON Baoguang Liu, Yuan Wang, Guangliang Guo, Song Jia, Xing Zhang
2013	J	`jnl`	Data Convertors Design for Optimization of the DDPL Family. IEICE Trans. Electron. Song Jia, Li Liu, Xiayu Li, Fengfeng Wu, Yuan Wang, Ganggang Zhang
2013	J	`jnl`	Improved CRC Calculation Strategies for 64-bit Serial RapidIO. IEICE Trans. Electron. Fengfeng Wu, Song Jia, Qinglong Meng, Shigong Lv, Yuan Wang, Dacheng Zhang
2013	—	`conf`	Novel gate-voltage-bias techniques for gate-coupled MOS (GCMOS) ESD protection circuits. ASICON Guangyi Lu, Yuan Wang, Jian Cao, Song Jia, Ganggang Zhang, Xing Zhang
2013	J	`jnl`	Thermo data-weighted average dynamic element matching (DEM) encoder for current-steering DACs. IEICE Electron. Express Yuan Wang, Baoguang Liu, Wei Su, Junlei Zhao, Xing Zhang
2012	J	`jnl`	A Pulse-Generator-Free Hybrid Latch Based Flip-Flop (PHLFF). IEICE Trans. Electron. Xiayu Li, Song Jia, Limin Liu, Yuan Wang
2012	J	`jnl`	Design of novel, semi-transparent flip-flops (STFF) for high speed and low power application. Sci. China Inf. Sci. Xiayu Li, Song Jia, Limin Liu, Yuan Wang, Ganggang Zhang
2011	—	`conf`	A novel multi-finger layout strategy for GGnMOS ESD protection device. ASICON Peng Zhang, Yuan Wang, Song Jia, Xing Zhang
2011	J	`jnl`	Novel single-loop multi-bit sigma-delta modulator using OTA sharing technique without DEM. IEICE Electron. Express Hongyi Li, Yuan Wang, Song Jia, Xing Zhang
2010	J	`jnl`	Low swing drivers based on charge redistribution. Sci. China Inf. Sci. Fengfeng Wu, Song Jia, Yuan Wang, Ganggang Zhang
2007	C	`conf`	Design of High-Performance Voltage Regulators Based on Frequency-Dependent Feedback Factor. ISCAS Liangguo Shen, Zushu Yan, Xing Zhang, Yuanfu Zhao, Yuan Wang