Yuan Pu

26 papers A* 7A 3Journal 12Unranked 4
YearRankTypeTitle / Venue / Authors
2026 — conf
Invited: Infusing EDA Knowledge into LLM Systems: An Information-Source Perspective.
ISPD
Yuhan Qin, Yuan Pu, Tairu Qiu, Zhuolun He, Bei Yu
2026 J jnl
RegPlace: Regularity-Aware Placement for Full-System DNN Accelerator Designs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Jiaxi Jiang, Yuan Pu, Mingjun Li, Yuxuan Zhao, Peiyu Liao, Zuodong Zhang, Yibo Lin, Bei Yu
2025 A* conf
Circuit Representation Learning with Masked Gate Modeling and Verilog-AIG Alignment.
ICLR
Haoyuan Wu, Haisheng Zheng, Yuan Pu, Bei Yu
2025 J jnl
Circuit Representation Learning with Masked Gate Modeling and Verilog-AIG Alignment.
CoRR
Haoyuan Wu, Haisheng Zheng, Yuan Pu, Bei Yu
2025 J jnl
Customized Retrieval Augmented Generation and Benchmarking for EDA Tool Documentation QA.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Yuan Pu, Zhuolun He, Yuqi Jiang, Tairu Qiu, Haoyuan Wu, Qi Sun, Cheng Zhuo, Bei Yu
2025 A* conf
DSPlacer: DSP Placement for FPGA-based CNN Accelerator.
DAC
Baohui Xie, Xinrui Zhu, Zhiyuan Lu, Yuan Pu, Tongkai Wu, Xiaofeng Zou, Bei Yu, Tinghuan Chen
2025 J jnl
EasyMRC: Efficient Mask Rule Checking via Representative Edge Sampling.
ACM Trans. Design Autom. Electr. Syst.
Jiahao Xu, Zhuolun He, Shuo Yin, Yuan Pu, Wenjian Yu, Bei Yu
2025 A conf
GPU Acceleration for Versatile Buffer Insertion.
ICCAD
Yuan Pu, Yuhao Ji, Siying Yu, Zuodong Zhang, Zizheng Guo, Zhuolun He, Yibo Lin, David Z. Pan, Bei Yu
2025 — conf
HeLO: A Heterogeneous Logic Optimization Framework by Hierarchical Clustering and Graph Learning.
ISPD
Yuan Pu, Fangzhou Liu, Zhuolun He, Keren Zhu, Rongliang Fu, Ziyi Wang, Tsung-Yi Ho, Bei Yu
2025 J jnl
IncreMacro: Incremental Macro Placement Refinement.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Yuan Pu, Tinghuan Chen, Zhuolun He, Jiajun Qin, Chen Bai, Haisheng Zheng, Yibo Lin, Bei Yu
2025 J jnl
Large Language Models for EDA: From Assistants to Agents.
Found. Trends Electron. Des. Autom.
Zhuolun He, Yuan Pu, Haoyuan Wu, Yuhan Qin, Tairu Qiu, Bei Yu
2025 J jnl
Large Language Models for EDA: Future or Mirage?
ACM Trans. Design Autom. Electr. Syst.
Zhuolun He, Yuan Pu, Haoyuan Wu, Tairu Qiu, Bei Yu
2025 A* conf
Late Breaking Results: Hybrid Logic Optimization with Predictive Self-Supervision.
DAC
Rongliang Fu, Ran Zhang, Ziyang Zheng, Zhengyuan Shi, Yuan Pu, JunYing Huang, Qiang Xu, Tsung-Yi Ho
2025 A conf
MM-GRADE: A Multi-Modal EDA Tool Documentation QA Framework Leveraging Retrieval Augmented Generation.
ICCAD
Yuan Pu, Zhuolun He, Shutong Lin, Jiajun Qin, Xinyun Zhang, Hairuo Han, Haisheng Zheng, Yuqi Jiang, Cheng Zhuo, Qi Sun, David Z. Pan, Bei Yu
2025 J jnl
PRO-TIME: Prerouting Optimization-Aware Timing Prediction via Multimodal Learning.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Ziyi Wang, Siting Liu, Yuan Pu, Song Chen, Tsung-Yi Ho, Bei Yu
2025 J jnl
ParSGCN: Bridging the Gap Between Emulation Partitioning and Scheduling.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Ziyi Wang, Wenqian Zhao, Yuan Pu, Lei Chen, Wilson W. K. Thong, Weihua Sheng, Tsung-Yi Ho, Bei Yu
2025 J jnl
UniMoCo: Unified Modality Completion for Robust Multi-Modal Embeddings.
CoRR
Jiajun Qin, Yuan Pu, Zhuolun He, Seunggeun Kim, David Z. Pan, Bei Yu
2024 A conf
Customized Retrieval Augmented Generation and Benchmarking for EDA Tool Documentation QA.
ICCAD
Yuan Pu, Zhuolun He, Tairu Qiu, Haoyuan Wu, Bei Yu
2024 J jnl
Customized Retrieval Augmented Generation and Benchmarking for EDA Tool Documentation QA.
CoRR
Yuan Pu, Zhuolun He, Tairu Qiu, Haoyuan Wu, Bei Yu
2024 — conf
IncreMacro: Incremental Macro Placement Refinement.
ISPD
Yuan Pu, Tinghuan Chen, Zhuolun He, Chen Bai, Haisheng Zheng, Yibo Lin, Bei Yu
2024 A* conf
Lesyn: Placement-aware Logic Resynthesis for Non-Integer Multiple-Cell-Height Designs.
DAC
Yuan Pu, Fangzhou Liu, Yu Zhang, Zhuolun He, Yibo Lin, Kai-Yuan Chao, Bei Yu
2024 — conf
Multi-Electrostatics Based Placement for Non-Integer Multiple-Height Cells.
ISPD
Yu Zhang, Yuan Pu, Fangzhou Liu, Peiyu Liao, Kai-Yuan Chao, Keren Zhu, Yibo Lin, Bei Yu
2024 A* conf
NeuroSelect: Learning to Select Clauses in SAT Solvers.
DAC
Hongduo Liu, Peng Xu, Yuan Pu, Lihao Yin, Hui-Ling Zhen, Mingxuan Yuan, Tsung-Yi Ho, Bei Yu
2023 J jnl
FastGR: Global Routing on CPU-GPU With Heterogeneous Task Graph Scheduler.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Siting Liu, Yuan Pu, Peiyu Liao, Hongzhong Wu, Rui Zhang, Zhitang Chen, Wenlong Lv, Yibo Lin, Bei Yu
2023 A* conf
FastGR: Global Routing on CPU-GPU with Heterogeneous Task Graph Scheduler (Extended Abstract).
IJCAI
Siting Liu, Yuan Pu, Peiyu Liao, Hongzhong Wu, Rui Zhang, Zhitang Chen, Wenlong Lv, Yibo Lin, Bei Yu
2023 A* conf
Restructure-Tolerant Timing Prediction via Multimodal Fusion.
DAC
Ziyi Wang, Siting Liu, Yuan Pu, Song Chen, Tsung-Yi Ho, Bei Yu