Yuan-Hua Chu - RankMe

36 papers A* 1C 6Misc 1Journal 10Unranked 18

Year	Rank	Type	Title / Venue / Authors
2019	J	`jnl`	A Sustainable Soil Energy Harvesting System With Wide-Range Power-Tracking Architecture. IEEE Internet Things J. I-Che Ou, Jia-Ping Yang, Chia-Hung Liu, Kai-Jie Huang, Kun-Ju Tsai, Yu Lee, Yuan-Hua Chu, Yu-Te Liao
2018	—	`conf`	A 99.2% Tracking Accuracy Single-Inductor Quadruple-Input-Quadruple-Output Buck-Boost Converter Topology with Periodical Interval Perturbation and Observation MPPT. A-SSCC Chao-Jen Huang, Yao-Sheng Ma, Wen-Hau Yang, Yen-Ting Lin, Chun-Chieh Kuo, Ke-Horng Chen, Hsiao-Jung Liu, Pei-Shan Yu, Fang-Chih Chu, Ching-Ju Lin, Hong-Wen Huang, Kuo-Chih Hung, Yuan-Hua Chu, Ying-Hsi Lin, Suhwan Kim, Krishnan Ravichandran
2018	—	`conf`	A Wide-Range Capacitive DC-DC Converter with 2D-MPPT for Soil/Solar Energy Extraction. A-SSCC I-Che Ou, Jia-Ping Yang, Chia-Hung Liu, Kai-Jie Huang, Kun-Ju Tsai, Yu Lee, Yuan-Hua Chu, Yu-Te Liao
2018	—	`conf`	MORAS: An energy-scalable system using adaptive voltage scaling. VLSI-DAT Kuo-Chiang Chang, Shien-Chun Luo, Ching-Ji Huang, Jia-Hung Peng, Yuan-Hua Chu
2016	J	`jnl`	A Varactor-Based All-Digital Multi-Phase PLL with Random-Sampling Spur Suppression Techniques. IEICE Trans. Electron. Chia-Wen Chang, Kai-Yu Lo, Hossameldin A. Ibrahim, Ming-Chiuan Su, Yuan-Hua Chu, Shyh-Jye Jou
2016	A*	`conf`	Invited - Wireless sensor nodes for environmental monitoring in internet of things. DAC Ting-Chou Lu, Li-Ren Huang, Yu Lee, Kun-Ju Tsai, Yu-Te Liao, Nai-Chen Cheng, Yuan-Hua Chu, Yi-Hsing Tsai, Fang-Chu Chen, Tzi-cker Chiueh
2015	J	`jnl`	A Near-Threshold Cell-Based All-Digital PLL with Hierarchical Band-Selection G-DCO for Fast Lock-In and Low-Power Applications. IEICE Trans. Electron. Chia-Wen Chang, Yuan-Hua Chu, Shyh-Jye Jou
2015	—	`conf`	All digitally controlled linear voltage regulator with PMOS strength self-calibration for ripple reduction. VLSI-DAT Yi-Ping Kuo, Po-Tsang Huang, Chung-Shiang Wu, Yu-Jie Liang, Ching-Te Chuang, Yuan-Hua Chu, Wei Hwang
2015	C	`conf`	An all-digital power management unit with 90% power efficiency and ns-order voltage transition time for DVS operation in low power sensing SoC applications. ISCAS Chung-Shiang Wu, Kai-Chun Lin, Yi-Ping Kuo, Po-Hung Chen, Yuan-Hua Chu, Wei Hwang
2014	J	`jnl`	40 nm Bit-Interleaving 12T Subthreshold SRAM With Data-Aware Write-Assist. IEEE Trans. Circuits Syst. I Regul. Pap. Yi-Wei Chiu, Yu-Hao Hu, Ming-Hsien Tu, Jun-Kai Zhao, Yuan-Hua Chu, Shyh-Jye Jou, Ching-Te Chuang
2014	—	`conf`	A 3 MHz-to-1.8 GHz 94 μW-to-9.5 mW 0.0153-mm A-SSCC Chun-Yuan Cheng, Jinn-Shyan Wang, Pei-Yuan Chou, Shiou-Ching Chen, Chi-Tien Sun, Yuan-Hua Chu, Tzu-Yi Yang
2014	J	`jnl`	A Wide-Range Level Shifter Using a Modified Wilson Current Mirror Hybrid Buffer. IEEE Trans. Circuits Syst. I Regul. Pap. Shien-Chun Luo, Ching-Ji Huang, Yuan-Hua Chu
2014	C	`conf`	A radio-controlled receiver for clocks/watches and alarm applications. ISCAS Jen-Chieh Liu, Huan-Ke Chiu, Jia-Hung Peng, Yuan-Hua Chu, Hong-Yi Huang
2014	C	`conf`	An ultra-low voltage hearing aid chip using variable-latency design technique. ISCAS Kuo-Chiang Chang, Shien-Chun Luo, Ching-Ji Huang, Chih-Wei Liu, Yuan-Hua Chu, Shyh-Jye Jou
2014	—	`conf`	Low power fixed-latency DSP accelerator with autonomous minimum energy tracking (AMET). Hot Chips Symposium Chung-Hsun Huang, Wei-Jen Chen, Keng-Jui Chang, Yi-Hsuan Ting, Keng-Chang Hsu, Yu-Fu Pan, Chao-Chun Chen, Yuan-Hua Chu, Tay-Jyi Lin, Jinn-Shyan Wang
2014	—	`conf`	PVT-aware digital controlled voltage regulator design for ultra-low-power (ULP) DVFS systems. SoCC Pei-Chen Wu, Yi-Ping Kuo, Chung-Shiang Wu, Ching-Te Chuang, Yuan-Hua Chu, Wei Hwang
2014	J	`jnl`	Separate Clock Network Voltage for Correcting Random Errors in ULV Clocked Storage Cells. IEEE Trans. Circuits Syst. II Express Briefs Shien-Chun Luo, Kuo-Chiang Chang, Ming-Pin Chen, Ching-Ji Huang, Yi-Fang Chiu, Po-Hsun Chen, Liang-Chia Cheng, Chih-Wei Liu, Yuan-Hua Chu
2013	—	`conf`	A 0.48V 0.57nJ/pixel video-recording SoC in 65nm CMOS. ISSCC Tay-Jyi Lin, Cheng-An Chien, Pei-Yao Chang, Ching-Wen Chen, Po-Hao Wang, Ting-Yu Shyu, Chien-Yung Chou, Shien-Chun Luo, Jiun-In Guo, Tien-Fu Chen, Gene C. H. Chuang, Yuan-Hua Chu, Liang-Chia Cheng, Hong-Men Su, Chewnpu Jou, Meikei Ieong, Cheng-Wen Wu, Jinn-Shyan Wang
2013	J	`jnl`	A Sub-0.3 V Area-Efficient L-Shaped 7T SRAM With Read Bitline Swing Expansion Schemes Based on Boosted Read-Bitline, Asymmetric-V IEEE J. Solid State Circuits Meng-Fan Chang, Ming-Bin Chen, Lai-Fu Chen, Shu-Meng Yang, Yao-Jen Kuo, Jui-Jen Wu, Hsiu-Yun Su, Yuan-Hua Chu, Wen-Chin Wu, Tzu-Yi Yang, Hiroyuki Yamauchi
2013	—	`conf`	A dual-edged triggered explicit-pulsed level converting flip-flop with a wide operation range. SoCC Mei-Wei Chen, Ming-Hung Chang, Pei-Chen Wu, Yi-Ping Kuo, Chun-Lin Yang, Yuan-Hua Chu, Wei Hwang
2013	J	`jnl`	An Adaptive Pulse-Triggered Flip-Flop for a High-Speed and Voltage-Scalable Standard Cell Library. IEEE Trans. Circuits Syst. II Express Briefs Shien-Chun Luo, Ching-Ji Huang, Yuan-Hua Chu
2012	—	`conf`	A 260mV L-shaped 7T SRAM with bit-line (BL) Swing expansion schemes based on boosted BL, asymmetric-VTH read-port, and offset cell VDD biasing techniques. VLSIC Ming-Pin Chen, Lai-Fu Chen, Meng-Fan Chang, Shu-Meng Yang, Yao-Jen Kuo, Jui-Jen Wu, Mon-Shu Ho, Hsiu-Yun Su, Yuan-Hua Chu, Wen-Chin Wu, Tzu-Yi Yang, Hiroyuki Yamauchi
2012	—	`conf`	An energy-efficient level converter with high thermal variation immunity for sub-threshold to super-threshold operation. SoCC Mei-Wei Chen, Ming-Hung Chang, Yuan-Hua Chu, Wei Hwang
2012	—	`conf`	An ultra-low power interface CMOS IC design for biosensor applications. MWSCAS Weibo Hu, Yen-Ting Liu, Vighnesh Das, Cliff Schecht, Tam Q. Nguyen, Donald Y. C. Lie, Tzu-Chao Yan, Chien-Nan Kuo, Stanley Wu, Yuan-Hua Chu, Tzu-Yi Yang
2012	—	`conf`	Energy-efficient RISC design with on-demand circuit-level timing speculation. ASP-DAC Tay-Jyi Lin, Yu-Ting Kuo, Yu-Jung Tsai, Ting-Yu Shyu, Yuan-Hua Chu
2012	—	`conf`	Thermoelectric energy harvesting with 1mV low input voltage and 390nA quiescent current for 99.6% maximum power point tracking. ESSCIRC Chao-Jen Huang, Wei-Chung Chen, Chia-Lung Ni, Ke-Horng Chen, Chien-Chun Lu, Yuan-Hua Chu, Ming-Ching Kuo
2011	—	`conf`	0.5 VDD digitally controlled oscillators design with compensation techniques for PVT variations. ASICON Chia-Wen Chang, Shyh-Jye Jou, Yuan-Hua Chu
2011	J	`jnl`	A Large Sigma V IEEE J. Solid State Circuits Jui-Jen Wu, Yen-Hui Chen, Meng-Fan Chang, Po-Wei Chou, Chien-Yuan Chen, Hung-Jen Liao, Ming-Bin Chen, Yuan-Hua Chu, Wen-Chin Wu, Hiroyuki Yamauchi
2011	J	`jnl`	Parallel Architecture Core (PAC) - the First Multicore Application Processor SoC in Taiwan Part I: Hardware Architecture & Software Development Tools. J. Signal Process. Syst. David Chih-Wei Chang, Tay-Jyi Lin, Chung-Ju Wu, Jenq Kuen Lee, Yuan-Hua Chu, An-Yeu Wu
2010	—	`conf`	A 0.29V embedded NAND-ROM in 90nm CMOS for ultra-low-voltage applications. ISSCC Meng-Fan Chang, Shu-Meng Yang, Chih-Wei Liang, Chih-Chyuang Chiang, Pi-Feng Chiu, Ku-Feng Lin, Yuan-Hua Chu, Wen-Chin Wu, Hiroyuki Yamauchi
2010	—	`conf`	Collaborative voltage scaling with online STA and variable-latency datapath. ACM Great Lakes Symposium on VLSI Tay-Jyi Lin, Pi-Chen Hsiao, Chi-Hung Lin, Shu-Chang Kuo, Chou-Kun Lin, Yu-Ting Kuo, Chih-Wei Liu, Yuan-Hua Chu
2010	Misc	`conf`	Energy-efficient real-time scheduling of multimedia tasks on multi-core processors. SAC Yi-Hung Wei, Chuan-Yue Yang, Tei-Wei Kuo, Shih-Hao Hung, Yuan-Hua Chu
2009	C	`conf`	Full System Simulation and Verification Framework. IAS Jing-Wun Lin, Chen-Chieh Wang, Chin-Yao Chang, Chung-Ho Chen, Kuen-Jong Lee, Yuan-Hua Chu, Jen-Chieh Yeh, Ying-Chuan Hsiao
2006	C	`conf`	Design of STR level converters for SoCs using the multi-island dual-VDD design technique. ISCAS Jinn-Shyan Wang, Yu-Juey Chang, Chingwei Yeh, Yuan-Hua Chu
2005	—	`conf`	The new approach of programmable pseudo fractional-N clock generator for GHz operation with 50% duty cycle. ECCTD Wei-Bin Yang, Shu-Chang Kuo, Yuan-Hua Chu, Kuo-Hsing Cheng
1995	C	`conf`	Low-Voltage Low-Power CMOS True-Single-Phase Clocking Scheme with Locally Asynchronous Logic Circuits. ISCAS Hong-Yi Huang, Jinn-Shyan Wang, Yuan-Hua Chu, Tain-Shun Wu, Kuo-Hsing Cheng, Chung-Yu Wu