Yuan-Ho Chen

50 papers B 1C 2Journal 40Unranked 7
YearRankTypeTitle / Venue / Authors
2025 J jnl
Corrections to "A Very Large-Scale Integration (VLSI) Chip Design for Abnormal Heartbeat Detection Using a Data-Shifting Neural Network (DSNN)".
IEEE Access
Yuan-Ho Chen, Szi-Wen Chen, Hong-Wen Jian, Shinn-Yn Lin, Rou-Shayn Chen
2025 J jnl
Efficient Power- and Area-Optimized 800-Spin Ising Chip for Solving Combinatorial Optimization Problems Using Multirun Decremental Annealing.
IEEE Internet Things J.
Yuan-Ho Chen, Yu-Jie Yen, Chin-Fu Nien, Chao-Sung Lai
2025 J jnl
Low-latency and power-efficient row-based binary-weighted compensator for fixed-width Booth multiplier.
Int. J. Circuit Theory Appl.
Chung-Yi Li, Hong-Chi Hu, Yuan-Ho Chen, Shinn-Yn Lin
2024 — conf
A Simplified Simulated Annealing Algorithm and Its Implementation.
GCCE
Wu-Hsun Chu, Yuan-Ho Chen
2024 J jnl
A Very Large-Scale Integration (VLSI) Chip Design for Abnormal Heartbeat Detection Using a Data-Shifting Neural Network (DSNN).
IEEE Access
Yuan-Ho Chen, Szi-Wen Chen, Hong-Wen Jian, Shinn-Yn Lin, Rou-Shayn Chen
2024 J jnl
Design and Implementation of a VLSI-based Annealing Accelerator for Efficiently Solving Combinatorial Optimization Problems.
IEEE Trans. Circuits Syst. II Express Briefs
Yuan-Ho Chen, Che-An Chou, Chin-Fu Nien, Shinn-Yn Lin
2024 — conf
Simulated Annealing Hardware Architecture for Max-Cut Combinatorial Optimization.
GCCE
Szu-Wei Chien, Yuan-Ho Chen
2024 C conf
VLSI Implementation of Recursive CNNs with Multi-Scale Integration for Image Classification Improvement.
TENCON
Kai-Fen Chang, Yuan-Ho Chen
2023 — conf
An Automated Toolchain for QUBO-based Optimization with Quantum-inspired Annealers.
ISOCC
Yun-Ting Zhang, Chin-Fu Nien, Chia-Wei Lin, Wen-Jui Chao, Chen-Yu Liu, Lien-Po Yu, Yuan-Ho Chen
2023 — conf
Hybrid CNN-LSTM Network for ECG Classification and Its Software-Hardware Co-Design Approach.
ISOCC
Song-Nien Tang, Yuan-Ho Chen, Yu-Wei Chang, Yu-Ting Chen, Shuo-Hung Chou
2022 J jnl
A VLSI Chip for the Abnormal Heart Beat Detection Using Convolutional Neural Network.
Sensors
Yuan-Ho Chen, Szi-Wen Chen, Pei-Jung Chang, Hsin-Tung Hua, Shinn-Yn Lin, Rou-Shayn Chen
2022 — conf
High Accuracy Abnormal ECG Detection Chip Using a Simple Neural Network.
ISOCC
Kai-Fen Chang, Yuan-Ho Chen
2022 J jnl
VLSI Implementation of QRS Complex Detector Based on Wavelet Decomposition.
IEEE Access
Yuan-Ho Chen, Chih-Wen Lu, Szi-Wen Chen, Ming-Han Tsai, Shinn-Yn Lin, Rou-Shayn Chen
2022 J jnl
Very Large-Scale Integration for Premature Ventricular Contraction Detection Using a Convolutional Neural Network.
J. Circuits Syst. Comput.
Yuan-Ho Chen, Hsin-Tung Hua
2022 — conf
Very-large-scale Integration of a Dual-lead Electrocardiogram Compression Chip with Modified Huffman Encoding.
LifeTech
Yi-Fan Chen, Wei-Jhong Huang, Yi-Wei Zeng, Hsin-Tung Hua, Kai-Fen Chang, Yuan-Ho Chen
2021 J jnl
Improvement of Accuracy of Fixed-Width Booth Multipliers Using Data Scaling Technology.
IEEE Trans. Circuits Syst. II Express Briefs
Yuan-Ho Chen
2021 J jnl
Simple and hardware-efficient row-based direct-mapping estimators in fixed-width modified Booth multipliers.
Int. J. Circuit Theory Appl.
Chung-Yi Li, Yuan-Ho Chen, Lu-An Lai, Wen-Chi Ye, Jun Yang
2020 J jnl
A VLSI Implementation of Independent Component Analysis for Biomedical Signal Separation Using CORDIC Engine.
IEEE Trans. Biomed. Circuits Syst.
Yuan-Ho Chen, Szi-Wen Chen, Min-Xian Wei
2020 J jnl
A low-area high-efficiency video coding inverse transform core using resource and time sharing architecture.
EURASIP J. Adv. Signal Process.
Yuan-Ho Chen, Chieh-Yang Liu
2020 J jnl
Low-Cost Implementation of Independent Component Analysis for Biomedical Signal Separation Using Very-Large-Scale Integration.
IEEE Trans. Circuits Syst.
Yuan-Ho Chen, Shun-Ping Wang
2020 — conf
Premature Ventricular Complex Detection Chip Obtained Using Convolution Neural Network.
ICAIIC
Yu-Lun Huang, Pei-Jung Chang, Yuan-Ho Chen
2020 J jnl
VLSI Implementation of a Cost-Efficient 3-Lead Lossless ECG Compressor and Decompressor.
Circuits Syst. Signal Process.
Yuan-Ho Chen, Yun-Hua Tseng, Pao-Hsien Chu, Yen Juan, Shun-Ping Wang
2019 J jnl
Cost-effective multi-standard video transform core using time-sharing architecture.
EURASIP J. Adv. Signal Process.
Yun-Hua Tseng, Yuan-Ho Chen
2019 J jnl
Run-time calibration scheme for the implementation of a robust field-programmable gate array-based time-to-digital converter.
Int. J. Circuit Theory Appl.
Yuan-Ho Chen
2018 J jnl
Fine-Tuning Accuracy Using Conditional Probability of the Bottom Sign-Bit in Fixed-Width Modified Booth Multiplier.
Circuits Syst. Signal Process.
Yuan-Ho Chen, Chung-Yi Li, Luhua Lai
2018 J jnl
Multiple Leads With a Switch Mode for Lossless and Lossy Compression Using Very-Large-Scale Integration Technology.
IEEE Access
Yun-Hua Tseng, Yuan-Ho Chen, Chih-Wen Lu
2017 J jnl
Adaptive Integration of the Compressed Algorithm of CS and NPC for the ECG Signal Compressed Algorithm in VLSI Implementation.
Sensors
Yun-Hua Tseng, Yuan-Ho Chen, Chih-Wen Lu
2017 J jnl
High-throughput IDCT architecture for high-efficiency video coding (HEVC).
Int. J. Circuit Theory Appl.
Yuan-Ho Chen, Yi-Fan Ko
2016 J jnl
Dynamic Error-Compensated Fixed-Width Booth Multiplier Based on Conditional-Probability of Input Series.
Circuits Syst. Signal Process.
Wen-Quan He, Yuan-Ho Chen, Shyh-Jye Jou
2016 J jnl
Low-cost multi-standard simultaneous forward and inverse video transform core.
Int. J. Circuit Theory Appl.
Yun-Hua Tseng, Yuan-Ho Chen, Tze-Yang Kao, Chih-Wen Lu
2015 J jnl
An Accuracy-Adjustment Fixed-Width Booth Multiplier Based on Multilevel Conditional Probability.
IEEE Trans. Very Large Scale Integr. Syst.
Yuan-Ho Chen
2015 J jnl
Area-Efficient Fixed-Width Squarer With Dynamic Error-Compensation Circuit.
IEEE Trans. Circuits Syst. II Express Briefs
Yuan-Ho Chen
2015 J jnl
Hardware Design and Implementation of a Wavelet De-Noising Procedure for Medical Signal Preprocessing.
Sensors
Szi-Wen Chen, Yuan-Ho Chen
2015 J jnl
High-Accuracy Fixed-Width Booth Multipliers Based on Probability and Simulation.
IEEE Trans. Circuits Syst. I Regul. Pap.
Wen-Quan He, Yuan-Ho Chen, Shyh-Jye Jou
2014 J jnl
A High-Throughput and Area-Efficient Video Transform Core With a Time Division Strategy.
IEEE Trans. Very Large Scale Integr. Syst.
Yuan-Ho Chen, Ruei-Yuan Jou, Tsin-Yuan Chang, Chih-Wen Lu
2014 J jnl
A Multi-stage Fault-Tolerant Multiplier with Triple Module Redundancy (TMR) Technique.
J. Circuits Syst. Comput.
Yuan-Ho Chen, Chih-Wen Lu, Shian-Shing Shyu, Chung-Lin Lee, Ting-Chia Ou
2014 J jnl
E-leadership effectiveness in virtual teams: motivating language perspective.
Ind. Manag. Data Syst.
Kai-Tang Fan, Yuan-Ho Chen, Ching-Wen Wang, Minder Chen
2014 J jnl
Hardware-Efficient Multi-Standard Video Transform Core.
J. Circuits Syst. Comput.
Yuan-Ho Chen, Hsiao-Tzu Liu
2014 J jnl
High-Throughput Multistandard Transform Core Supporting MPEG/H.264/VC-1 Using Common Sharing Distributed Arithmetic.
IEEE Trans. Very Large Scale Integr. Syst.
Yuan-Ho Chen, Jyun-Neng Chen, Tsin-Yuan Chang, Chih-Wen Lu
2013 C conf
A high resolution FPGA-based merged delay line TDC with nonlinearity calibration.
ISCAS
Yuan-Ho Chen
2012 J jnl
A High Performance Video Transform Engine by Using Space-Time Scheduling Strategy.
IEEE Trans. Very Large Scale Integr. Syst.
Yuan-Ho Chen, Tsin-Yuan Chang
2012 J jnl
A High-Accuracy Adaptive Conditional-Probability Estimator for Fixed-Width Booth Multipliers.
IEEE Trans. Circuits Syst. I Regul. Pap.
Yuan-Ho Chen, Tsin-Yuan Chang
2012 J jnl
Integrated model of hot spring service quality perceptions under uncertainty.
Appl. Soft Comput.
Ming-Lang Tseng, Yuan-Ho Chen, Yong Geng
2012 J jnl
Period Extension and Randomness Enhancement Using High-Throughput Reseeding-Mixing PRNG.
IEEE Trans. Very Large Scale Integr. Syst.
Chung-Yi Li, Yuan-Ho Chen, Tsin-Yuan Chang, Lih-Yuan Deng, Kiwing To
2011 J jnl
A Probabilistic Estimation Bias Circuit for Fixed-Width Booth Multiplier and Its DCT Applications.
IEEE Trans. Circuits Syst. II Express Briefs
Chung-Yi Li, Yuan-Ho Chen, Tsin-Yuan Chang, Jyun-Neng Chen
2011 J jnl
Area-Effective and Power-Efficient Fixed-Width Booth Multipliers Using Generalized Probabilistic Estimation Bias.
IEEE J. Emerg. Sel. Topics Circuits Syst.
Yuan-Ho Chen, Chung-Yi Li, Tsin-Yuan Chang
2011 J jnl
High Throughput DA-Based DCT With High Accuracy Error-Compensated Adder Tree.
IEEE Trans. Very Large Scale Integr. Syst.
Yuan-Ho Chen, Tsin-Yuan Chang, Chung-Yi Li
2006 B conf
Low-Complexity Bit-Parallel Systolic Multipliers over GF(2m).
SMC
Chiou-Yng Lee, Chin-Chin Chen, Yuan-Ho Chen, Erl-Huei Lu
2006 J jnl
Power control for CDMA cellular radio systems via l
IEEE Trans. Wirel. Commun.
Bor-Sen Chen, Bore-Kuen Lee, Yuan-Ho Chen
2006 J jnl
Robust$H_infty$Power Control for CDMA Cellular Communication Systems.
IEEE Trans. Signal Process.
Bore-Kuen Lee, Yuan-Ho Chen, Bor-Sen Chen