Yuan-Chun Luo

18 papers A* 1A 1B 1C 1Journal 7Unranked 7
YearRankTypeTitle / Venue / Authors
2025 C conf
Digital Compute-in-Memory Ising Annealer with Ferroelectric Capacitor-Based nvSRAM for Combinatorial Optimization Problems.
ISCAS
Yuyao Kong, Jianwei Jia, Anni Lu, Faaiq G. Waqar, Yuan-Chun Luo, Hai Li, Ian A. Young, Shimeng Yu
2025 J jnl
NeuroSim V1.5: Improved Software Backbone for Benchmarking Compute-in-Memory Accelerators with Device and Circuit-level Non-idealities.
CoRR
James Read, Ming-Yen Lee, Wei-Hsing Huang, Yuan-Chun Luo, Anni Lu, Shimeng Yu
2024 B conf
A Cross-layer Framework for Design Space and Variation Analysis of Non-Volatile Ferroelectric Capacitor-Based Compute-in-Memory Accelerators.
ASPDAC
Yuan-Chun Luo, James Read, Anni Lu, Shimeng Yu
2024 A* conf
Digital CIM with Noisy SRAM Bit: A Compact Clustered Annealer for Large-Scale Combinatorial Optimization.
DAC
Anni Lu, Junmo Lee, Yuan-Chun Luo, Hai Li, Ian A. Young, Shimeng Yu
2024 J jnl
Endurance-Aware Compiler for 3-D Stackable FeRAM as Global Buffer in TPU-Like Architecture.
IEEE Trans. Very Large Scale Integr. Syst.
Yuan-Chun Luo, Anni Lu, Yandong Luo, Sou-Chi Chang, Uygar Avci, Shimeng Yu
2024 — conf
Engineering nvCap From FEOL to BEOL with Ferroelectric Small-signal Non-destructive Read.
IMW
Tae-Hyeon Kim, Yuan-Chun Luo, Omkar Phadke, James Read, Shimeng Yu
2024 J jnl
Thermally Constrained Codesign of Heterogeneous 3-D Integration of Compute-in-Memory, Digital ML Accelerator, and RISC-V Cores for Mixed ML and Non-ML Workloads.
IEEE Trans. Very Large Scale Integr. Syst.
Yuan-Chun Luo, Anni Lu, Janak Sharda, Moritz Scherer, Jorge Tomás Gómez, Syed Shakib Sarwar, Ziyun Li, Reid Frederick Pinkham, Barbara De Salvo, Shimeng Yu
2023 — conf
Low-Frequency Noise Characteristics of Ferroelectric Field-Effect Transistors.
IRPS
Omkar Phadke, Khandker Akif Aabrar, Yuan-Chun Luo, Sharadindu Gopal Kirtania, Asif Islam Khan, Suman Datta, Shimeng Yu
2023 J jnl
Scalable In-Memory Clustered Annealer With Temporal Noise of Charge Trap Transistor for Large Scale Travelling Salesman Problems.
IEEE J. Emerg. Sel. Topics Circuits Syst.
Anni Lu, Jae Hur, Yuan-Chun Luo, Hai Li, Dmitri E. Nikonov, Ian A. Young, Yang-Kyu Choi, Shimeng Yu
2022 J jnl
A Ferroelectric-Based Volatile/Non-Volatile Dual-Mode Buffer Memory for Deep Neural Network Accelerators.
IEEE Trans. Computers
Yandong Luo, Yuan-Chun Luo, Shimeng Yu
2022 J jnl
Design and Optimization of Non-Volatile Capacitive Crossbar Array for In-Memory Computing.
IEEE Trans. Circuits Syst. II Express Briefs
Yuan-Chun Luo, Anni Lu, Jae Hur, Shaolan Li, Shimeng Yu
2022 J jnl
Nonvolatile Capacitive Crossbar Array for In-Memory Computing.
Adv. Intell. Syst.
Jae Hur, Yuan-Chun Luo, Anni Lu, Tzu-Han Wang, Shaolan Li, Asif Islam Khan, Shimeng Yu
2021 A conf
A FeRAM based Volatile/Non-volatile Dual-mode Buffer Memory for Deep Neural Network Training.
DATE
Yandong Luo, Yuan-Chun Luo, Shimeng Yu
2021 — conf
A Technology Path for Scaling Embedded FeRAM to 28nm with 2T1C Structure.
IMW
Jae Hur, Yuan-Chun Luo, Zheng Wang, Wonbo Shim, Asif Islam Khan, Shimeng Yu
2021 — conf
Compute-in-Memory: From Device Innovation to 3D System Integration.
ESSDERC
Shimeng Yu, Wonbo Shim, Jae Hur, Yuan-Chun Luo, Gihun Choe, Wantong Li, Anni Lu, Xiaochen Peng
2021 — conf
Design of Non-volatile Capacitive Crossbar Array for In-Memory Computing.
IMW
Yuan-Chun Luo, Anni Lu, Jae Hur, Shaolan Li, Shimeng Yu
2020 — conf
Modeling Multi-states in Ferroelectric Tunnel Junction.
DRC
Yuan-Chun Luo, Jae Hur, Panni Wang, Asif Islam Khan, Shimeng Yu
2018 — conf
DrowsyNet: Convolutional neural networks with runtime power-accuracy tunability using inference-stage dropout.
VLSI-DAT
Ren-Shuo Liu, Yun-Chen Lo, Yuan-Chun Luo, Chih-Yu Shen, Cheng-Ju Lee