Yu Lee

16 papers A* 1A 1C 2Journal 4Unranked 8
YearRankTypeTitle / Venue / Authors
2022 — conf
Robust Timing Synchronization Algorithm for 5G New Radio.
WF-IoT
Yu Lee, Tzu-Chieh Kao, Zhen-Ming Huang, Hsuan-Po Lin, Chun-Ta Wu, Chao-Yu Chen
2019 J jnl
A Sustainable Soil Energy Harvesting System With Wide-Range Power-Tracking Architecture.
IEEE Internet Things J.
I-Che Ou, Jia-Ping Yang, Chia-Hung Liu, Kai-Jie Huang, Kun-Ju Tsai, Yu Lee, Yuan-Hua Chu, Yu-Te Liao
2018 — conf
A Wide-Range Capacitive DC-DC Converter with 2D-MPPT for Soil/Solar Energy Extraction.
A-SSCC
I-Che Ou, Jia-Ping Yang, Chia-Hung Liu, Kai-Jie Huang, Kun-Ju Tsai, Yu Lee, Yuan-Hua Chu, Yu-Te Liao
2017 J jnl
A 8 Phases 192MHz Crystal-Less Clock Generator with PVT Calibration.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Ting-Chou Lu, Ming-Dou Ker, Hsiao-Wen Zan, Jen-Chieh Liu, Yu Lee
2016 A* conf
Invited - Wireless sensor nodes for environmental monitoring in internet of things.
DAC
Ting-Chou Lu, Li-Ren Huang, Yu Lee, Kun-Ju Tsai, Yu-Te Liao, Nai-Chen Cheng, Yuan-Hua Chu, Yi-Hsing Tsai, Fang-Chu Chen, Tzi-cker Chiueh
2016 C conf
Live demonstrator: Challenging the Bio-inspired Artificial Pancreas with a mixed-meal model library.
ISCAS
Pau Herrero, Mohamed Fayez El-Sharkawy, Peter Pesl, Bernard Hernandez, Lorraine Choi, Osama M. Awara, Yu Lee, Jian Lim, Mohamed M. Yusof, Aaron Sheah, Liyangyi Yu, Pantelis Georgiou
2013 — conf
A 3.4mW 2.3-to-2.7GHz frequency synthesizer in 0.18-µm CMOS.
ESSCIRC
Chih-Hsiang Chang, Ching-Yuan Yang, Yu Lee, Jun-Hong Weng, Nai-Chen Cheng
2012 C conf
A chip-to-chip clock-deskewing circuit for 3-D ICs.
ISCAS
Ai-Jia Chuang, Yu Lee, Ching-Yuan Yang
2010 A conf
An embedded wide-range and high-resolution CLOCK jitter measurement circuit.
DATE
Yu Lee, Ching-Yuan Yang, Nai-Chen Daniel Cheng, Ji-Jan Chen
2009 — conf
Retargeting Motion of Clothing to New Characters.
GRAPP
Yu Lee, Moon-Ryul Jung
2008 J jnl
A PWM and PAM Signaling Hybrid Technology for Serial-Link Transceivers.
IEEE Trans. Instrum. Meas.
Ching-Yuan Yang, Yu Lee
2008 — conf
A programmable duty cycle corrector based on delta-sigma modulated PWM mechanism.
APCCAS
Gung-Yu Lin, Ching-Yuan Yang, Yu Lee, Jun-Hong Weng
2008 — conf
Experimental Results of Built-In Jitter Measurement for Gigahertz Clock.
ATS
Nai-Chen Daniel Cheng, Yu Lee, Ji-Jan Chen
2007 — conf
A 2-ps Resolution Wide Range BIST Circuit for Jitter Measurement.
ATS
Nai-Chen Daniel Cheng, Yu Lee, Ji-Jan Chen
2006 J jnl
A CMOS Clock and Data Recovery Circuit with a Half-Rate Three-State Phase Detector.
IEICE Trans. Electron.
Ching-Yuan Yang, Yu Lee, Cheng-Hsing Lee
2005 — conf
A 0.18-µm CMOS 1-Gb/s serial link transceiver by using PWM and PAM techniques.
ISCAS (2)
Ching-Yuan Yang, Yu Lee