Yu Huang

106 papers A* 4A 30B 5Misc 9Journal 23Unranked 35
YearRankTypeTitle / Venue / Authors
2025 J jnl
FGNN2: A Powerful Pretraining Framework for Learning the Logic Functionality of Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Ziyi Wang, Chen Bai, Zhuolun He, Guangliang Zhang, Qiang Xu, Tsung-Yi Ho, Yu Huang, Bei Yu
2025 J jnl
HDLdebugger: Streamlining HDL debugging with Large Language Models.
ACM Trans. Design Autom. Electr. Syst.
Xufeng Yao, Haoyang Li, Tsz Ho Chan, Wenyi Xiao, Mingxuan Yuan, Yu Huang, Lei Chen, Bei Yu
2024 A* conf
BetterV: Controlled Verilog Generation with Discriminative Guidance.
ICML
Zehua Pei, Hui-Ling Zhen, Mingxuan Yuan, Yu Huang, Bei Yu
2024 J jnl
BetterV: Controlled Verilog Generation with Discriminative Guidance.
CoRR
Zehua Pei, Hui-Ling Zhen, Mingxuan Yuan, Yu Huang, Bei Yu
2024 J jnl
Erratum to: Large circuit models: opportunities and challenges.
Sci. China Inf. Sci.
Lei Chen, Yiqi Chen, Zhufei Chu, Wenji Fang, Tsung-Yi Ho, Ru Huang, Yu Huang, Sadaf Khan, Min Li, Xingquan Li, Yu Li, Yun Liang, Jinwei Liu, Yi Liu, Yibo Lin, Guojie Luo, Hongyang Pan, Zhengyuan Shi, Guangyu Sun, Dimitrios Tsaras, Runsheng Wang, Ziyi Wang, Xinming Wei, Zhiyao Xie, Qiang Xu, Chenhao Xue, Junchi Yan, Jun Yang, Bei Yu, Mingxuan Yuan, Evangeline F. Y. Young, Xuan Zeng, Haoyi Zhang, Zuodong Zhang, Yuxiang Zhao, Hui-Ling Zhen, Ziyang Zheng, Binwu Zhu, Keren Zhu, Sunan Zou
2024 J jnl
HDLdebugger: Streamlining HDL debugging with Large Language Models.
CoRR
Xufeng Yao, Haoyang Li, Tsz Ho Chan, Wenyi Xiao, Mingxuan Yuan, Yu Huang, Lei Chen, Bei Yu
2024 J jnl
Large circuit models: opportunities and challenges.
Sci. China Inf. Sci.
Lei Chen, Yiqi Chen, Zhufei Chu, Wenji Fang, Tsung-Yi Ho, Ru Huang, Yu Huang, Sadaf Khan, Min Li, Xingquan Li, Yu Li, Yun Liang, Jinwei Liu, Yi Liu, Yibo Lin, Guojie Luo, Hongyang Pan, Zhengyuan Shi, Guangyu Sun, Dimitrios Tsaras, Runsheng Wang, Ziyi Wang, Xinming Wei, Zhiyao Xie, Qiang Xu, Chenhao Xue, Junchi Yan, Jun Yang, Bei Yu, Mingxuan Yuan, Evangeline F. Y. Young, Xuan Zeng, Haoyi Zhang, Zuodong Zhang, Yuxiang Zhao, Hui-Ling Zhen, Ziyang Zheng, Binwu Zhu, Keren Zhu, Sunan Zou
2024 J jnl
The Dawn of AI-Native EDA: Promises and Challenges of Large Circuit Models.
CoRR
Lei Chen, Yiqi Chen, Zhufei Chu, Wenji Fang, Tsung-Yi Ho, Yu Huang, Sadaf Khan, Min Li, Xingquan Li, Yun Liang, Yibo Lin, Jinwei Liu, Yi Liu, Guojie Luo, Zhengyuan Shi, Guangyu Sun, Dimitrios Tsaras, Runsheng Wang, Ziyi Wang, Xinming Wei, Zhiyao Xie, Qiang Xu, Chenhao Xue, Evangeline F. Y. Young, Bei Yu, Mingxuan Yuan, Haoyi Zhang, Zuodong Zhang, Yuxiang Zhao, Hui-Ling Zhen, Ziyang Zheng, Binwu Zhu, Keren Zhu, Sunan Zou
2023 J jnl
A Unified Framework for Layout Pattern Analysis With Deep Causal Estimation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Ran Chen, Shoubo Hu, Zhitang Chen, Shengyu Zhu, Bei Yu, Pengyun Li, Cheng Chen, Yu Huang, Jianye Hao
2023 J jnl
Conflict-driven Structural Learning Towards Higher Coverage Rate in ATPG.
CoRR
Hui-Ling Zhen, Naixing Wang, Junhua Huang, Xinyue Huang, Mingxuan Yuan, Yu Huang
2023 A conf
EffiSyn: Efficient Logic Synthesis with Dynamic Scoring and Pruning.
ICCAD
Xing Li, Lei Chen, Jiantang Zhang, Shuang Wen, Weihua Sheng, Yu Huang, Mingxuan Yuan
2023 A conf
TOFU: A Two-Step Floorplan Refinement Framework for Whitespace Reduction.
DATE
Shixiong Kai, Chak-Wa Pui, Fangzhou Wang, Shougao Jiang, Bin Wang, Yu Huang, Jianye Hao
2022 — conf
Accelerate SAT-based ATPG via Preprocessing and New Conflict Management Heuristics.
ASP-DAC
Junhua Huang, Hui-Ling Zhen, Naixing Wang, Mingxuan Yuan, Hui Mao, Yu Huang, Jiping Tao
2022 A conf
Compression-Aware ATPG.
ITC
Xing Wang, Zezhong Wang, Naixing Wang, Weiwei Zhang, Yu Huang
2022 A conf
DeepTPI: Test Point Insertion with Deep Reinforcement Learning.
ITC
Zhengyuan Shi, Min Li, Sadaf Khan, Liuzheng Wang, Naixing Wang, Yu Huang, Qiang Xu
2022 J jnl
DeepTPI: Test Point Insertion with Deep Reinforcement Learning.
CoRR
Zhengyuan Shi, Min Li, Sadaf Khan, Liuzheng Wang, Naixing Wang, Yu Huang, Qiang Xu
2022 A* conf
Functionality matters in netlist representation learning.
DAC
Ziyi Wang, Chen Bai, Zhuolun He, Guangliang Zhang, Qiang Xu, Tsung-Yi Ho, Bei Yu, Yu Huang
2022 J jnl
LHNN: Lattice Hypergraph Neural Network for VLSI Congestion Prediction.
CoRR
Bowen Wang, Guibao Shen, Dong Li, Jianye Hao, Wulong Liu, Yu Huang, Hongzhong Wu, Yibo Lin, Guangyong Chen, Pheng-Ann Heng
2022 A* conf
LHNN: lattice hypergraph neural network for VLSI congestion prediction.
DAC
Bowen Wang, Guibao Shen, Dong Li, Jianye Hao, Wulong Liu, Yu Huang, Hongzhong Wu, Yibo Lin, Guangyong Chen, Pheng-Ann Heng
2022 A conf
Neural Fault Analysis for SAT-based ATPG.
ITC
Junhua Huang, Hui-Ling Zhen, Naixing Wang, Hui Mao, Mingxuan Yuan, Yu Huang
2022 A conf
RCANet: Root Cause Analysis via Latent Variable Interaction Modeling for Yield Improvement.
ITC
Xiaopeng Zhang, Shoubo Hu, Zhitang Chen, Shengyu Zhu, Evangeline F. Y. Young, Pengyun Li, Cheng Chen, Yu Huang, Jianye Hao
2021 A conf
A Unified Framework for Layout Pattern Analysis with Deep Causal Estimation.
ICCAD
Ran Chen, Shoubo Hu, Zhitang Chen, Shengyu Zhu, Bei Yu, Pengyun Li, Cheng Chen, Yu Huang, Jianye Hao
2021 — conf
Automotive Test and Reliability.
ITC-Asia
Yu Huang, David Francis, Yervant Zorian, Nilanjan Mukherjee
2021 — conf
Diagnosis and Yield Learning.
ITC-Asia
Yu Huang, Wu-Tung Cheng, Ruifeng Guo, Sameer Chillarige
2021 J jnl
Representation Learning of Logic Circuits.
CoRR
Min Li, Sadaf Khan, Zhengyuan Shi, Naixing Wang, Yu Huang, Qiang Xu
2021 Misc conf
Special Session - Test for AI Chips: from DFT to On-line Testing.
VTS
Huawei Li, Xiaowei Li, Yu Huang, Ying Wang, Gary Guo
2021 A conf
Testability-Aware Low Power Controller Design with Evolutionary Learning.
ITC
Min Li, Zhengyuan Shi, Zezhong Wang, Weiwei Zhang, Yu Huang, Qiang Xu
2021 J jnl
Testability-Aware Low Power Controller Design with Evolutionary Learning.
CoRR
Min Li, Zhengyuan Shi, Zezhong Wang, Weiwei Zhang, Yu Huang, Qiang Xu
2020 J jnl
Diagnosis of Intermittent Scan Chain Faults Through a Multistage Neural Network Reasoning Process.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Mason Chern, Shih-Wei Lee, Shi-Yu Huang, Yu Huang, Gaurav Veda, Kun-Han Tsai, Wu-Tung Cheng
2020 Misc conf
Effective Design of Layout-Friendly EDT Decompressor.
VTS
Yu Huang, Janusz Rajski, Mark Kassab, Nilanjan Mukherjee, Jeffrey Mayer
2020 B conf
Efficient Prognostication of Pattern Count with Different Input Compression Ratios.
ETS
Fong-Jyun Tsai, Chong-Siao Ye, Yu Huang, Kuen-Jong Lee, Wu-Tung Cheng, Sudhakar M. Reddy, Mark Kassab, Janusz Rajski
2020 — conf
Estimation of Test Data Volume for Scan Architectures with Different Numbers of Input Channels.
ITC-Asia
Fong-Jyun Tsai, Chong-Siao Ye, Yu Huang, Kuen-Jong Lee, Wu-Tung Cheng, Sudhakar M. Reddy, Mark Kassab, Janusz Rajski, Shi-Xuan Zheng
2020 A conf
Fast Bring-Up of an AI SoC through IEEE 1687 Integrating Embedded TAPs and IEEE 1500 Interfaces.
ITC
Haiying Ma, Ligang Lu, Haitao Qian, Jing Han, Xin Wen, Fanjin Meng, Rahul Singhal, Martin Keim, Yu Huang, Wu Yang
2020 J jnl
Low Cost Hypercompression of Test Data.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Yu Huang, Sylwester Milewski, Janusz Rajski, Jerzy Tyszer, Chen Wang
2020 A conf
Prediction of Test Pattern Count and Test Data Volume for Scan Architectures under Different Input Channel Configurations.
ITC
Fong-Jyun Tsai, Chong-Siao Ye, Kuen-Jong Lee, Shi-Xuan Zheng, Yu Huang, Wu-Tung Cheng, Sudhakar M. Reddy, Mark Kassab, Janusz Rajski, Chen Wang, Justyna Zawada
2019 — conf
A Case Study of Testing Strategy for AI SoC.
ITC-Asia
Haiying Ma, Rui Guo, Quan Jing, Jing Han, Yu Huang, Rahul Singhal, Wu Yang, Xin Wen, Fanjin Meng
2019 — conf
Deep Learning Based Test Compression Analyzer.
ATS
Cheng-Hung Wu, Yu Huang, Kuen-Jong Lee, Wu-Tung Cheng, Gaurav Veda, Sudhakar M. Reddy, Chun-Cheng Hu, Chong-Siao Ye
2019 — conf
Improving scan chain diagnostic accuracy using multi-stage artificial neural networks.
ASP-DAC
Mason Chern, Shih-Wei Lee, Shi-Yu Huang, Yu Huang, Gaurav Veda, Kun-Han Hans Tsai, Wu-Tung Cheng
2019 Misc conf
Innovative Practices on DFT for AI Chips.
VTS
Iris Ma, Hui King Lau, Joseph A. Reynick, Yu Huang
2019 B conf
Non-Adaptive Pattern Reordering to Improve Scan Chain Diagnostic Resolution.
ETS
Yu Huang, Jakub Janicki, Szczepan Urban
2019 — conf
Reversible Scan Based Diagnostic Patterns.
VLSI-DAT
Yu Huang, Szczepan Urban, Wu-Tung Cheng, Manish Sharma, Fengju Niu, Junna Zhong, Wen-Lung Hsu
2019 — conf
Tutorial 1B: AI Chip Technologies and DFT Methodologies.
SoCC
Yu Huang, Rahul Singhal
2018 A conf
Hypercompression of Test Patterns.
ITC
Yu Huang, Sylwester Milewski, Janusz Rajski, Jerzy Tyszer, Chen Wang
2018 — conf
Industrial Case Studies of SoC Test Scheduling Optimization by Selecting Appropriate EDT Architectures.
ITC-Asia
Guoliang Li, Henry Zhao, Qinfu Yang, Jun Qian, Yu Huang
2018 Misc conf
Innovative practices on machine learning for emerging applications.
VTS
Kareem Madkour, Zhaobo Zhang, Alfred L. Crouch, Peter L. Levin, Eve Hunter, Yu Huang
2018 Misc conf
Special session on machine learning for test and diagnosis.
VTS
Krishnendu Chakrabarty, Li-C. Wang, Gaurav Veda, Yu Huang
2017 — conf
On designing two-dimensional scan architecture for test chips.
VLSI-DAT
Yu Huang, Wu-Tung Cheng
2017 — conf
Scan Chain Diagnosis Based on Unsupervised Machine Learning.
ATS
Yu Huang, Brady Benware, Randy Klingenberg, Huaxing Tang, Jayant Dsouza, Wu-Tung Cheng
2015 B conf
Advancements in diagnosis driven yield analysis (DDYA): A survey of state-of-the-art scan diagnosis and yield analysis technologies.
ETS
Yu Huang, Wu Yang, Wu-Tung Cheng
2015 J jnl
Diagnosis and Layout Aware (DLA) Scan Chain Stitching.
IEEE Trans. Very Large Scale Integr. Syst.
Jing Ye, Yu Huang, Yu Hu, Wu-Tung Cheng, Ruifeng Guo, Liyang Lai, Ting-Pu Tai, Xiaowei Li, Wei-pin Changchien, Daw-Ming Lee, Ji-Jan Chen, Sandeep C. Eruvathi, Kartik K. Kumara, Charles C. C. Liu, Sam Pan
2015 — conf
Hybrid Hierarchical and Modular Tests for SoC Designs.
NATW
Guoliang Li, Jun Qian, Qinfu Yang, Yuan Zuo, Rui Li, Yu Huang, Mark Kassab, Janusz Rajski
2015 J jnl
Scan Test Bandwidth Management for Ultralarge-Scale System-on-Chip Architectures.
IEEE Trans. Very Large Scale Integr. Syst.
Wu-Tung Cheng, Yan Dong, Grady Giles, Yu Huang, Jakub Janicki, Mark Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer
2014 — conf
Bit selection algorithm suitable for high-volume production of SRAM-PUF.
HOST
Kan Xiao, Md. Tauhidur Rahman, Domenic Forte, Yu Huang, Mei Su, Mohammad Tehranipoor
2014 J jnl
Diagnose Failures Caused by Multiple Locations at a Time.
IEEE Trans. Very Large Scale Integr. Syst.
Jing Ye, Yu Hu, Xiaowei Li, Wu-Tung Cheng, Yu Huang, Huaxing Tang
2014 — conf
Test Compression Improvement with EDT Channel Sharing in SoC Designs.
NATW
Yu Huang, Mark Kassab, Jay Jahangiri, Janusz Rajski, Wu-Tung Cheng, Dongkwan Han, Jihye Kim, Kun Young Chung
2013 A conf
Diagnosis and Layout Aware (DLA) scan chain stitching.
ITC
Jing Ye, Yu Huang, Yu Hu, Wu-Tung Cheng, Ruifeng Guo, Liyang Lai, Ting-Pu Tai, Xiaowei Li, Wei-pin Changchien, Daw-Ming Lee, Ji-Jan Chen, Sandeep C. Eruvathi, Kartik K. Kumara, Charles C. C. Liu, Sam Pan
2013 Misc conf
Distributed dynamic partitioning based diagnosis of scan chain.
VTS
Yu Huang, Xiaoxin Fan, Huaxing Tang, Manish Sharma, Wu-Tung Cheng, Brady Benware, Sudhakar M. Reddy
2013 A conf
EDT bandwidth management - Practical scenarios for large SoC designs.
ITC
Jakub Janicki, Jerzy Tyszer, Wu-Tung Cheng, Yu Huang, Mark Kassab, Nilanjan Mukherjee, Janusz Rajski, Yan Dong, Grady Giles
2012 — conf
A Hybrid Flow for Memory Failure Bitmap Classification.
Asian Test Symposium
Jianbo Li, Yu Huang, Wu-Tung Cheng, Chris Schuermyer, Dong Xiang, Eric Faehn, Ruth Farrugia
2012 A conf
Improved volume diagnosis throughput using dynamic design partitioning.
ITC
Xiaoxin Fan, Huaxing Tang, Yu Huang, Wu-Tung Cheng, Sudhakar M. Reddy, Brady Benware
2010 A conf
Case study of scan chain diagnosis and PFA on a low yield wafer.
ITC
Yu Huang, Brady Benware, Wu-Tung Cheng, Ting-Pu Tai, Feng-Ming Kuo, Yuan-Shih Chen
2010 — conf
Emulating and diagnosing IR-drop by using dynamic SDF.
ASP-DAC
Ke Peng, Yu Huang, Ruifeng Guo, Wu-Tung Cheng, Mohammad Tehranipoor
2010 — conf
Enhance Profiling-Based Scan Chain Diagnosis by Pattern Masking.
Asian Test Symposium
Wu-Tung Cheng, Yu Huang
2010 B conf
Full-circuit SPICE simulation based validation of dynamic delay estimation.
ETS
Ke Peng, Yu Huang, Pinki Mallick, Wu-Tung Cheng, Mohammad Tehranipoor
2010 J jnl
On Reducing Scan Shift Activity at RTL.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Elif Alpaslan, Yu Huang, Xijiang Lin, Wu-Tung Cheng, Jennifer Dworak
2010 A conf
Test cycle power optimization for scan-based designs.
ITC
Kun-Han Tsai, Yu Huang, Wu-Tung Cheng, Ting-Pu Tai, Augusli Kifli
2009 — conf
On Improving Diagnostic Test Generation for Scan Chain Failures.
Asian Test Symposium
Xun Tang, Ruifeng Guo, Wu-Tung Cheng, Sudhakar M. Reddy, Yu Huang
2009 — conf
Scan Chain Diagnosis by Adaptive Signal Profiling with Manufacturing ATPG Patterns.
Asian Test Symposium
Yu Huang, Wu-Tung Cheng, Ruifeng Guo, Ting-Pu Tai, Feng-Ming Kuo, Yuan-Shih Chen
2008 A conf
Detection and Diagnosis of Static Scan Cell Internal Defect.
ITC
Ruifeng Guo, Liyang Lai, Yu Huang, Wu-Tung Cheng
2008 A conf
Deterministic Diagnostic Pattern Generation (DDPG) for Compound Defects.
ITC
Fei Wang, Yu Hu, Huawei Li, Xiaowei Li, Jing Ye, Yu Huang
2008 B conf
Diagnose Multiple Stuck-at Scan Chain Faults.
ETS
Yu Huang, Wu-Tung Cheng, Ruifeng Guo
2008 — conf
Observation Point Oriented Deterministic Diagnosis Pattern Generation (DDPG) for Chain Diagnosis.
ATS
Fei Wang, Yu Hu, Yu Huang, Jing Ye, Xiaowei Li
2008 Misc conf
Reducing Scan Shift Power at RTL.
VTS
Elif Alpaslan, Yu Huang, Xijiang Lin, Wu-Tung Cheng, Jennifer Dworak
2008 J jnl
Scan Shift Power Reduction by Freezing Power Sensitive Scan Cells.
J. Electron. Test.
Xijiang Lin, Yu Huang
2008 J jnl
Survey of Scan Chain Diagnosis.
IEEE Des. Test Comput.
Yu Huang, Ruifeng Guo, Wu-Tung Cheng, James Chien-Mo Li
2007 — conf
A RTL Testability Analyzer Based on Logical Virtual Prototyping.
ATS
Yu Huang, Nilanjan Mukherjee, Wu-Tung Cheng, Greg Aldrich
2007 A conf
A complete test set to diagnose scan chain failures.
ITC
Ruifeng Guo, Yu Huang, Wu-Tung Cheng
2007 A conf
Diagnose compound scan chain and system logic defects.
ITC
Yu Huang, Wu-Tung Cheng, Ruifeng Guo, Will Hsu, Yuan-Shih Chen, Albert Mann
2007 A conf
Dynamic learning based scan chain diagnosis.
DATE
Yu Huang
2007 — conf
Effect of IR-Drop on Path Delay Testing Using Statistical Analysis.
ATS
Chunsheng Liu, Yang Wu, Yu Huang
2007 Misc conf
Effects of Embedded Decompression and Compaction Architectures on Side-Channel Attack Resistance.
VTS
Chunsheng Liu, Yu Huang
2007 — conf
Fault Dictionary Based Scan Chain Failure Diagnosis.
ATS
Ruifeng Guo, Yu Huang, Wu-Tung Cheng
2007 — conf
Programmable Logic BIST for At-speed Test.
ATS
Yu Huang, Xijiang Lin
2007 — conf
Scan Diagnosis and Its Successful Industrial Applications.
ATS
Wu Yang, Wu-Tung Cheng, Yu Huang, Martin Keim, Randy Klingenberg
2006 A conf
Diagnosis of defects on scan enable and clock trees.
DATE
Yu Huang, Keith Gallie
2006 A conf
Diagnosis with Limited Failure Information.
ITC
Yu Huang, Wu-Tung Cheng, Nagesh Tamarapalli, Janusz Rajski, Randy Klingenberg, Will Hsu, Yuan-Shih Chen
2006 — conf
On N-Detect Pattern Set Optimization.
ISQED
Yu Huang
2005 A conf
Compressed pattern diagnosis for scan chain failures.
ITC
Yu Huang, Wu-Tung Cheng, Janusz Rajski
2005 A conf
Off-shore outsource DFT vs. build off-shore branch offices.
ITC
Yu Huang
2005 — conf
Using fault model relaxation to diagnose real scan chain defects.
ASP-DAC
Yu Huang, Wu-Tung Cheng, Greg Crowell
2004 — conf
Compactor Independent Direct Diagnosis.
Asian Test Symposium
Wu-Tung Cheng, Kun-Han Tsai, Yu Huang, Nagesh Tamarapalli, Janusz Rajski
2004 A conf
Intermittent Scan Chain Fault Diagnosis Based on Signal Probability Analysis.
DATE
Yu Huang, Wu-Tung Cheng, Cheng-Ju Hsieh, Huan-Yung Tseng, Alou Huang, Yu-Ting Hung
2003 — conf
Efficient Diagnosis for Multiple Intermittent Scan Chain Hold-Time Faults.
Asian Test Symposium
Yu Huang, Wu-Tung Cheng, Cheng-Ju Hsieh, Huan-Yung Tseng, Alou Huang, Yu-Ting Hung
2003 Misc conf
SOC Test Scheduling Using Simulated Annealing.
VTS
Wei Zou, Sudhakar M. Reddy, Irith Pomeranz, Yu Huang
2003 — conf
Static Pin Mapping and SOC Test Scheduling for Cores with Multiple Test Sets.
ISQED
Yu Huang, Wu-Tung Cheng, Chien-Chung Tsai, Nilanjan Mukherjee, Sudhakar M. Reddy
2003 A conf
Statistical Diagnosis for Intermittent Scan Chain Hold-Time Fault.
ITC
Yu Huang, Wu-Tung Cheng, Sudhakar M. Reddy, Cheng-Ju Hsieh, Yu-Ting Hung
2003 A* conf
Using embedded infrastructure IP for SOC post-silicon verification.
DAC
Yu Huang, Wu-Tung Cheng
2002 — conf
Constraint Driven Pin Mapping for Concurrent SOC Testing.
ASP-DAC/VLSI Design
Yu Huang, Nilanjan Mukherjee, Chien-Chung Tsai, Omer Samman, Yahya Zaidan, Yanping Zhang, Wu-Tung Cheng, Sudhakar M. Reddy
2002 — conf
Core - Clustering Based SOC Test Scheduling Optimization.
Asian Test Symposium
Yu Huang, Sudhakar M. Reddy, Wu-Tung Cheng
2002 J jnl
On Concurrent Test of Core-Based SOC Design.
J. Electron. Test.
Yu Huang, Wu-Tung Cheng, Chien-Chung Tsai, Nilanjan Mukherjee, Omer Samman, Yahya Zaidan, Sudhakar M. Reddy
2002 A conf
Optimal Core Wrapper Width Selection and SOC Test Scheduling Based on 3-D Bin Packing Algorithm.
ITC
Yu Huang, Sudhakar M. Reddy, Wu-Tung Cheng, Paul Reuter, Nilanjan Mukherjee, Chien-Chung Tsai, Omer Samman, Yahya Zaidan
2002 J jnl
Synthesis of Scan Chains for Netlist Descriptions at RT-Level.
J. Electron. Test.
Yu Huang, Chien-Chung Tsai, Nilanjan Mukherjee, Omer Samman, Wu-Tung Cheng, Sudhakar M. Reddy
2001 — conf
Effect of RTL coding style on testability.
CICC
Yu Huang, Chien-Chung Tsai, Nilanjan Mukherhee, Wu-Tung Cheng, Sudhakar M. Reddy
2001 A conf
On RTL scan design.
ITC
Yu Huang, Chien-Chung Tsai, Nilanjan Mukherjee, Omer Samman, Dan Devries, Wu-Tung Cheng, Sudhakar M. Reddy
2001 — conf
Resource Allocation and Test Scheduling for Concurrent Test of Core-Based SoC D.
Asian Test Symposium
Yu Huang, Wu-Tung Cheng, Chien-Chung Tsai, Nilanjan Mukherjee, Omer Samman, Yahya Zaidan, Sudhakar M. Reddy
2000 A conf
Improving the Proportion of At-Speed Tests in Scan BIST.
ICCAD
Yu Huang, Irith Pomeranz, Sudhakar M. Reddy, Janusz Rajski