Yu Hu

57 papers A* 5A 9B 2Journal 22Unranked 19
YearRankTypeTitle / Venue / Authors
2021 J jnl
Quantization of Deep Neural Networks for Accurate Edge Computing.
ACM J. Emerg. Technol. Comput. Syst.
Wentao Chen, Hailong Qiu, Jian Zhuang, Chutong Zhang, Yu Hu, Qing Lu, Tianchen Wang, Yiyu Shi, Meiping Huang, Xiaowei Xu
2021 J jnl
Quantization of Deep Neural Networks for Accurate EdgeComputing.
CoRR
Wentao Chen, Hailong Qiu, Jian Zhuang, Chutong Zhang, Yu Hu, Qing Lu, Tianchen Wang, Yiyu Shi, Meiping Huang, Xiaowei Xu
2019 J jnl
MDA: A Reconfigurable Memristor-Based Distance Accelerator for Time Series Mining on Data Centers.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Xiaowei Xu, Feng Lin, Wenyao Xu, Xinwei Yao, Yiyu Shi, Dewen Zeng, Yu Hu
2018 J jnl
Accelerating Dynamic Time Warping With Memristor-Based Customized Fabrics.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Xiaowei Xu, Feng Lin, Aosen Wang, Xinwei Yao, Qing Lu, Wenyao Xu, Yiyu Shi, Yu Hu
2018 J jnl
Efficient Hardware Implementation of Cellular Neural Networks with Incremental Quantization and Early Exit.
ACM J. Emerg. Technol. Comput. Syst.
Xiaowei Xu, Qing Lu, Tianchen Wang, Yu Hu, Chen Zhuo, Jinglan Liu, Yiyu Shi
2018 A* conf
Quantization of Fully Convolutional Networks for Accurate Biomedical Image Segmentation.
CVPR
Xiaowei Xu, Qing Lu, Lin Yang, Xiaobo Sharon Hu, Danny Z. Chen, Yu Hu, Yiyu Shi
2018 J jnl
Quantization of Fully Convolutional Networks for Accurate Biomedical Image Segmentation.
CoRR
Xiaowei Xu, Qing Lu, Yu Hu, Lin Yang, Xiaobo Sharon Hu, Danny Ziyi Chen, Yiyu Shi
2018 J jnl
Scalable and Parameterized Architecture for Efficient Stream Mining.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Li Zhang, Dawei Li, Xuecheng Zou, Yu Hu, Xiaowei Xu
2017 A* conf
An Efficient Memristor-based Distance Accelerator for Time Series Data Mining on Data Centers.
DAC
Xiaowei Xu, Dewen Zeng, Wenyao Xu, Yiyu Shi, Yu Hu
2017 — conf
Efficient hardware implementation of cellular neural networks with powers-of-two based incremental quantization.
NCS
Xiaowei Xu, Qing Lu, Tianchen Wang, Jinglan Liu, Yu Hu, Yiyu Shi
2016 J jnl
Body-Earth Mover's Distance: A Matching-Based Approach for Sleep Posture Recognition.
IEEE Trans. Biomed. Circuits Syst.
Xiaowei Xu, Feng Lin, Aosen Wang, Yu Hu, Ming-Chun Huang, Wenyao Xu
2015 J jnl
A flexible control study of variable speed limit in connected vehicle systems.
Int. J. Embed. Syst.
Lu Pu, Xiaowei Xu, Han He, Hanqing Zhou, Zhijun Qiu, Yu Hu
2015 — conf
Energy-efficient pipelined DTW architecture on hybrid embedded platforms.
IGSC
Hanqing Zhou, Xiaowei Xu, Yu Hu, Guangyu Yu, Zeyu Yan, Feng Lin, Wenyao Xu
2015 — conf
On-bed sleep posture recognition based on body-earth mover's distance.
BioCAS
Xiaowei Xu, Feng Lin, Aosen Wang, Chen Song, Yu Hu, Wenyao Xu
2013 — conf
A Simulation Study of Connected Vehicle Systems Using Named Data Networking.
CloudComp
Tao Jiang, Xiaowei Xu, Lu Pu, Yu Hu, Zhijun Qiu
2013 — conf
An energy-efficient sub-Nyquist sampling method based on compressed sensing in wireless sensor network for vehicle detection.
ICCVE
Jiangchen Li, Xiaowei Xu, Hongpeng Zhao, Yu Hu, Tony Z. Qiu
2013 J jnl
Fast Filter-Based Boolean Matchers.
IEEE Embed. Syst. Lett.
Chaofan Yu, Lingli Wang, Chun Zhang, Yu Hu, Lei He
2013 J jnl
SPECO: Stochastic Perturbation based Clock tree Optimization considering temperature uncertainty.
Integr.
Sina Basir-Kazeruni, Hao Yu, Fang Gong, Yu Hu, Chunchen Liu, Lei He
2011 — conf
A method to build reconfigurable architectures by extracting common subgraphs.
ASICON
Tianyun Zhang, Rui Zhang, Lingli Wang, Yu Hu
2011 B conf
Acceleration of Multi-agent Simulation on FPGAs.
FPL
Lintao Cui, Jing Chen, Yu Hu, Jinjun Xiong, Zhe Feng, Lei He
2011 — conf
Enhancement of incremental design for FPGAs using circuit similarity.
ISQED
Xiaoyu Shi, Dahua Zeng, Yu Hu, Guohui Lin, Osmar R. Zaïane
2011 B conf
IPF: In-Place X-Filling to Mitigate Soft Errors in SRAM-Based FPGAs.
FPL
Zhe Feng, Naifeng Jing, Gengsheng Chen, Yu Hu, Lei He
2011 J jnl
In-Place FPGA Retiming for Mitigation of Variational Single-Event Transient Faults.
IEEE Trans. Circuits Syst. I Regul. Pap.
Wenyao Xu, Jia Wang, Yu Hu, Ju-Yueh Lee, Fang Gong, Lei He, Majid Sarrafzadeh
2011 J jnl
System-in-Package: Electrical and Layout Perspectives.
Found. Trends Electron. Des. Autom.
Lei He, Shauki Elassaad, Yiyu Shi, Yu Hu, Wei Yao
2010 J jnl
Accelerating Boolean Matching Using Bloom Filter.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Chun Zhang, Yu Hu, Lingli Wang, Lei He, Jiarong Tong
2010 — conf
Accelerating FPGA design space exploration using circuit similarity-based placement.
FPT
Xiaoyu Shi, Dahua Zeng, Yu Hu, Guohui Lin, Osmar R. Zaïane
2010 A conf
Building a faster boolean matcher using bloom filter.
FPGA
Chun Zhang, Yu Hu, Lingli Wang, Lei He, Jiarong Tong
2010 A conf
Engineering a scalable Boolean matching based on EDA SaaS 2.0.
ICCAD
Chun Zhang, Yu Hu, Lingli Wang, Lei He, Jiarong Tong
2010 — conf
Fault-tolerant resynthesis with dual-output LUTs.
ASP-DAC
Ju-Yueh Lee, Yu Hu, Rupak Majumdar, Lei He, Minming Li
2010 A conf
On power and fault-tolerance optimization in FPGA physical synthesis.
ICCAD
Manu Jose, Yu Hu, Rupak Majumdar
2010 A conf
RALF: Reliability Analysis for Logic Faults - An exact algorithm and its applications.
DATE
Samuel B. Luckenbill, Ju-Yueh Lee, Yu Hu, Rupak Majumdar, Lei He
2010 A* conf
Rewiring for robustness.
DAC
Manu Jose, Yu Hu, Rupak Majumdar, Lei He
2009 J jnl
Design and Synthesis of Programmable Logic Block With Mixed LUT and Macrogate.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Yu Hu, Satyaki Das, Steven Trimberger, Lei He
2009 A conf
IPR: In-Place Reconfiguration for FPGA fault tolerance.
ICCAD
Zhe Feng, Yu Hu, Lei He, Rupak Majumdar
2009 — conf
Simultaneous test pattern compaction, ordering and X-filling for testing power reduction.
ISQED
Ju-Yueh Lee, Yu Hu, Rupak Majumdar, Lei He
2009 — conf
Worst case timing jitter and amplitude noise in differential signaling.
ISQED
Wei Yao, Yiyu Shi, Lei He, Sudhakar Pamarti, Yu Hu
2008 J jnl
A full-scale solution to the rectilinear obstacle-avoiding Steiner problem.
Integr.
Tom Tong Jing, Yu Hu, Zhe Feng, Xianlong Hong, Xiaodong Hu, Guiying Yan
2008 J jnl
Dual-V
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
King Ho Tam, Yu Hu, Lei He, Tom Tong Jing, Xinyi Zhang
2008 J jnl
Exploiting Symmetries to Speed Up SAT-Based Boolean Matching for Logic Synthesis of FPGAs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Yu Hu, Victor Shih, Rupak Majumdar, Lei He
2008 A* conf
FPGA area reduction by multi-output function based sequential resynthesis.
DAC
Yu Hu, Victor Shih, Rupak Majumdar, Lei He
2008 J jnl
Fashion: A Fast and Accurate Solution to Global Routing Problem.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Zhen Cao, Tong Jing, Jinjun Xiong, Yu Hu, Zhe Feng, Lei He, Xianlong Hong
2008 J jnl
Physical synthesis for FPGA interconnect power reduction by dual-Vdd budgeting and retiming.
ACM Trans. Design Autom. Electr. Syst.
Yu Hu, Yan Lin, Lei He, Tim Tuan
2008 A conf
Robust FPGA resynthesis based on fault-tolerant Boolean matching.
ICCAD
Yu Hu, Zhe Feng, Lei He, Rupak Majumdar
2007 A conf
Design, synthesis and evaluation of heterogeneous FPGA with mixed LUTs and macro-gates.
ICCAD
Yu Hu, Satyaki Das, Steven Trimberger, Lei He
2007 — conf
DpRouter: A Fast and Accurate Dynamic-Pattern-Based Global Routing Algorithm.
ASP-DAC
Zhen Cao, Tong Jing, Jinjun Xiong, Yu Hu, Lei He, Xianlong Hong
2007 A conf
Exploiting symmetry in SAT-based Boolean matching for heterogeneous FPGA technology mapping.
ICCAD
Yu Hu, Victor Shih, Rupak Majumdar, Lei He
2007 — conf
Fast dual-vdd buffering based on interconnect prediction and sampling.
SLIP
Yu Hu, King Ho Tam, Tong Jing, Lei He
2007 — conf
Minimal skew clock embedding considering time variant temperature gradient.
ISPD
Hao Yu, Yu Hu, Chunchen Liu, Lei He
2007 J jnl
lambda-OAT: lambda-Geometry Obstacle-Avoiding Tree Construction With O(nlog n) Complexity.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Tom Tong Jing, Zhe Feng, Yu Hu, Xianlong Hong, Xiaodong Hu, Guiying Yan
2006 J jnl
ACO-Steiner: Ant Colony Optimization Based Rectilinear Steiner Minimal Tree Algorithm.
J. Comput. Sci. Technol.
Yu Hu, Tong Jing, Zhe Feng, Xianlong Hong, Xiaodong Hu, Guiying Yan
2006 — conf
An
ISPD
Zhe Feng, Yu Hu, Tong Jing, Xianlong Hong, Xiaodong Hu, Guiying Yan
2006 A conf
An efficient chip-level time slack allocation algorithm for Dual-Vdd FPGA power reduction.
ISLPED
Yan Lin, Yu Hu, Lei He, Vijay Raghunat
2006 — conf
DraXRouter: global routing in X-Architecture with dynamic resource assignment.
ASP-DAC
Zhen Cao, Tong Jing, Yu Hu, Yiyu Shi, Xianlong Hong, Xiaodong Hu, Guiying Yan
2006 A* conf
Simultaneous time slack budgeting and retiming for dual-Vdd FPGA power reduction.
DAC
Yu Hu, Yan Lin, Lei He, Tim Tuan
2005 — conf
A Routing Paradigm with Novel Resources Estimation and Routability Models for X-Architecture Based Physical Design.
SAMOS
Yu Hu, Tong Jing, Xianlong Hong, Xiaodong Hu, Guiying Yan
2005 — conf
An-OARSMan: obstacle-avoiding routing tree construction with good length performance.
ASP-DAC
Yu Hu, Tong Jing, Xianlong Hong, Zhe Feng, Xiaodong Hu, Guiying Yan
2005 — conf
Via-Aware Global Routing for Good VLSI Manufacturability and High Yield.
ASAP
Yang Yang, Tong Jing, Xianlong Hong, Yu Hu, Qi Zhu, Xiaodong Hu, Guiying Yan