Yu Deng - RankMe

27 papers A* 1B 5C 5Journal 7Unranked 9

Year	Rank	Type	Title / Venue / Authors
2020	J	`jnl`	ASIE: An Asynchronous SNN Inference Engine for AER Events Processing. ACM J. Emerg. Technol. Comput. Syst. Ziyang Kang, Lei Wang, Shasha Guo, Rui Gong, Shiming Li, Yu Deng, Weixia Xu
2020	J	`jnl`	CSMO-DSE: Fast and Precise Application-driven DSE Guided by Criticality and Sensitivity Analysis. ACM J. Emerg. Technol. Comput. Syst. Lei Wang, Yu Deng, Rui Gong, Wei Shi, Li Luo, Yongwen Wang
2020	J	`jnl`	Laius: an energy-efficient FPGA CNN accelerator with the support of a fixed-point training framework. Int. J. Comput. Sci. Eng. Zikai Nie, Zhisheng Li, Lei Wang, Shasha Guo, Yu Deng, Rangyu Deng, Qiang Dou
2020	J	`jnl`	SIES: A Novel Implementation of Spiking Convolutional Neural Network Inference Engine on Field-Programmable Gate Array. J. Comput. Sci. Technol. Shuquan Wang, Lei Wang, Yu Deng, Zhi-Jie Yang, Sha-Sha Guo, Ziyang Kang, Yu-Feng Guo, Weixia Xu
2019	—	`conf`	A Systolic SNN Inference Accelerator and its Co-optimized Software Framework. ACM Great Lakes Symposium on VLSI Shasha Guo, Lei Wang, Shuquan Wang, Yu Deng, Zhijie Yang, Shiming Li, Zhige Xie, Qiang Dou
2019	—	`conf`	ASIE: An Asynchronous SNN Inference Engine for AER Events Processing. ASYNC Ziyang Kang, Lei Wang, Shasha Guo, Rui Gong, Yu Deng, Qiang Dou
2018	—	`conf`	A Parallel Algorithm for Instruction Dependence Graph Analysis Based on Multithreading. ISPA/IUCC/BDCloud/SocialCom/SustainCom Lei Wang, Yu Deng, Rui Gong, Wei Shi, Zhenyu Zhao, Qiang Dou
2018	—	`conf`	A Power Efficient Hardware Implementation of the IF Neuron Model. ACA Shuquan Wang, Shasha Guo, Lei Wang, Nan Li, Zikai Nie, Yu Deng, Qiang Dou, Weixia Xu
2018	C	`conf`	Systolic Array Based Accelerator and Algorithm Mapping for Deep Learning Algorithms. NPC Zhijie Yang, Lei Wang, Dong Ding, Xiangyu Zhang, Yu Deng, Shiming Li, Qiang Dou
2017	—	`conf`	Laius: An 8-Bit Fixed-Point CNN Hardware Inference Engine. ISPA/IUCC Zhisheng Li, Lei Wang, Shasha Guo, Yu Deng, Qiang Dou, Haifang Zhou, Wenyuan Lu
2016	C	`conf`	The Macro-DSE for HPC Processing Unit: The Physical Constraints Perspective. GPC Yuxing Tang, Lei Wang, Yu Deng, Xiaoqiang Ni, Qiang Dou
2015	—	`conf`	A Scalable and Fast Microprocessor Design Space Exploration Methodology. MCSoC Lei Wang, Yuxing Tang, Yu Deng, Fangyan Qin, Qiang Dou, Guangda Zhang, Feipeng Zhang
2009	B	`conf`	Comparability graph coloring for optimizing utilization of stream register files in stream processors. PPoPP Xuejun Yang, Li Wang, Jingling Xue, Yu Deng, Ying Zhang
2009	J	`jnl`	Fei Teng 64 Stream Processing System: Architecture, Compiler, and Programming. IEEE Trans. Parallel Distributed Syst. Xuejun Yang, Xiaobo Yan, Zuocheng Xing, Yu Deng, Jiang Jiang, Jing Du, Ying Zhang
2009	J	`jnl`	Matrix-based streamization approach for improving locality and parallelism on FT64 stream processor. J. Supercomput. Xuejun Yang, Jing Du, Xiaobo Yan, Yu Deng
2009	J	`jnl`	SRF Coloring: Stream Register File Allocation via Graph Coloring. J. Comput. Sci. Technol. Xuejun Yang, Yu Deng, Li Wang, Xiaobo Yan, Jing Du, Ying Zhang, Guibin Wang, Tao Tang
2008	—	`conf`	A Double-Buffering Strategy for the SRF management in the Imagine Stream Processor. ICYCS Yu Deng, Li Wang, Xiaobo Yan, Xuejun Yang
2008	B	`conf`	Optimizing scientific application loops on stream processors. LCTES Li Wang, Xuejun Yang, Jingling Xue, Yu Deng, Xiaobo Yan, Tao Tang, Quan Hoang Nguyen
2008	B	`conf`	Scientific Computing Applications on a Stream Processor. ISPASS Ying Zhang, Xuejun Yang, Guibin Wang, Ian Rogers, Gen Li, Yu Deng, Xiaobo Yan
2007	A*	`conf`	A 64-bit stream processor architecture for scientific applications. ISCA Xuejun Yang, Xiaobo Yan, Zuocheng Xing, Yu Deng, Jiang Jiang, Ying Zhang
2007	B	`conf`	Efficient generation of stream programs from loops. ICPADS Xuejun Yang, Yu Deng, Xiaobo Yan, Li Wang, Jing Du, Ying Zhang
2007	B	`conf`	Evaluation of Transcendental Functions on Imagine Architecture. ICPP Xiaobo Yan, Tao Tang, Yu Deng, Jing Du, Xuejun Yang
2007	C	`conf`	Implementation and Evaluation of Specific Data-Intensive Scientific Applications on the FT64 Stream Processor. CIT Yu Deng, Xuejun Yang, Xiaobo Yan, Ying Zhang, Jing Du
2007	C	`conf`	Implementation and Optimization of Sparse Matrix-Vector Multiplication on Imagine Stream Processor. ISPA Li Wang, Xuejun Yang, Guibin Wang, Xiaobo Yan, Yu Deng, Jing Du, Ying Zhang, Tao Tang, Kun Zeng
2007	—	`conf`	Laplace Transformation on the FT64 Stream Processor. Asia-Pacific Computer Systems Architecture Conference Yu Deng, Xuejun Yang, Xiaobo Yan, Kun Zeng
2006	C	`conf`	Matrix-Based Programming Optimization for Improving Memory Hierarchy Performance on Imagine. ISPA Xuejun Yang, Jing Du, Xiaobo Yan, Yu Deng
2004	—	`conf`	The Design and Performance Analysis of Embedded Parallel Multiprocessing System. ICESS Guanghui Liu, Fei Xia, Xuejun Yang, Haifang Zhou, Heng Zhao, Yu Deng