Yu Cao - RankMe

258 papers A* 22A 40B 7C 13Misc 2Journal 106Unranked 66

Year	Rank	Type	Title / Venue / Authors
2026	—	`conf`	Chiplet-NAS: Chiplet-aware Neural Architecture Search for Efficient AI Inference on 2.5D Integration. ASP-DAC Cheng Guo, Pragnya Sudershan Nalla, Nikhil K. Cherukuri, Rui Xue, Sachin S. Sapatnekar, Chaitali Chakrabarti, Yu Cao, Jeff Zhang
2026	J	`jnl`	Mozart: Modularized and Efficient MoE Training on 3.5D Wafer-Scale Chiplet Architectures. CoRR Shuqing Luo, Ye Han, Pingzhi Li, Jiayin Qin, Jie Peng, Yang Zhao, Yu Cao, Tianlong Chen
2026	A	`conf`	vFPGA: Towards Sub-µs Reconfiguration via 3D FPGA and Packaging Co-Design. FPGA Nikhil K. Cherukuri, Sharad Nag, Pragnya Sudershan Nalla, Ashish K. Kola, Chetan S. Gadireddi, Kevin Dai, Jae-sun Seo, Zhenman Fang, Jeff Zhang, Yu Cao
2025	A	`conf`	Adaptive Graph Learning for Efficient Thermal Analysis of Multi-Stacking Chiplet Systems under Interface Variations. ICCAD Ziyao Yang, Jingbo Sun, Vidya A. Chhabria, Yu Cao
2025	A	`conf`	CLAIRE: Composable Chiplet Libraries for AI Inference. DATE Pragnya Sudershan Nalla, Emad Haque, Yaotian Liu, Sachin S. Sapatnekar, Jeff Zhang, Chaitali Chakrabarti, Yu Cao
2025	J	`jnl`	GUI-Spotlight: Adaptive Iterative Focus Refinement for Enhanced GUI Visual Grounding. CoRR Bin Lei, Nuo Xu, Ali Payani, Ming-Yi Hong, Chunhua Liao, Yu Cao, Caiwen Ding
2025	J	`jnl`	HDLxGraph: Bridging Large Language Models and HDL Repositories via HDL Graph Databases. CoRR Pingqing Zheng, Jiayin Qin, Fuqi Zhang, Shang Wu, Yu Cao, Caiwen Ding, Yang Zhao
2025	J	`jnl`	HISIM: Analytical Performance Modeling and Design Space Exploration of 2.5D/3D Integration for AI Computing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Zhenyu Wang, Pragnya Sudershan Nalla, Jingbo Sun, A. Alper Goksoy, Sumit K. Mandal, Jae-sun Seo, Vidya A. Chhabria, Jeff Zhang, Chaitali Chakrabarti, Ümit Y. Ogras, Yu Cao
2025	A	`conf`	MAHL: Multi-Agent LLM-Guided Hierarchical Chiplet Design with Adaptive Debugging. ICCAD Jinwei Tang, Jiayin Qin, Nuo Xu, Pragnya Sudershan Nalla, Yu Cao, Yang Katie Zhao, Caiwen Ding
2025	J	`jnl`	MAHL: Multi-Agent LLM-Guided Hierarchical Chiplet Design with Adaptive Debugging. CoRR Jinwei Tang, Jiayin Qin, Nuo Xu, Pragnya Sudershan Nalla, Yu Cao, Yang Zhao, Caiwen Ding
2025	J	`jnl`	Occult: Optimizing Collaborative Communication across Experts for Accelerated Parallel MoE Training and Inference. CoRR Shuqing Luo, Pingzhi Li, Jie Peng, Hanrui Wang, Yang Zhao, Yu Cao, Yu Cheng, Tianlong Chen
2025	A*	`conf`	Occult: Optimizing Collaborative Communications across Experts for Accelerated Parallel MoE Training and Inference. ICML Shuqing Luo, Pingzhi Li, Jie Peng, Yang Zhao, Yu Cao, Yu Cheng, Tianlong Chen
2025	A*	`conf`	RTGS: Real-Time 3D Gaussian Splatting SLAM via Multi-Level Redundancy Reduction. MICRO Leshu Li, Jiayin Qin, Jie Peng, Zishen Wan, Huaizhi Qu, Ye Han, Pingqing Zheng, Hongsen Zhang, Yu Cao, Tianlong Chen, Yang Katie Zhao
2025	J	`jnl`	RTGS: Real-Time 3D Gaussian Splatting SLAM via Multi-Level Redundancy Reduction. CoRR Leshu Li, Jiayin Qin, Jie Peng, Zishen Wan, Huaizhi Qu, Ye Han, Pingqing Zheng, Hongsen Zhang, Yu Cao, Tianlong Chen, Yang Katie Zhao
2025	J	`jnl`	Tiny Chiplets Enabled by Packaging Scaling: Opportunities in ESD Protection and Signal Integrity. CoRR Emad Haque, Pragnya Sudershan Nalla, Jeff Zhang, Sachin S. Sapatnekar, Chaitali Chakrabarti, Yu Cao
2025	A*	`conf`	Uncertainty-Based Extensible Codebook for Discrete Federated Learning in Heterogeneous Data Silos. ICML Tianyi Zhang, Yu Cao, Dianbo Liu
2024	A	`conf`	A 16nm Heterogeneous Accelerator for Energy-Efficient Sparse and Dense AI Computing. ISLPED Gopikrishnan Raveendran Nair, Fengyang Jiang, Jeff Zhang, Yu Cao
2024	J	`jnl`	A 65-nm RRAM Compute-in-Memory Macro for Genome Processing. IEEE J. Solid State Circuits Fan Zhang, Amitesh Sridharan, Wangxin He, Injune Yeo, Maximilian Liehr, Wei Zhang, Nathaniel C. Cady, Yu Cao, Jae-sun Seo, Deliang Fan
2024	J	`jnl`	A Progressive Subnetwork Searching Framework for Dynamic Inference. IEEE Trans. Neural Networks Learn. Syst. Li Yang, Zhezhi He, Yu Cao, Deliang Fan
2024	A	`conf`	Cryogenic Operation of Computing-In-Memory based Spiking Neural Network. ISLPED Laith A. Shamieh, Wei-Chun Wang, Shida Zhang, Rakshith Saligram, Amol D. Gaidhane, Yu Cao, Arijit Raychowdhury, Suman Datta, Saibal Mukhopadhyay
2024	B	`conf`	Exploiting 2.5D/3D Heterogeneous Integration for AI Computing. ASPDAC Zhenyu Wang, Jingbo Sun, A. Alper Goksoy, Sumit K. Mandal, Yaotian Liu, Jae-sun Seo, Chaitali Chakrabarti, Ümit Y. Ogras, Vidya A. Chhabria, Jeff Zhang, Yu Cao
2024	J	`jnl`	HiVeGen - Hierarchical LLM-based Verilog Generation for Scalable Chip Design. CoRR Jinwei Tang, Jiayin Qin, Kiran Thorat, Chen Tian, Yu Cao, Yang Zhao, Caiwen Ding
2024	J	`jnl`	High Throughput FPGA-Based Object Detection via Algorithm-Hardware Co-Design. ACM Trans. Reconfigurable Technol. Syst. Anupreetham Anupreetham, Mohamed Ibrahim, Mathew Hall, Andrew Boutros, Ajay Kuzhively, Abinash Mohanty, Eriko Nurvitadhi, Vaughn Betz, Yu Cao, Jae-sun Seo
2024	—	`ch.`	In-Memory Computing for AI Accelerators: Challenges and Solutions. Embedded Machine Learning for Cyber-Physical, IoT, and Edge Computing: Hardware Architectures Gokul Krishnan, Sumit K. Mandal, Chaitali Chakrabarti, Jae-sun Seo, Ümit Y. Ogras, Yu Cao
2024	A	`conf`	Patch-based Selection and Refinement for Early Object Detection. WACV Tianyi Zhang, Kishore Kasichainula, Yaoxin Zhuo, Baoxin Li, Jae-sun Seo, Yu Cao
2024	—	`conf`	SHIFFT: A Scalable Hybrid In-Memory Computing FFT Accelerator. ISVLSI Pragnya Sudershan Nalla, Zhenyu Wang, Sapan Agarwal, T. Patrick Xiao, Christopher H. Bennett, Matthew J. Marinella, Jae-sun Seo, Yu Cao
2024	A*	`conf`	Transformer-Based Selective Super-resolution for Efficient Image Refinement. AAAI Tianyi Zhang, Kishore Kasichainula, Yaoxin Zhuo, Baoxin Li, Jae-sun Seo, Yu Cao
2024	J	`jnl`	Uncertainty-Based Extensible Codebook for Discrete Federated Learning in Heterogeneous Data Silos. CoRR Tianyi Zhang, Yu Cao, Dianbo Liu
2023	—	`conf`	3D-ISC: A 65nm 3D Compatible In-Sensor Computing Accelerator with Reconfigurable Tile Architecture for Real-Time DVS Data Compression. A-SSCC Gokul Krishnan, Gopikrishnan Raveendran Nair, Jonghyun Oh, Anupreetham Anupreetham, Pragnya Sudershan Nalla, Ahmed Hassan, Injune Yeo, Kishore Kasichainula, Jae-sun Seo, Mingoo Seok, Yu Cao
2023	—	`conf`	A 65nm RRAM Compute-in-Memory Macro for Genome Sequencing Alignment. ESSCIRC Fan Zhang, Wangxin He, Injune Yeo, Maximilian Liehr, Nathaniel C. Cady, Yu Cao, Jae-sun Seo, Deliang Fan
2023	—	`conf`	A Time-Memory-based CMOS Vision Sensor with In-Pixel Temporal Derivative Computing for Multi-Mode Image Processing. ESSCIRC Dong-Woo Jee, Seong-Min Ko, Kishore Kasichainula, Injune Yeo, Yu Cao, Jae-sun Seo
2023	J	`jnl`	Abisko: Deep codesign of an architecture for spiking neural networks using novel neuromorphic materials. Int. J. High Perform. Comput. Appl. Jeffrey S. Vetter, Prasanna Date, Farah Fahim, Shruti R. Kulkarni, Petro Maksymovych, A. Alec Talin, Marc González Tallada, Pruek Vanna-Iampikul, Aaron R. Young, David Brooks, Yu Cao, Gu-Yeon Wei, Sung Kyu Lim, Frank Liu, Matthew J. Marinella, Bobby G. Sumpter, Narasinga Rao Miniskar
2023	J	`jnl`	Algorithm-hardware Co-optimization for Energy-efficient Drone Detection on Resource-constrained FPGA. ACM Trans. Reconfigurable Technol. Syst. Han-Sok Suh, Jian Meng, Ty Nguyen, Vijay Kumar, Yu Cao, Jae-sun Seo
2023	—	`conf`	Benchmarking Heterogeneous Integration with 2.5D/3D Interconnect Modeling. ASICON Zhenyu Wang, Jingbo Sun, A. Alper Goksoy, Sumit K. Mandal, Jae-sun Seo, Chaitali Chakrabarti, Ümit Y. Ogras, Vidya A. Chhabria, Yu Cao
2023	A	`conf`	FPGA Acceleration of GCN in Light of the Symmetry of Graph Adjacency Matrix. DATE Gopikrishnan Raveendran Nair, Han-Sok Suh, Mahantesh Halappanavar, Frank Liu, Jae-sun Seo, Yu Cao
2023	C	`conf`	Improving the Efficiency of CMOS Image Sensors through In-Sensor Selective Attention. ISCAS Tianyi Zhang, Kishore Kasichainula, Dong-Woo Jee, Injune Yeo, Yaoxin Zhuo, Baoxin Li, Jae-sun Seo, Yu Cao
2023	J	`jnl`	MNSIM 2.0: A Behavior-Level Modeling Tool for Processing-In-Memory Architectures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Zhenhua Zhu, Hanbo Sun, Tongxin Xie, Yu Zhu, Guohao Dai, Lixue Xia, Dimin Niu, Xiaoming Chen, Xiaobo Sharon Hu, Yu Cao, Yuan Xie, Huazhong Yang, Yu Wang
2023	J	`jnl`	Patch-based Selection and Refinement for Early Object Detection. CoRR Tianyi Zhang, Kishore Kasichainula, Yaoxin Zhuo, Baoxin Li, Jae-sun Seo, Yu Cao
2023	J	`jnl`	SpikeSim: An End-to-End Compute-in-Memory Hardware Evaluation Tool for Benchmarking Spiking Neural Networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Abhishek Moitra, Abhiroop Bhattacharjee, Runcong Kuang, Gokul Krishnan, Yu Cao, Priyadarshini Panda
2023	J	`jnl`	Transformer-based Selective Super-Resolution for Efficient Image Refinement. CoRR Tianyi Zhang, Kishore Kasichainula, Yaoxin Zhuo, Baoxin Li, Jae-sun Seo, Yu Cao
2022	A	`conf`	Big-Little Chiplets for In-Memory Acceleration of DNNs: A Scalable Heterogeneous Architecture. ICCAD Gokul Krishnan, A. Alper Goksoy, Sumit K. Mandal, Zhenyu Wang, Chaitali Chakrabarti, Jae-sun Seo, Ümit Y. Ogras, Yu Cao
2022	J	`jnl`	COIN: Communication-Aware In-Memory Acceleration for Graph Convolutional Networks. CoRR Sumit K. Mandal, Gokul Krishnan, A. Alper Goksoy, Gopikrishnan Ravindran Nair, Yu Cao, Ümit Y. Ogras
2022	J	`jnl`	COIN: Communication-Aware In-Memory Acceleration for Graph Convolutional Networks. IEEE J. Emerg. Sel. Topics Circuits Syst. Sumit K. Mandal, Gokul Krishnan, A. Alper Goksoy, Gopikrishnan Ravindran Nair, Yu Cao, Ümit Y. Ogras
2022	J	`jnl`	Efficient continual learning at the edge with progressive segmented training. Neuromorph. Comput. Eng. Xiaocong Du, Shreyas Kolala Venkataramanaiah, Zheng Li, Han-Sok Suh, Shihui Yin, Gokul Krishnan, Frank Liu, Jae-sun Seo, Yu Cao
2022	J	`jnl`	Exploring Model Stability of Deep Neural Networks for Reliable RRAM-Based In-Memory Acceleration. IEEE Trans. Computers Gokul Krishnan, Li Yang, Jingbo Sun, Jubin Hazra, Xiaocong Du, Maximilian Liehr, Zheng Li, Karsten Beckmann, Rajiv V. Joshi, Nathaniel C. Cady, Deliang Fan, Yu Cao
2022	A*	`conf`	Gradient-Based Novelty Detection Boosted by Self-Supervised Binary Classification. AAAI Jingbo Sun, Li Yang, Jiaxin Zhang, Frank Liu, Mahantesh Halappanavar, Deliang Fan, Yu Cao
2022	J	`jnl`	Hybrid RRAM/SRAM in-Memory Computing for Robust DNN Acceleration. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Gokul Krishnan, Zhenyu Wang, Injune Yeo, Li Yang, Jian Meng, Maximilian Liehr, Rajiv V. Joshi, Nathaniel C. Cady, Deliang Fan, Jae-sun Seo, Yu Cao
2022	J	`jnl`	Impact of On-chip Interconnect on In-memory Acceleration of Deep Neural Networks. ACM J. Emerg. Technol. Comput. Syst. Gokul Krishnan, Sumit K. Mandal, Chaitali Chakrabarti, Jae-sun Seo, Ümit Y. Ogras, Yu Cao
2022	—	`conf`	Spatial-temporal Data Compression of Dynamic Vision Sensor Output with High Pixel-level Saliency using Low-precision Sparse Autoencoder. IEEECONF Ahmed Hassan, Jian Meng, Yu Cao, Jae-sun Seo
2022	J	`jnl`	SpikeSim: An end-to-end Compute-in-Memory Hardware Evaluation Tool for Benchmarking Spiking Neural Networks. CoRR Abhishek Moitra, Abhiroop Bhattacharjee, Runcong Kuang, Gokul Krishnan, Yu Cao, Priyadarshini Panda
2022	A	`conf`	XST: A Crossbar Column-wise Sparse Training for Efficient Continual Learning. DATE Fan Zhang, Li Yang, Jian Meng, Jae-sun Seo, Yu Cao, Deliang Fan
2021	—	`conf`	Algorithm-Hardware Co-Optimization for Energy-Efficient Drone Detection on Resource-Constrained FPGA. FPT Han-Sok Suh, Jian Meng, Ty Nguyen, Shreyas K. Venkataramanaiah, Vijay Kumar, Yu Cao, Jae-sun Seo
2021	C	`conf`	Alternate Model Growth and Pruning for Efficient Training of Recommendation Systems. ICMLA Xiaocong Du, Bhargav Bhushanam, Jiecao Yu, Dhruv Choudhary, Tianxiang Gao, Sherman Wong, Louis Feng, Jongsoo Park, Yu Cao, Arun Kejariwal
2021	J	`jnl`	Alternate Model Growth and Pruning for Efficient Training of Recommendation Systems. CoRR Xiaocong Du, Bhargav Bhushanam, Jiecao Yu, Dhruv Choudhary, Tianxiang Gao, Sherman Wong, Louis Feng, Jongsoo Park, Yu Cao, Arun Kejariwal
2021	B	`conf`	End-to-End FPGA-based Object Detection Using Pipelined CNN and Non-Maximum Suppression. FPL Anupreetham Anupreetham, Mohamed Ibrahim, Mathew Hall, Andrew Boutros, Ajay Kuzhively, Abinash Mohanty, Eriko Nurvitadhi, Vaughn Betz, Yu Cao, Jae-sun Seo
2021	B	`conf`	Evolutionary NAS in Light of Model Stability for Accurate Continual Learning. IJCNN Xiaocong Du, Zheng Li, Jingbo Sun, Frank Liu, Yu Cao
2021	J	`jnl`	Gradient-based Novelty Detection Boosted by Self-supervised Binary Classification. CoRR Jingbo Sun, Li Yang, Jiaxin Zhang, Frank Liu, Mahantesh Halappanavar, Deliang Fan, Yu Cao
2021	J	`jnl`	Impact of On-Chip Interconnect on In-Memory Acceleration of Deep Neural Networks. CoRR Gokul Krishnan, Sumit K. Mandal, Chaitali Chakrabarti, Jae-sun Seo, Ümit Y. Ogras, Yu Cao
2021	J	`jnl`	RA-BNN: Constructing Robust & Accurate Binary Neural Network to Simultaneously Defend Adversarial Bit-Flip Attack and Improve Accuracy. CoRR Adnan Siraj Rakin, Li Yang, Jingtao Li, Fan Yao, Chaitali Chakrabarti, Yu Cao, Jae-sun Seo, Deliang Fan
2021	—	`conf`	Robust RRAM-based In-Memory Computing in Light of Model Stability. IRPS Gokul Krishnan, Jingbo Sun, Jubin Hazra, Xiaocong Du, Maximilian Liehr, Zheng Li, Karsten Beckmann, Rajiv V. Joshi, Nathaniel C. Cady, Yu Cao
2021	J	`jnl`	SIAM: Chiplet-based Scalable In-Memory Acceleration with Mesh for Deep Neural Networks. CoRR Gokul Krishnan, Sumit K. Mandal, Manvitha Pannala, Chaitali Chakrabarti, Jae-sun Seo, Ümit Y. Ogras, Yu Cao
2021	J	`jnl`	SIAM: Chiplet-based Scalable In-Memory Acceleration with Mesh for Deep Neural Networks. ACM Trans. Embed. Comput. Syst. Gokul Krishnan, Sumit K. Mandal, Manvitha Pannala, Chaitali Chakrabarti, Jae-sun Seo, Ümit Y. Ogras, Yu Cao
2021	A	`conf`	SWIFT: Small-World-based Structural Pruning to Accelerate DNN Inference on FPGA. FPGA Yufei Ma, Gokul Krishnan, Yu Cao, Le Ye, Ru Huang
2021	—	`conf`	Self-supervised Novelty Detection for Continual Learning: A Gradient-Based Approach Boosted by Binary Classification. CSSL Jingbo Sun, Li Yang, Jiaxin Zhang, Frank Liu, Mahantesh Halappanavar, Deliang Fan, Yu Cao
2021	—	`conf`	System-Level Benchmarking of Chiplet-based IMC Architectures for Deep Neural Network Acceleration. ASICON Gokul Krishnan, Sumit K. Mandal, Chaitali Chakrabarti, Jae-sun Seo, Ümit Y. Ogras, Yu Cao
2020	J	`jnl`	A Latency-Optimized Reconfigurable NoC for In-Memory Acceleration of DNNs. IEEE J. Emerg. Sel. Topics Circuits Syst. Sumit K. Mandal, Gokul Krishnan, Chaitali Chakrabarti, Jae-sun Seo, Yu Cao, Ümit Y. Ogras
2020	J	`jnl`	A Progressive Sub-Network Searching Framework for Dynamic Inference. CoRR Li Yang, Zhezhi He, Yu Cao, Deliang Fan
2020	A*	`conf`	Accurate Inference with Inaccurate RRAM Devices: Statistical Data, Model Transfer, and On-line Adaptation. DAC Gouranga Charan, Jubin Hazra, Karsten Beckmann, Xiaocong Du, Gokul Krishnan, Rajiv V. Joshi, Nathaniel C. Cady, Yu Cao
2020	J	`jnl`	Automatic Compilation of Diverse CNNs Onto High-Performance FPGA Accelerators. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yufei Ma, Yu Cao, Sarma B. K. Vrudhula, Jae-sun Seo
2020	C	`conf`	DAT-RNN: Trajectory Prediction with Diverse Attention. ICMLA Zheng Li, Xiaocong Du, Yu Cao
2020	—	`conf`	Deep Neural Network Training Accelerator Designs in ASIC and FPGA. ISOCC Shreyas K. Venkataramanaiah, Shihui Yin, Yu Cao, Jae-sun Seo
2020	A*	`conf`	Efficient and Modularized Training on FPGA for Real-time Applications. IJCAI Shreyas Kolala Venkataramanaiah, Xiaocong Du, Zheng Li, Shihui Yin, Yu Cao, Jae-sun Seo
2020	A	`conf`	FPGA-based Low-Batch Training Accelerator for Modern CNNs Featuring High Bandwidth Memory. ICCAD Shreyas K. Venkataramanaiah, Han-Sok Suh, Shihui Yin, Eriko Nurvitadhi, Aravind Dasu, Yu Cao, Jae-sun Seo
2020	A	`conf`	GAR: Graph Assisted Reasoning for Object Detection. WACV Zheng Li, Xiaocong Du, Yu Cao
2020	J	`jnl`	Interconnect-Aware Area and Energy Optimization for In-Memory Acceleration of DNNs. IEEE Des. Test Gokul Krishnan, Sumit K. Mandal, Chaitali Chakrabarti, Jae-sun Seo, Ümit Y. Ogras, Yu Cao
2020	—	`conf`	MNSIM 2.0: A Behavior-Level Modeling Tool for Memristor-based Neuromorphic Computing Systems. ACM Great Lakes Symposium on VLSI Zhenhua Zhu, Hanbo Sun, Kaizhong Qiu, Lixue Xia, Gokul Krishnan, Guohao Dai, Dimin Niu, Xiaoming Chen, Xiaobo Sharon Hu, Yu Cao, Yuan Xie, Yu Wang, Huazhong Yang
2020	—	`conf`	Noise-based Selection of Robust Inherited Model for Accurate Continual Learning. CVPR Workshops Xiaocong Du, Zheng Li, Jae-sun Seo, Frank Liu, Yu Cao
2020	A*	`conf`	Non-uniform DNN Structured Subnets Sampling for Dynamic Inference. DAC Li Yang, Zhezhi He, Yu Cao, Deliang Fan
2020	B	`conf`	Online Knowledge Acquisition with the Selective Inherited Model. IJCNN Xiaocong Du, Shreyas Kolala Venkataramanaiah, Zheng Li, Jae-sun Seo, Frank Liu, Yu Cao
2020	J	`jnl`	Performance Modeling for CNN Inference Accelerators on FPGA. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yufei Ma, Yu Cao, Sarma B. K. Vrudhula, Jae-sun Seo
2019	J	`jnl`	A 1.06- $\mu$ W Smart ECG Processor in 65-nm CMOS for Real-Time Biometric Authentication and Personal Cardiac Monitoring. IEEE J. Solid State Circuits Shihui Yin, Minkyu Kim, Deepak Kadetotad, Yang Liu, ChiSung Bae, Sang Joon Kim, Yu Cao, Jae-sun Seo
2019	J	`jnl`	A Real-Time 17-Scale Object Detection Accelerator With Adaptive 2000-Stage Classification in 65 nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. Minkyu Kim, Abinash Mohanty, Deepak Kadetotad, Luning Wei, Xiaofei He, Yu Cao, Jae-sun Seo
2019	B	`conf`	Automatic Compiler Based FPGA Accelerator for CNN Training. FPL Shreyas Kolala Venkataramanaiah, Yufei Ma, Shihui Yin, Eriko Nurvitadhi, Aravind Dasu, Yu Cao, Jae-sun Seo
2019	J	`jnl`	Automatic Compiler Based FPGA Accelerator for CNN Training. CoRR Shreyas Kolala Venkataramanaiah, Yufei Ma, Shihui Yin, Eriko Nurvitadhi, Aravind Dasu, Yu Cao, Jae-sun Seo
2019	J	`jnl`	CGaP: Continuous Growth and Pruning for Efficient Deep Learning. CoRR Xiaocong Du, Zheng Li, Yu Cao
2019	J	`jnl`	Efficient Network Construction Through Structural Plasticity. IEEE J. Emerg. Sel. Topics Circuits Syst. Xiaocong Du, Zheng Li, Yufei Ma, Yu Cao
2019	J	`jnl`	Efficient Network Construction through Structural Plasticity. CoRR Xiaocong Du, Zheng Li, Yufei Ma, Yu Cao
2019	J	`jnl`	Guest Editors' Introduction to the Special Section on Hardware and Algorithms for Energy-Constrained On-chip Machine Learning. ACM J. Emerg. Technol. Comput. Syst. Jae-sun Seo, Yu Cao, Xin Li, Paul N. Whatmough
2019	J	`jnl`	Guest Editors' Introduction: Hardware and Algorithms for Energy-Constrained On-Chip Machine Learning (Part 2). ACM J. Emerg. Technol. Comput. Syst. Jae-sun Seo, Yu Cao, Xin Li, Paul N. Whatmough
2019	J	`jnl`	Single-Net Continual Learning with Progressive Segmented Training (PST). CoRR Xiaocong Du, Gouranga Charan, Frank Liu, Yu Cao
2019	C	`conf`	Single-Net Continual Learning with Progressive Segmented Training. ICMLA Xiaocong Du, Gouranga Charan, Frank Liu, Yu Cao
2019	J	`jnl`	Structural Pruning in Deep Neural Networks: A Small-World Approach. CoRR Gokul Krishnan, Xiaocong Du, Yu Cao
2019	J	`jnl`	Towards Efficient Neural Networks On-a-chip: Joint Hardware-Algorithm Approaches. CoRR Xiaocong Du, Gokul Krishnan, Abinash Mohanty, Zheng Li, Gouranga Charan, Yu Cao
2018	J	`jnl`	ALAMO: FPGA acceleration of deep learning algorithms with a modularized RTL compiler. Integr. Yufei Ma, Naveen Suda, Yu Cao, Sarma B. K. Vrudhula, Jae-sun Seo
2018	—	`conf`	Accelerated BTI degradation under stochastic TDDB effect. IRPS Devyani Patra, Ahmed Kamal Reza, Mehdi Katoozi, Ethan H. Cannon, Kaushik Roy, Yu Cao
2018	J	`jnl`	Adaptive accelerated aging for 28 nm HKMG technology. Microelectron. Reliab. Devyani Patra, Ahmed Kamal Reza, Mohammad Khaled Hassan, Mehdi Katoozi, Ethan H. Cannon, Kaushik Roy, Yu Cao
2018	A	`conf`	Algorithm-hardware co-design of single shot detector for fast object detection on FPGAs. ICCAD Yufei Ma, Tu Zheng, Yu Cao, Sarma B. K. Vrudhula, Jae-sun Seo
2018	—	`conf`	Compact modeling and simulation of accelerated circuit aging. CICC Devyani Patra, Jiayang Zhang, Runsheng Wang, Mehdi Katoozi, Ethan H. Cannon, Ru Huang, Yu Cao
2018	—	`conf`	Generative Sensing: Transforming Unreliable Sensor Data for Reliable Recognition. MIPR Lina J. Karam, Tejas S. Borkar, Yu Cao, Junseok Chae
2018	J	`jnl`	Generative Sensing: Transforming Unreliable Sensor Data for Reliable Recognition. CoRR Lina J. Karam, Tejas S. Borkar, Yu Cao, Junseok Chae
2018	J	`jnl`	Guest Editors' Introduction: Frontiers of Hardware and Algorithms for On-chip Learning. ACM J. Emerg. Technol. Comput. Syst. Yu Cao, Xin Li, Jae-sun Seo, Ganesh Dasika
2018	J	`jnl`	Large-Scale Neuromorphic Spiking Array Processors: A quest to mimic the brain. CoRR Chetan Singh Thakur, Jamal Molin, Gert Cauwenberghs, Giacomo Indiveri, Kundan Kumar, Ning Qiao, Johannes Schemmel, Runchun Wang, Elisabetta Chicca, Jennifer Olson Hasler, Jae-sun Seo, Shimeng Yu, Yu Cao, André van Schaik, Ralph Etienne-Cummings
2018	J	`jnl`	MNSIM: Simulation Platform for Memristor-Based Neuromorphic Computing System. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Lixue Xia, Boxun Li, Tianqi Tang, Peng Gu, Pai-Yu Chen, Shimeng Yu, Yu Cao, Yu Wang, Yuan Xie, Huazhong Yang
2018	J	`jnl`	Optimizing the Convolution Operation to Accelerate Deep Neural Networks on FPGA. IEEE Trans. Very Large Scale Integr. Syst. Yufei Ma, Yu Cao, Sarma B. K. Vrudhula, Jae-sun Seo
2018	J	`jnl`	Power, Performance, and Area Benefit of Monolithic 3D ICs for On-Chip Deep Neural Networks Targeting Speech Recognition. ACM J. Emerg. Technol. Comput. Syst. Kyungwook Chang, Deepak Kadetotad, Yu Cao, Jae-sun Seo, Sung Kyu Lim
2018	J	`jnl`	Process Scalability of Pulse-Based Circuits for Analog Image Convolution. IEEE Trans. Circuits Syst. I Regul. Pap. Robert D'Angelo, Xiaocong Du, Christopher D. Salthouse, Brent Hollosi, Geremy Freifeld, Wes Uy, Haiyao Huang, Nhut Tran, Armand Chery, Jae-sun Seo, Yu Cao, Dorothy C. Poppe, Sameer R. Sonkusale
2018	Misc	`conf`	Towards a Wearable Cough Detector Based on Neural Networks. ICASSP Prad Kadambi, Abinash Mohanty, Hao Ren, Jaclyn Smith, Kevin McGuinnes, Kimberly Holt, Armin Furtwaengler, Roberto Slepetys, Zheng Yang, Jae-sun Seo, Junseok Chae, Yu Cao, Visar Berisha
2017	—	`conf`	A real-time 17-scale object detection accelerator with adaptive 2000-stage classification in 65nm CMOS. ASP-DAC Minkyu Kim, Abinash Mohanty, Deepak Kadetotad, Naveen Suda, Luning Wei, Pooja Saseendran, Xiaofei He, Yu Cao, Jae-sun Seo
2017	C	`conf`	A real-time 17-scale object detection accelerator with adaptive 2000-stage classification in 65nm CMOS. ISCAS Minkyu Kim, Abinash Mohanty, Deepak Kadetotad, Naveen Suda, Luning Wei, Pooja Saseendran, Xiaofei He, Yu Cao, Jae-sun Seo
2017	J	`jnl`	Algorithm and Hardware Design of Discrete-Time Spiking Neural Networks Based on Back Propagation with Binary Activations. CoRR Shihui Yin, Shreyas K. Venkataramanaiah, Gregory K. Chen, Ram Krishnamurthy, Yu Cao, Chaitali Chakrabarti, Jae-sun Seo
2017	—	`conf`	Algorithm and hardware design of discrete-time spiking neural networks based on back propagation with binary activations. BioCAS Shihui Yin, Shreyas K. Venkataramanaiah, Gregory K. Chen, Ram Krishnamurthy, Yu Cao, Chaitali Chakrabarti, Jae-sun Seo
2017	B	`conf`	An automatic RTL compiler for high-throughput FPGA implementation of diverse deep convolutional neural networks. FPL Yufei Ma, Yu Cao, Sarma B. K. Vrudhula, Jae-sun Seo
2017	J	`jnl`	Cost-Effective Design Solutions for Enhancing PRAM Reliability and Performance. IEEE Trans. Multi Scale Comput. Syst. Chengen Yang, Manqing Mao, Yu Cao, Chaitali Chakrabarti
2017	C	`conf`	End-to-end scalable FPGA accelerator for deep residual networks. ISCAS Yufei Ma, Minkyu Kim, Yu Cao, Sarma B. K. Vrudhula, Jae-sun Seo
2017	J	`jnl`	Guest Editors' Introduction: Hardware and Algorithms for On-Chip Learning. ACM J. Emerg. Technol. Comput. Syst. Yu Cao, Xin Li, TaeMin Kim, Suyog Gupta
2017	J	`jnl`	Improving efficiency in sparse learning with the feedforward inhibitory motif. Neurocomputing Zihan Xu, Steven Skorheim, Ming Tu, Visar Berisha, Shimeng Yu, Jae-sun Seo, Maxim Bazhenov, Yu Cao
2017	A	`conf`	Monolithic 3D IC designs for low-power deep neural networks targeting speech recognition. ISLPED Kyungwook Chang, Deepak Kadetotad, Yu Cao, Jae-sun Seo, Sung Kyu Lim
2017	A	`conf`	Optimizing Loop Operation and Dataflow in FPGA Acceleration of Deep Convolutional Neural Networks. FPGA Yufei Ma, Yu Cao, Sarma B. K. Vrudhula, Jae-sun Seo
2017	J	`jnl`	RTN in Scaled Transistors for On-Chip Random Seed Generation. IEEE Trans. Very Large Scale Integr. Syst. Abinash Mohanty, Ketul B. Sutaria, Hiromitsu Awano, Takashi Sato, Yu Cao
2016	J	`jnl`	A 65 nm Programmable ANalog Device Array (PANDA) for Analog Circuit Emulation. IEEE Trans. Circuits Syst. I Regul. Pap. Naveen Suda, Jounghyuk Suh, Nagib Hakim, Yu Cao, Bertan Bakkaloglu
2016	A*	`conf`	Bi-Level Rare Temporal Pattern Detection. ICDM Dawei Zhou, Jingrui He, Yu Cao, Jae-sun Seo
2016	A	`conf`	Compact oscillation neuron exploiting metal-insulator-transition for neuromorphic computing. ICCAD Pai-Yu Chen, Jae-sun Seo, Yu Cao, Shimeng Yu
2016	C	`conf`	Design of a reliable RRAM-based PUF for compact hardware security primitives. ISCAS Ayush Shrivastava, Pai-Yu Chen, Yu Cao, Shimeng Yu, Chaitali Chakrabarti
2016	C	`conf`	High-performance face detection with CPU-FPGA acceleration. ISCAS Abinash Mohanty, Naveen Suda, Minkyu Kim, Sarma B. K. Vrudhula, Jae-sun Seo, Yu Cao
2016	A	`conf`	MNSIM: Simulation platform for memristor-based neuromorphic computing system. DATE Lixue Xia, Boxun Li, Tianqi Tang, Peng Gu, Xiling Yin, Wenqin Huangfu, Pai-Yu Chen, Shimeng Yu, Yu Cao, Yu Wang, Yuan Xie, Huazhong Yang
2016	J	`jnl`	Optimizing Latency, Energy, and Reliability of 1T1R ReRAM Through Cross-Layer Techniques. IEEE J. Emerg. Sel. Topics Circuits Syst. Manqing Mao, Yu Cao, Shimeng Yu, Chaitali Chakrabarti
2016	Misc	`conf`	Ranking the parameters of deep neural networks using the fisher information. ICASSP Ming Tu, Visar Berisha, Martin Woolf, Jae-sun Seo, Yu Cao
2016	—	`conf`	Reducing the Model Order of Deep Neural Networks Using Information Theory. ISVLSI Ming Tu, Visar Berisha, Yu Cao, Jae-sun Seo
2016	J	`jnl`	Reducing the Model Order of Deep Neural Networks Using Information Theory. CoRR Ming Tu, Visar Berisha, Yu Cao, Jae-sun Seo
2016	B	`conf`	Scalable and modularized RTL compilation of Convolutional Neural Networks onto FPGA. FPL Yufei Ma, Naveen Suda, Yu Cao, Jae-sun Seo, Sarma B. K. Vrudhula
2016	J	`jnl`	Technological Exploration of RRAM Crossbar Array for Matrix-Vector Multiplication. J. Comput. Sci. Technol. Lixue Xia, Peng Gu, Boxun Li, Tianqi Tang, Xiling Yin, Wenqin Huangfu, Shimeng Yu, Yu Cao, Yu Wang, Huazhong Yang
2016	A	`conf`	Throughput-Optimized OpenCL-based FPGA Accelerator for Large-Scale Convolutional Neural Networks. FPGA Naveen Suda, Vikas Chandra, Ganesh Dasika, Abinash Mohanty, Yufei Ma, Sarma B. K. Vrudhula, Jae-sun Seo, Yu Cao
2015	J	`jnl`	A Finite-Point Method for Efficient Gate Characterization Under Multiple Input Switching. ACM Trans. Design Autom. Electr. Syst. Anupama R. Subramaniam, Janet Roveda, Yu Cao
2015	—	`conf`	Duty cycle shift under static/dynamic aging in 28nm HK-MG technology. IRPS Ketul B. Sutaria, Pengpeng Ren, Abinash Mohanty, Xixiang Feng, Runsheng Wang, Ru Huang, Yu Cao
2015	C	`conf`	Energy-efficient reconstruction of compressively sensed bioelectrical signals with stochastic computing circuits. ICCD Yufei Ma, Minkyu Kim, Yu Cao, Jae-sun Seo, Sarma B. K. Vrudhula
2015	—	`conf`	Exploiting resistive cross-point array for compact design of physical unclonable function. HOST Pai-Yu Chen, Runchen Fang, Rui Liu, Chaitali Chakrabarti, Yu Cao, Shimeng Yu
2015	J	`jnl`	Finite-point method for efficient timing characterization of sequential elements. Integr. Anupama R. Subramaniam, Janet Roveda, Yu Cao
2015	C	`conf`	Impact of temporal transistor variations on circuit reliability. ISCAS Runsheng Wang, Yu Cao
2015	A	`conf`	Mitigating Effects of Non-ideal Synaptic Device Characteristics for On-chip Learning. ICCAD Pai-Yu Chen, Binbin Lin, I-Ting Wang, Tuo-Hung Hou, Jieping Ye, Sarma B. K. Vrudhula, Jae-sun Seo, Yu Cao, Shimeng Yu
2015	—	`conf`	On-chip Sparse Learning with Resistive Cross-point Array Architecture. ACM Great Lakes Symposium on VLSI Shimeng Yu, Yu Cao
2015	C	`conf`	Optimizing latency, energy, and reliability of 1T1R ReRAM through appropriate voltage settings. ICCD Manqing Mao, Yu Cao, Shimeng Yu, Chaitali Chakrabarti
2015	J	`jnl`	Parallel Architecture With Resistive Crosspoint Array for Dictionary Learning Acceleration. IEEE J. Emerg. Sel. Topics Circuits Syst. Deepak Kadetotad, Zihan Xu, Abinash Mohanty, Pai-Yu Chen, Binbin Lin, Jieping Ye, Sarma B. K. Vrudhula, Shimeng Yu, Yu Cao, Jae-sun Seo
2015	—	`conf`	Programming strategies to improve energy efficiency and reliability of ReRAM memory systems. SiPS Manqing Mao, Yu Cao, Shimeng Yu, Chaitali Chakrabarti
2015	—	`conf`	Technological exploration of RRAM crossbar array for matrix-vector multiplication. ASP-DAC Peng Gu, Boxun Li, Tianqi Tang, Shimeng Yu, Yu Cao, Yu Wang, Huazhong Yang
2015	A	`conf`	Technology-design co-optimization of resistive cross-point array for accelerating learning algorithms on chip. DATE Pai-Yu Chen, Deepak Kadetotad, Zihan Xu, Abinash Mohanty, Binbin Lin, Jieping Ye, Sarma B. K. Vrudhula, Jae-sun Seo, Yu Cao, Shimeng Yu
2014	J	`jnl`	A Low Cost Multi-Tiered Approach to Improving the Reliability of Multi-Level Cell Pram. J. Signal Process. Syst. Chengen Yang, Yunus Emre, Zihan Xu, Hsing Min Chen, Yu Cao, Chaitali Chakrabarti
2014	A*	`conf`	BTI-Induced Aging under Random Stress Waveforms: Modeling, Simulation and Silicon Validation. DAC Ketul Sutaria, Athul Ramkumar, Rongjun Zhu, Renju Rajveev, Yao Ma, Yu Cao
2014	J	`jnl`	Cross-Layer Modeling and Simulation of Circuit Reliability. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yu Cao, Jyothi Velamala, Ketul Sutaria, Mike Shuo-Wei Chen, Jonathan Ahlbin, Ivan Sanchez Esqueda, Michael Bajura, Michael Fritze
2014	—	`conf`	Low cost ECC schemes for improving the reliability of DRAM+PRAMMAIN memory systems. SiPS Manqing Mao, Chengen Yang, Zihan Xu, Yu Cao, Chaitali Chakrabarti
2014	—	`conf`	Neurophysics-inspired parallel architecture with resistive crosspoint array for dictionary learning. BioCAS Deepak Kadetotad, Zihan Xu, Abinash Mohanty, Pai-Yu Chen, Binbin Lin, Jieping Ye, Sarma B. K. Vrudhula, Shimeng Yu, Yu Cao, Jae-sun Seo
2014	—	`conf`	Parallel Programming of Resistive Cross-point Array for Synaptic Plasticity. BICA Zihan Xu, Abinash Mohanty, Pai-Yu Chen, Deepak Kadetotad, Binbin Lin, Jieping Ye, Sarma B. K. Vrudhula, Shimeng Yu, Jae-sun Seo, Yu Cao
2014	—	`conf`	Statistical analysis of random telegraph noise in digital circuits. ASP-DAC Xiaoming Chen, Yu Wang, Yu Cao, Huazhong Yang
2014	J	`jnl`	The Stochastic Loss of Spikes in Spiking Neural P Systems: Design and Implementation of Reliable Arithmetic Circuits. Fundam. Informaticae Zihan Xu, Matteo Cavaliere, Pei An, Sarma B. K. Vrudhula, Yu Cao
2014	—	`conf`	Where is the Achilles Heel under Circuit Aging. ISVLSI Ketul Sutaria, Athul Ramkumar, Rongjun Zhu, Yu Cao
2013	—	`conf`	ACE: A robust variability and aging sensor for high-k/metal gate SoC. ESSDERC Min Chen, Vijay Reddy, Srikanth Krishnan, Jay Ondrusek, Yu Cao
2013	J	`jnl`	Assessment of Circuit Optimization Techniques Under NBTI. IEEE Des. Test Xiaoming Chen, Yu Wang, Huazhong Yang, Yuan Xie, Yu Cao
2013	—	`conf`	Compact modeling of STT-MTJ for SPICE simulation. ESSDERC Zihan Xu, Ketul Sutaria, Chengen Yang, Chaitali Chakrabarti, Yu Cao
2013	J	`jnl`	Evaluation and mitigation of performance degradation under random telegraph noise for digital circuits. IET Circuits Devices Syst. Xiaoming Chen, Hong Luo, Yu Wang, Yu Cao, Yuan Xie, Yuchun Ma, Huazhong Yang
2013	J	`jnl`	NBTI-aware circuit node criticality computation. ACM J. Emerg. Technol. Comput. Syst. Shengqi Yang, Wenping Wang, Mark Hagan, Wei Zhang, Pallav Gupta, Yu Cao
2013	J	`jnl`	Programmable ANalog Device Array (PANDA): A Methodology for Transistor-Level Analog Emulation. IEEE Trans. Circuits Syst. I Regul. Pap. Jounghyuk Suh, Naveen Suda, Cheng Xu, Nagib Hakim, Yu Cao, Bertan Bakkaloglu
2012	J	`jnl`	A self-tuning design methodology for power-efficient multi-core systems. ACM Trans. Design Autom. Electr. Syst. Jin Sun, Rui Zheng, Jyothi Velamala, Yu Cao, Roman L. Lysecky, Karthik Shankar, Janet Meiling Wang Roveda
2012	—	`conf`	An analytical approach to efficient circuit variability analysis in scaled CMOS design. ISQED Samatha Gummalla, Anupama R. Subramaniam, Yu Cao, Chaitali Chakrabarti
2012	J	`jnl`	Asymmetric Aging and Workload Sensitive Bias Temperature Instability Sensors. IEEE Des. Test Comput. Min Chen, Vijay Reddy, Srikanth Krishnan, Venkatesh Srinivasan, Yu Cao
2012	A	`conf`	Design benchmarking to 7nm with FinFET predictive technology models. ISLPED Saurabh Sinha, Brian Cline, Greg Yeric, Vikas Chandra, Yu Cao
2012	—	`conf`	Enhancing the Reliability of STT-RAM through Circuit and System Level Techniques. SiPS Yunus Emre, Chengen Yang, Ketul Sutaria, Yu Cao, Chaitali Chakrabarti
2012	A*	`conf`	Exploring sub-20nm FinFET design with predictive technology models. DAC Saurabh Sinha, Greg Yeric, Vikas Chandra, Brian Cline, Yu Cao
2012	C	`conf`	Hierarchical modeling of Phase Change memory for reliable design. ICCD Zihan Xu, Ketul Sutaria, Chengen Yang, Chaitali Chakrabarti, Yu Cao
2012	J	`jnl`	Improving reliability of non-volatile memory technologies through circuit level techniques and error control coding. EURASIP J. Adv. Signal Process. Chengen Yang, Yunus Emre, Yu Cao, Chaitali Chakrabarti
2012	—	`conf`	Multi-Tiered Approach to Improving the Reliability of Multi-Level Cell PRAM. SiPS Chengen Yang, Yunus Emre, Yu Cao, Chaitali Chakrabarti
2012	A*	`conf`	Physics matters: statistical aging prediction under trapping/detrapping. DAC Jyothi Bhaskarr Velamala, Ketul Sutaria, Takashi Sato, Yu Cao
2012	—	`conf`	Statistical aging under dynamic voltage scaling: A logarithmic model approach. CICC Jyothi Velamala, Ketul Sutaria, Hirofumi Shimizu, Hiromitsu Awano, Takashi Sato, Yu Cao
2012	—	`conf`	Temporal Performance Degradation under RTN: Evaluation and Mitigation for Nanoscale Circuits. ISVLSI Hong Luo, Yu Wang, Yu Cao, Yuan Xie, Yuchun Ma, Huazhong Yang
2012	J	`jnl`	The potential of Fe-FET for robust design under variations: A compact modeling study. Microelectron. J. Chi-Chao Wang, Yun Ye, Yu Cao
2012	J	`jnl`	Variation-Aware Supply Voltage Assignment for Simultaneous Power and Aging Optimization. IEEE Trans. Very Large Scale Integr. Syst. Xiaoming Chen, Yu Wang, Yu Cao, Yuchun Ma, Huazhong Yang
2011	—	`conf`	A workload-aware neuromorphic controller for dynamic power and thermal management. AHS Saurabh Sinha, Jounghyuk Suh, Bertan Bakkaloglu, Yu Cao
2011	—	`conf`	Circuit-level delay modeling considering both TDDB and NBTI. ISQED Hong Luo, Xiaoming Chen, Jyothi Velamala, Yu Wang, Yu Cao, Vikas Chandra, Yuchun Ma, Huazhong Yang
2011	A*	`conf`	Design sensitivity of single event transients in scaled logic circuits. DAC Jyothi Velamala, Robert LiVolsi, Myra Torres, Yu Cao
2011	A	`conf`	Failure diagnosis of asymmetric aging under NBTI. ICCAD Jyothi Bhaskarr Velamala, Venkatesa Ravi, Yu Cao
2011	J	`jnl`	Leakage Power and Circuit Aging Cooptimization by Gate Replacement Techniques. IEEE Trans. Very Large Scale Integr. Syst. Yu Wang, Xiaoming Chen, Wenping Wang, Yu Cao, Yuan Xie, Huazhong Yang
2011	—	`book`	Predictive Technology Model for Robust Nanoelectronic Design Yu Cao
2011	A*	`conf`	Programmable analog device array (PANDA): a platform for transistor-level analog reconfigurability. DAC Rui Zheng, Jounghyuk Suh, Cheng Xu, Nagib Hakim, Bertan Bakkaloglu, Yu Cao
2011	J	`jnl`	Self-Tuning for Maximized Lifetime Energy-Efficiency in the Presence of Circuit Aging. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Evelyn Mintarno, Joëlle Skaf, Rui Zheng, Jyothi Velamala, Yu Cao, Stephen P. Boyd, Robert W. Dutton, Subhasish Mitra
2011	J	`jnl`	Statistical Modeling and Simulation of Threshold Variation Under Random Dopant Fluctuations and Line-Edge Roughness. IEEE Trans. Very Large Scale Integr. Syst. Yun Ye, Frank Liu, Min Chen, Sani R. Nassif, Yu Cao
2011	J	`jnl`	Workload-Aware Neuromorphic Design of the Power Controller. IEEE J. Emerg. Sel. Topics Circuits Syst. Saurabh Sinha, Jounghyuk Suh, Bertan Bakkaloglu, Yu Cao
2010	A	`conf`	A resilience roadmap. DATE Sani R. Nassif, Nikil Mehta, Yu Cao
2010	A	`conf`	A self-evolving design methodology for power efficient multi-core systems. ICCAD Jin Sun, Rui Zheng, Jyothi Velamala, Yu Cao, Roman L. Lysecky, Karthik Shankar, Janet Meiling Wang Roveda
2010	J	`jnl`	Guest Editors' Introduction: Compact Variability Modeling in Scaled CMOS Design. IEEE Des. Test Comput. Yu Cao, Frank Liu
2010	A*	`conf`	In-situ characterization and extraction of SRAM variability. DAC Srivatsan Chellappa, Jia Ni, Xiaoyin Yao, Nathan D. Hindman, Jyothi Velamala, Min Chen, Yu Cao, Lawrence T. Clark
2010	J	`jnl`	Modeling and Analysis of the Nonrectangular Gate Effect for Postlithography Circuit Simulation. IEEE Trans. Very Large Scale Integr. Syst. Ritu Singhal, Asha Balijepalli, Anupama R. Subramaniam, Chi-Chao Wang, Frank Liu, Sani R. Nassif, Yu Cao
2010	A	`conf`	Optimized self-tuning for circuit aging. DATE Evelyn Mintarno, Joëlle Skaf, Rui Zheng, Jyothi Velamala, Yu Cao, Stephen P. Boyd, Robert W. Dutton, Subhasish Mitra
2010	A	`conf`	Simulation of random telegraph Noise with 2-stage equivalent circuit. ICCAD Yun Ye, Chi-Chao Wang, Yu Cao
2010	J	`jnl`	The Impact of NBTI Effect on Combinational Circuit: Modeling, Simulation, and Analysis. IEEE Trans. Very Large Scale Integr. Syst. Wenping Wang, Shengqi Yang, Sarvesh Bhardwaj, Sarma B. K. Vrudhula, Frank Liu, Yu Cao
2010	A	`conf`	Workload-adaptive process tuning strategy for power-efficient multi-core processors. ISLPED Jungseob Lee, Chi-Chao Wang, Hamid Reza Ghasemi, Lloyd Bircher, Yu Cao, Nam Sung Kim
2010	A	`conf`	Workload-aware neuromorphic design of low-power supply voltage controller. ISLPED Saurabh Sinha, Jounghyuk Suh, Bertan Bakkaloglu, Yu Cao
2009	—	`conf`	A framework for estimating NBTI degradation of microarchitectural components. ASP-DAC Michael DeBole, Krishnan Ramakrishnan, Varsha Balakrishnan, Wenping Wang, Hong Luo, Yu Wang, Yuan Xie, Yu Cao, Narayanan Vijaykrishnan
2009	—	`conf`	Circuit aging prediction for low-power operation. CICC Rui Zheng, Jyothi Velamala, Vijay Reddy, Varsha Balakrishnan, Evelyn Mintarno, Subhasish Mitra, Srikanth Krishnan, Yu Cao
2009	J	`jnl`	Compact modeling of a PD SOI MESFET for wide temperature designs. Microelectron. J. Asha Balijepalli, Joseph Ervin, William Lepkowski, Yu Cao, Trevor J. Thornton
2009	C	`conf`	Enabling resonant clock distribution with scaled on-chip magnetic inductors. ICCD Saurabh Sinha, Wei Xu, Jyothi Bhaskarr Velamala, Tawab Dastagir, Bertan Bakkaloglu, Hongbin Yu, Yu Cao
2009	J	`jnl`	Finite-Point-Based Transistor Model: A New Approach to Fast Circuit Simulation. IEEE Trans. Very Large Scale Integr. Syst. Min Chen, Wei Zhao, Frank Liu, Yu Cao
2009	A	`conf`	Gate replacement techniques for simultaneous leakage and aging optimization. DATE Yu Wang, Xiaoming Chen, Wenping Wang, Yu Cao, Yuan Xie, Huazhong Yang
2009	J	`jnl`	Guest Editors' Introduction: Reliability Challenges in Nano-CMOS Design. IEEE Des. Test Comput. Yu Cao, Jim Tschanz, Pradip Bose
2009	A	`conf`	Modeling of layout-dependent stress effect in CMOS design. ICCAD Chi-Chao Wang, Wei Zhao, Frank Liu, Min Chen, Yu Cao
2009	—	`conf`	On the efficacy of input Vector Control to mitigate NBTI effects and leakage power. ISQED Yu Wang, Xiaoming Chen, Wenping Wang, Varsha Balakrishnan, Yu Cao, Yuan Xie, Huazhong Yang
2009	—	`conf`	Pathfinding for 22nm CMOS designs using Predictive Technology Models. CICC Xia Li, Wei Zhao, Yu Cao, Zhi Zhu, Jooyoung Song, David Bang, Chi-Chao Wang, Seung-Hyuk Kang, Joseph Wang, Matt Nowak, Nick Yu
2009	J	`jnl`	The Predictive Technology Model in the Late Silicon Era and Beyond. Found. Trends Electron. Des. Autom. Yu Cao, Asha Balijepalli, Saurabh Sinha, Chi-Chao Wang, Wenping Wang, Wei Zhao
2009	A*	`conf`	Variability analysis under layout pattern-dependent rapid-thermal annealing process. DAC Yun Ye, Frank Liu, Min Chen, Yu Cao
2009	A	`conf`	Variation-aware supply voltage assignment for minimizing circuit degradation and leakage. ISLPED Xiaoming Chen, Yu Wang, Yu Cao, Yuchun Ma, Huazhong Yang
2008	—	`conf`	A Simplified Model of Carbon Nanotube Transistor with Applications to Analog and Digital Design. ISQED Saurabh Sinha, Asha Balijepalli, Yu Cao
2008	J	`jnl`	Digital Circuit Design Challenges and Opportunities in the Era of Nanoscale CMOS. Proc. IEEE Benton H. Calhoun, Yu Cao, Xin Li, Ken Mai, Lawrence T. Pileggi, Rob A. Rutenbar, Kenneth L. Shepard
2008	—	`conf`	Finite-Point Gate Model for Fast Timing and Power Analysis. ISQED Dinesh Ganesan, Alexander V. Mitev, Janet Meiling Wang, Yu Cao
2008	—	`conf`	Node Criticality Computation for Circuit Timing Analysis and Optimization under NBTI Effect. ISQED Wenping Wang, Shengqi Yang, Yu Cao
2008	A	`conf`	Optimized Circuit Failure Prediction for Aging: Practicality and Promise. ITC Mridul Agarwal, Varsha Balakrishnan, Anshuman Bhuyan, Kyunglok Kim, Bipul C. Paul, Wenping Wang, Bo Yang, Yu Cao, Subhasish Mitra
2008	—	`conf`	Projection-Based Piecewise-Linear Response Surface Modeling for Strongly Nonlinear VLSI Performance Variations. ISQED Xin Li, Yu Cao
2008	J	`jnl`	Scalable model for predicting the effect of negative bias temperature instability for reliable design. IET Circuits Devices Syst. Sarvesh Bhardwaj, Wenping Wang, Rakesh Vattikonda, Yu Cao, Sarma B. K. Vrudhula
2008	A*	`conf`	Statistical modeling and simulation of threshold variation under dopant fluctuations and line-edge roughness. DAC Yun Ye, Frank Liu, Sani R. Nassif, Yu Cao
2008	—	`conf`	Statistical prediction of circuit aging under process variations. CICC Wenping Wang, Vijay Reddy, Bo Yang, Varsha Balakrishnan, Srikanth Krishnan, Yu Cao
2007	—	`conf`	A New Simulation Method for NBTI Analysis in SPICE Environment. ISQED Rakesh Vattikonda, Yansheng Luo, Alex Gyure, Xiaoning Qi, Sam C. Lo, Mahmoud Shahram, Yu Cao, Kishore Singhal, Dino Toffolon
2007	A	`conf`	A robust finite-point based gate model considering process variations. ICCAD Alexander V. Mitev, Dinesh Ganesan, Dheepan Shanmugasundaram, Yu Cao, Janet Meiling Wang
2007	—	`conf`	An Integrated Modeling Paradigm of Circuit Reliability for 65nm CMOS Technology. CICC Wenping Wang, Vijay Reddy, Anand T. Krishnan, Rakesh Vattikonda, Srikanth Krishnan, Yu Cao
2007	A	`conf`	An efficient method to identify critical gates under circuit aging. ICCAD Wenping Wang, Zile Wei, Shengqi Yang, Yu Cao
2007	—	`conf`	Compact Modeling of a PD SOI MESFET for Wide Temperature Designs. ISQED Asha Balijepalli, Joseph Ervin, Yu Cao, Trevor Thornton
2007	A	`conf`	Compact modeling of carbon nanotube transistor for early stage process-design exploration. ISLPED Asha Balijepalli, Saurabh Sinha, Yu Cao
2007	A	`conf`	Fast statistical circuit analysis with finite-point based transistor model. DATE Min Chen, Wei Zhao, Frank Liu, Yu Cao
2007	A*	`conf`	Modeling and Analysis of Non-Rectangular Gate for Post-Lithography Circuit Simulation. DAC Ritu Singhal, Asha Balijepalli, Anupama R. Subramaniam, Frank Liu, Sani R. Nassif, Yu Cao
2007	—	`conf`	Optimizing finfet technology for high-speed and low-power design. ACM Great Lakes Symposium on VLSI Tarun Sairam, Wei Zhao, Yu Cao
2007	J	`jnl`	Predictive technology model for nano-CMOS design exploration. ACM J. Emerg. Technol. Comput. Syst. Wei Zhao, Yu Cao
2007	—	`conf`	Rigorous extraction of process variations for 65nm CMOS design. ESSCIRC Wei Zhao, Yu Cao, Frank Liu, Kanak Agarwal, Dhruva Acharyya, Sani R. Nassif, Kevin J. Nowka
2007	A*	`conf`	The Impact of NBTI on the Performance of Combinational and Sequential Circuits. DAC Wenping Wang, Shengqi Yang, Sarvesh Bhardwaj, Rakesh Vattikonda, Sarma B. K. Vrudhula, Frank Liu, Yu Cao
2006	A	`conf`	Analysis and modeling of CD variation for statistical static timing. ICCAD Brian Cline, Kaviraj Chopra, David T. Blaauw, Yu Cao
2006	—	`conf`	Analysis of Pulse Signaling for Low-Power On-Chip Global Bus Design. ISQED Min Chen, Yu Cao
2006	—	`conf`	LOTUS: Leakage Optimization under Timing Uncertainty for Standard-cell designs. ISQED Sarvesh Bhardwaj, Yu Cao, Sarma B. K. Vrudhula
2006	A*	`conf`	Modeling and minimization of PMOS NBTI effect for robust nanometer design. DAC Rakesh Vattikonda, Wenping Wang, Yu Cao
2006	A*	`conf`	Modeling of intra-die process variations for accurate analysis and optimization of nano-scale circuits. DAC Sarvesh Bhardwaj, Sarma B. K. Vrudhula, Praveen Ghanta, Yu Cao
2006	—	`conf`	New Generation of Predictive Technology Model for Sub-45nm Design Exploration. ISQED Wei Zhao, Yu Cao
2006	—	`conf`	Predictive Modeling of the NBTI Effect for Reliable Design. CICC Sarvesh Bhardwaj, Wenping Wang, Rakesh Vattikonda, Yu Cao, Sarma B. K. Vrudhula
2006	—	`conf`	Predictive Technology Model for Nano-CMOS Design Exploration. Nano-Net Yu Cao, Wei Zhao
2006	J	`jnl`	SRAM Cell Optimization for Ultra-Low Power Standby. J. Low Power Electron. Huifang Qin, Rakesh Vattikonda, Thuan Trinh, Yu Cao, Jan M. Rabaey
2006	J	`jnl`	Statistical Leakage Minimization of Digital Circuits Using Gate Sizing, Gate Length Biasing, Threshold Voltage Selection. J. Low Power Electron. Sarvesh Bhardwaj, Yu Cao, Sarma B. K. Vrudhula
2006	—	`conf`	Statistical leakage minimization through joint selection of gate sizes, gate lengths and threshold voltage. ASP-DAC Sarvesh Bhardwaj, Yu Cao, Sarma B. K. Vrudhula
2005	J	`jnl`	Impact of on-chip interconnect frequency-dependent R(f)L(f) on digital and RF design. IEEE Trans. Very Large Scale Integr. Syst. Yu Cao, Xuejue Huang, Dennis Sylvester, Tsu-Jae King, Chenming Hu
2005	—	`conf`	Modeling Within-Die Spatial Correlation Effects for Process-Design Co-Optimization. ISQED Paul Friedberg, Yu Cao, Jason Cain, Ruth Wang, Jan M. Rabaey, Costas J. Spanos
2005	J	`jnl`	Standby supply voltage minimization for deep sub-micron SRAM. Microelectron. J. Huifang Qin, Yu Cao, Dejan Markovic, Andrei Vladimirescu, Jan M. Rabaey
2005	J	`jnl`	Switch-factor based loop RLC modeling for efficient timing analysis. IEEE Trans. Very Large Scale Integr. Syst. Yu Cao, Xiaodong Yang, Xuejue Huang, Dennis Sylvester
2004	—	`conf`	SRAM Leakage Suppression by Minimizing Standby Supply Voltage. ISQED Huifang Qin, Yu Cao, Dejan Markovic, Andrei Vladimirescu, Jan M. Rabaey
2003	J	`jnl`	Bidirectional closed-form transformation between on-chip coupling noise waveforms and interconnect delay-change curves. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Takashi Sato, Yu Cao, Kanak Agarwal, Dennis Sylvester, Chenming Hu
2003	J	`jnl`	Frequency-independent equivalent-circuit model for on-chip spiral inductors. IEEE J. Solid State Circuits Yu Cao, Robert A. Groves, Xuejue Huang, Noah Zamdmer, Jean-Olivier Plouchart, Richard A. Wachnik, Tsu-Jae King, Chenming Hu
2003	J	`jnl`	Improved a priori interconnect predictions and technology extrapolation in the GTX system. IEEE Trans. Very Large Scale Integr. Syst. Yu Cao, Chenming Hu, Xuejue Huang, Andrew B. Kahng, Igor L. Markov, Michael Oliver, Dirk Stroobandt, Dennis Sylvester
2003	J	`jnl`	Loop-based interconnect modeling and optimization approach for multigigahertz clock network design. IEEE J. Solid State Circuits Xuejue Huang, Phillip J. Restle, Thomas J. Bucelot, Yu Cao, Tsu-Jae King, Chenming Hu
2003	A	`conf`	Switch-Factor Based Loop RLC Modeling for Efficient Timing Analysis. ICCAD Yu Cao, Xiaodong Yang, Xuejue Huang, Dennis Sylvester
2002	J	`jnl`	Effective on-chip inductance modeling for multiple signal lines and application to repeater insertion. IEEE Trans. Very Large Scale Integr. Syst. Yu Cao, Xuejue Huang, N. H. Chang, Shen Lin, O. Sam Nakagawa, Weize Xie, Dennis Sylvester, Chenming Hu
2002	—	`conf`	Efficient Generation of Delay Change Curves for Noise-Aware Static Timing Analysis. ASP-DAC/VLSI Design Kanak Agarwal, Yu Cao, Takashi Sato, Dennis Sylvester, Chenming Hu
2002	—	`conf`	Frequency-independent equivalent circuit model for on-chip spiral inductors. CICC Yu Cao, Robert A. Groves, Noah Zamdmer, Jean-Olivier Plouchart, Richard A. Wachnik, Xuejue Huang, Tsu-Jae King, Chenming Hu
2002	—	`conf`	Loop-based interconnect modeling and optimization approach for multi-GHz clock network design. CICC Xuejue Huang, Phillip J. Restle, Thomas J. Bucelot, Yu Cao, Tsu-Jae King
2001	J	`jnl`	Accurate in situ measurement of peak noise and delay change induced by interconnect coupling. IEEE J. Solid State Circuits Takashi Sato, Dennis Sylvester, Yu Cao, Chenming Hu
2001	—	`conf`	Effective On-chip Inductance Modeling for Multiple Signal Lines and Application on Repeater Insertion. ISQED Yu Cao, Xuejue Huang, Chenming Hu, Norman Chang, Shen Lin, O. Sam Nakagawa, Weize Xie
2000	A	`conf`	Effects of Global Interconnect Optimizations on Performance Estimation of Deep Submicron Design. ICCAD Yu Cao, Chenming Hu, Xuejue Huang, Andrew B. Kahng, Sudhakar Muddu, Dirk Stroobandt, Dennis Sylvester
2000	A*	`conf`	GTX: the MARCO GSRC technology extrapolation system. DAC Andrew E. Caldwell, Yu Cao, Andrew B. Kahng, Farinaz Koushanfar, Hua Lu, Igor L. Markov, Michael Oliver, Dirk Stroobandt, Dennis Sylvester
2000	—	`conf`	New paradigm of predictive MOSFET and interconnect modeling for early circuit simulation. CICC Yu Cao, Takashi Sato, Michael Orshansky, Dennis Sylvester, Chenming Hu