| Year | Rank | Type | Title / Venue / Authors |
|---|---|---|---|
| 2024 | J | jnl |
IEEE Trans. Circuits Syst. I Regul. Pap.
|
| 2024 | J | jnl |
An Area-Efficient Low-Jitter Fractional Output Divider With Replica-DTC-Free Background Calibration.
IEEE J. Solid State Circuits
|
| 2021 | — | conf |
ISSCC
|
| 2020 | — | conf |
VLSI-DAT
|
| 2019 | — | conf |
A-SSCC
|
| 2018 | J | jnl |
Comput. Educ.
|
| 2014 | J | jnl |
Comput. Phys. Commun.
|
| 2014 | Misc | conf |
AMIA
|
| 2004 | A | conf |
DATE
|
| 2003 | — | conf |
Asian Test Symposium
|
| 2003 | A | conf |
ITC
|