| Year | Rank | Type | Title / Venue / Authors |
|---|---|---|---|
| 2016 | — | conf |
A-SSCC
|
| 2015 | J | jnl |
Int. J. Distributed Sens. Networks
|
| 2015 | J | jnl |
RFC
|
| 2013 | J | jnl |
J. Appl. Math.
|
| 2013 | B | conf |
AINA
|
| 2012 | C | conf |
ISCAS
|
| 2012 | J | jnl |
An At-Speed Test Technique for High-Speed High-order Adder by a 6.4-GHz 64-bit Domino Adder Example.
IEEE Trans. Circuits Syst. I Regul. Pap.
|
| 2012 | — | conf |
AINA Workshops
|
| 2012 | — | conf |
CASoN
|
| 2012 | — | conf |
AINA Workshops
|
| 2011 | C | conf |
ISCAS
|
| 2011 | C | conf |
ISCAS
|
| 2011 | — | conf |
CICC
|
| 2011 | B | conf |
IWCMC
|
| 2010 | C | conf |
IAS
|
| 2010 | — | conf |
BWCCA
|
| 2008 | J | jnl |
RFC
|
| 2006 | J | jnl |
IEICE Trans. Commun.
|
| 2005 | Misc | conf |
TRIDENTCOM
|
| 2004 | J | jnl |
RFC
|
| 2003 | — | conf |
DISCEX (2)
|
| 2003 | — | conf |
DISCEX (2)
|
| 2002 | — | conf |
DANCE
|