Yu-Shen Yang

16 papers A 6C 2Journal 3Unranked 5
YearRankTypeTitle / Venue / Authors
2014 — conf
Simulation and satisfiability guided counter-example triage for RTL design debugging.
ISQED
Zissis Poulos, Yu-Shen Yang, Andreas G. Veneris, Bao Le
2013 C conf
A failure triage engine based on error trace signature extraction.
IOLTS
Zissis Poulos, Yu-Shen Yang, Andreas G. Veneris
2012 — conf
Automated data analysis techniques for a modern silicon debug environment.
ASP-DAC
Yu-Shen Yang, Andreas G. Veneris, Nicola Nicolici, Masahiro Fujita
2012 J jnl
Automating Data Analysis and Acquisition Setup in a Silicon Debug Environment.
IEEE Trans. Very Large Scale Integr. Syst.
Yu-Shen Yang, Andreas G. Veneris, Nicola Nicolici
2012 A conf
Leveraging reconfigurability to raise productivity in FPGA functional debug.
DATE
Zissis Poulos, Yu-Shen Yang, Jason Helge Anderson, Andreas G. Veneris, Bao Le
2011 J jnl
Automating Logic Transformations With Approximate SPFDs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Yu-Shen Yang, Subarna Sinha, Andreas G. Veneris, Robert K. Brayton
2010 — conf
Automated silicon debug data analysis techniques for a hardware data acquisition environment.
ISQED
Yu-Shen Yang, Brian Keng, Nicola Nicolici, Andreas G. Veneris, Sean Safarpour
2009 A conf
Automated data analysis solutions to silicon debug.
DATE
Yu-Shen Yang, Nicola Nicolici, Andreas G. Veneris
2009 A conf
Sequential logic rectifications with approximate SPFDs.
DATE
Yu-Shen Yang, Subarna Sinha, Andreas G. Veneris, Robert K. Brayton, Duncan Exon Smith
2008 C conf
On the Minimization of Potential Transient Errors and SER in Logic Circuits Using SPFD.
IOLTS
Sobeeh Almukhaizim, Yiorgos Makris, Yu-Shen Yang, Andreas G. Veneris
2007 — conf
Automating Logic Rectification by Approximate SPFDs.
ASP-DAC
Yu-Shen Yang, Subarnarekha Sinha, Andreas G. Veneris, Robert K. Brayton
2006 J jnl
Extraction error modeling and automated model debugging in high-performance custom designs.
IEEE Trans. Very Large Scale Integr. Syst.
Yu-Shen Yang, Andreas G. Veneris, Paul J. Thadikaran, Srikanth Venkataraman
2006 A conf
Seamless Integration of SER in Rewiring-Based Design Space Exploration.
ITC
Sobeeh Almukhaizim, Yiorgos Makris, Yu-Shen Yang, Andreas G. Veneris
2005 A conf
Extraction Error Modeling and Automated Model Debugging in High-Performance Low Power Custom Designs.
DATE
Yu-Shen Yang, Andreas G. Veneris, Paul J. Thadikaran, Srikanth Venkataraman
2003 — conf
Extraction Error Analysis, Diagnosis and Correction in Custom-Made High-Performance Designs.
MTV
Yu-Shen Yang, Jiang Brandon Liu, Paul J. Thadikaran, Andreas G. Veneris
2003 A conf
Extraction Error Diagnosis and Correction in High-Performance Designs.
ITC
Yu-Shen Yang, Jiang Brandon Liu, Paul J. Thadikaran, Andreas G. Veneris