Yu-Liang Chou

19 papers A 2B 1Journal 13Unranked 3
YearRankTypeTitle / Venue / Authors
2025 J jnl
Benchmarking Instance-Centric Counterfactual Algorithms for XAI: From White Box to Black Box.
ACM Comput. Surv.
Catarina Moreira, Yu-Liang Chou, Chihcheng Hsieh, Chun Ouyang, João Pereira, Joaquim Jorge
2022 J jnl
Benchmark Evaluation of Counterfactual Algorithms for XAI: From a White Box to a Black Box.
CoRR
Yu-Liang Chou, Chihcheng Hsieh, Catarina Moreira, Chun Ouyang, Joaquim Jorge, João Madeiras Pereira
2022 J jnl
Counterfactuals and causability in explainable artificial intelligence: Theory, algorithms, and applications.
Inf. Fusion
Yu-Liang Chou, Catarina Moreira, Peter Bruza, Chun Ouyang, Joaquim Jorge
2021 J jnl
Counterfactuals and Causability in Explainable Artificial Intelligence: Theory, Algorithms, and Applications.
CoRR
Yu-Liang Chou, Catarina Moreira, Peter Bruza, Chun Ouyang, Joaquim Jorge
2021 J jnl
LINDA-BN: An interpretable probabilistic approach for demystifying black-box predictive models.
Decis. Support Syst.
Catarina Moreira, Yu-Liang Chou, Mythreyi Velmurugan, Chun Ouyang, Renuka Sindhgatta, Peter Bruza
2020 J jnl
An Interpretable Probabilistic Approach for Demystifying Black-box Predictive Models.
CoRR
Catarina Moreira, Yu-Liang Chou, Mythreyi Velmurugan, Chun Ouyang, Renuka Sindhgatta, Peter Bruza
2014 J jnl
An Energy and Performance Efficient DVFS Scheme for Irregular Parallel Divide-and-Conquer Algorithms on the Intel SCC.
IEEE Comput. Archit. Lett.
Yu-Liang Chou, Shaoshan Liu, Eui-Young Chung, Jean-Luc Gaudiot
2013 J jnl
A hyperscalar dual-core architecture for embedded systems.
Microprocess. Microsystems
Jih-Ching Chiu, Kai-Ming Yang, Yu-Liang Chou
2013 J jnl
A relation-exchanging buffering mechanism for instruction and data streaming.
Comput. Electr. Eng.
Jih-Ching Chiu, Kai-Ming Yang, Yu-Liang Chou, Chih-Kang Wu
2013 — conf
OCP: Offload Co-Processor for energy efficiency in embedded mobile systems.
ASAP
Jie Tang, Chen Liu, Yu-Liang Chou, Shaoshan Liu
2011 J jnl
A Unitable Computing Architecture for Chip Multiprocessors.
Comput. J.
Jih-Ching Chiu, Yu-Liang Chou, Po-Kai Chen, Ding-Siang Su
2010 — conf
A hyperscalar multi-core architecture.
Conf. Computing Frontiers
Jih-Ching Chiu, Yu-Liang Chou, Ding-Siang Su
2010 J jnl
A multi-streaming SIMD multimedia computing engine.
Microprocess. Microsystems
Jih-Ching Chiu, Yu-Liang Chou
2010 B conf
Hyperscalar: A Novel Dynamically Reconfigurable Multi-core Architecture.
ICPP
Jih-Ching Chiu, Yu-Liang Chou, Po-Kai Chen
2010 J jnl
The Basic Block Reassembling Instruction Stream Buffer with LWBTB for X86 ISA.
J. Inf. Sci. Eng.
Jih-Ching Chiu, Yu-Liang Chou, Tseng-Kuei Lin
2009 — conf
A multi-streaming SIMD architecture for multimedia applications.
Conf. Computing Frontiers
Jih-Ching Chiu, Yu-Liang Chou, Hua-Yi Tzeng
2009 A conf
Design of a novel SIMD architecture by fusing operations and registers.
ICS
Jih-Ching Chiu, Kai-Ming Yang, Yu-Liang Chou
2008 A conf
Designs of the basic block reassembling Instruction Stream Buffer for X86 ISA.
ACSAC
Jih-Ching Chiu, Yu-Liang Chou, Ta-Li Yeh, Tseng-Kuei Lin
2008 J jnl
The Multi-context Reconfigurable Processing Unit for Fine-grain Computing.
J. Inf. Sci. Eng.
Jih-Ching Chiu, Yu-Liang Chou, Ren-Bang Lin