Yu-Der Chih

71 papers Journal 25Unranked 46
YearRankTypeTitle / Venue / Authors
2026 — conf
15.4 A 16nm 168Mb Embedded STT-MRAM with 0.0249µm
ISSCC
Po-Hao Lee, Chia-Fu Lee, Hon-Jarn Lin, Cheng-Han Lu, Yen-An Chang, Pranata W. Sanjaya, Chia-Jung Tsen, Kuan-Chun Chen, Ming-Chieh Lin, Chao-Jung Hung, Tan-Li Chou, Chih-Hui Weng, Chia-Yu Wang, J. J. Wu, Harry Chuang, Yih Wang, Yu-Der Chih, Tsung-Yung Jonathan Chang
2026 J jnl
A 3 nm FinFET 125 TOPS/W-29 TFLOPS/W, 90 TOPS/mm
IEEE J. Solid State Circuits
Haruki Mori, Je-Min Hung, Wei-Chang Zhao, Kinshuk Khare, Brian Crafton, Hiroaki Ishii, Cheng-En Lee, Xiaochen Peng, Xiaoyu Sun, Yorinobu Fujino, Chia-Jung Tsen, Vineet Joshi, Chao-Kai Chuang, Takeshi Hashizume, Chia-Fu Lee, Tan-Li Chou, Kerem Akarvardar, Saman Adham, Yih Wang, Hidehiro Fujiwara, Yu-Der Chih, Yen-Huei Chen, Hung-Jen Liao, Tsung-Yung Jonathan Chang
2026 J jnl
A μ-NMC-Δ-IMC Heterogeneous STT-MRAM Compute-in-Memory Macro Using Δ-Clamping Bit Reduction for Noise-Tolerant Bayesian Neural Networks.
IEEE J. Solid State Circuits
De-Qi You, Win-San Khwa, Bo Zhang, Fang-Yi Chen, Andrew Lee, Yu-Cheng Hung, Yi-Ming Li, Yu-Hui Wang, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Yu-Der Chih, Tsung-Yung Jonathan Chang, Meng-Fan Chang
2025 — conf
14.1 A 22nm 104.5TOPS/W µ-NMC-Δ-IMC Heterogeneous STT-MRAM CIM Macro for Noise-Tolerant Bayesian Neural Networks.
ISSCC
De-Qi You, Win-San Khwa, Bo Zhang, Fang-Yi Chen, Andrew Lee, Yu-Cheng Hung, Yi-Ming Li, Yu-Hui Wang, Chung-Chuan Lo, Ren-Shuo Liu, Kea-Tiong Tang, Chih-Cheng Hsieh, Yu-Der Chih, Tsung-Yung Jonathan Chang, Meng-Fan Chang
2025 J jnl
A 22 nm Floating-Point ReRAM Compute-in-Memory Macro Using Residue-Shared ADC for AI Edge Device.
IEEE J. Solid State Circuits
Hung-Hsi Hsu, Tai-Hao Wen, Win-San Khwa, Wei-Hsing Huang, Zhao-En Ke, Yu-Hsiang Chin, Hua-Jin Wen, Yu-Chen Chang, Wei-Ting Hsu, Ashwin Sanjay Lele, Bo Zhang, Ping-Sheng Wu, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Shih-Hsih Teng, Chung-Cheng Chou, Yu-Der Chih, Tsung-Yung Jonathan Chang, Meng-Fan Chang
2025 J jnl
An Edge Accelerator With 5 MB of 0.256-pJ/bit Embedded RRAM and a Localization Solver for Bristle Robot Surveillance.
IEEE J. Solid State Circuits
Samuel D. Spetalnick, Ashwin Sanjay Lele, Brian Crafton, Muya Chang, Sigang Ryu, Jong-Hyeok Yoon, Zhijian Hao, Azadeh Ansari, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Arijit Raychowdhury
2025 J jnl
Enhancing DCIM Efficiency with Multi-Storage-Row Architecture for Edge AI Workloads.
IEEE Comput. Archit. Lett.
Xiaoyu Sun, Haruki Mori, Wei-Chang Zhao, Je-Min Hung, Hidehiro Fujiwara, Brian Crafton, Bo Zhang, Win-San Khwa, Yu-Der Chih, Tsung-Yung Jonathan Chang, Kerem Akarvardar
2025 J jnl
MINOTAUR: A Posit-Based 0.42-0.50-TOPS/W Edge Transformer Inference and Training Accelerator.
IEEE J. Solid State Circuits
Kartik Prabhu, Robert M. Radway, Jeffrey Yu, Kai Bartolone, Massimo Giordano, Fabian Peddinghaus, Yonatan Urman, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Subhasish Mitra, Priyanka Raina
2024 — conf
15.7 A 32Mb RRAM in a 12nm FinFet Technology with a 0.0249μm
ISSCC
Yi-Cheng Huang, Shang-Hsuan Liu, Hsu-Shun Chen, Hsin-Chang Feng, Chih-Feng Li, Chou-Ying Yang, Wei-Keng Chang, Chang-Feng Yang, Chun-Yu Wu, Yen-Cheng Lin, Tsung-Tse Yang, Chih-Yang Chang, Wen-Ting Chu, Harry Chuang, Yih Wang, Yu-Der Chih, Tsung-Yung Jonathan Chang
2024 — conf
15.9 A 16nm 16Mb Embedded STT-MRAM with a 20ns Write Time, a 10
ISSCC
Ku-Feng Lin, Hiroki Noguchi, Yi-Chun Shih, Perng-Fei Yuh, Yuan-Jen Lee, Tung-Cheng Chang, Sheng-Po Huang, Yu-Fan Lin, Chun-Ying Lee, Yen-Hsiang Huang, Jui-Che Tsai, Saman Adham, Peter Noel, Ramin Yazdi, Marat Gershoig, YangJae Shin, Vineet Joshi, Ted Wong, Meng-Ru Jiang, J. J. Wu, Chun-Tai Cheng, Yu-Jen Wang, Harry Chuang, Yu-Der Chih, Yih Wang, Tsung-Yung Jonathan Chang
2024 — conf
30.1 A 40nm VLIW Edge Accelerator with 5MB of 0.256pJ/b RRAM and a Localization Solver for Bristle Robot Surveillance.
ISSCC
Samuel D. Spetalnick, Ashwin Sanjay Lele, Brian Crafton, Muya Chang, Sigang Ryu, Jong-Hyeok Yoon, Zhijian Hao, Azadeh Ansari, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Arijit Raychowdhury
2024 — conf
34.4 A 3nm, 32.5TOPS/W, 55.0TOPS/mm
ISSCC
Hidehiro Fujiwara, Haruki Mori, Wei-Chang Zhao, Kinshuk Khare, Cheng-En Lee, Xiaochen Peng, Vineet Joshi, Chao-Kai Chuang, Shu-Huan Hsu, Takeshi Hashizume, Toshiaki Naganuma, Chen-Hung Tien, Yao-Yi Liu, Yen-Chien Lai, Chia-Fu Lee, Tan-Li Chou, Kerem Akarvardar, Saman Adham, Yih Wang, Yu-Der Chih, Yen-Huei Chen, Hung-Jen Liao, Tsung-Yung Jonathan Chang
2024 — conf
34.8 A 22nm 16Mb Floating-Point ReRAM Compute-in-Memory Macro with 31.2TFLOPS/W for AI Edge Devices.
ISSCC
Tai-Hao Wen, Hung-Hsi Hsu, Win-San Khwa, Wei-Hsing Huang, Zhao-En Ke, Yu-Hsiang Chin, Hua-Jin Wen, Yu-Chen Chang, Wei-Ting Hsu, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Shih-Hsih Teng, Chung-Cheng Chou, Yu-Der Chih, Tsung-Yung Jonathan Chang, Meng-Fan Chang
2024 — conf
A 22nm Nonvolatile AI-Edge Processor with 21.4TFLOPS/W using 47.25Mb Lossless-Compressed-Computing STT-MRAM Near-Memory-Compute Macro.
VLSI Technology and Circuits
De-Qi You, Win-San Khwa, Jui-Jen Wu, Chuan-Jia Jhang, Guan-Yi Lin, Po-Jung Chen, Ting-Chien Chiu, Fang-Yi Chen, Andrew Lee, Yu-Cheng Hung, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Yu-Der Chih, Tsung-Yung Jonathan Chang, Meng-Fan Chang
2024 J jnl
A Heterogeneous RRAM In-Memory and SRAM Near-Memory SoC for Fused Frame and Event-Based Target Identification and Tracking.
IEEE J. Solid State Circuits
Ashwin Sanjay Lele, Muya Chang, Samuel D. Spetalnick, Brian Crafton, Shota Konno, Zishen Wan, Ashwin Bhat, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Arijit Raychowdhury
2024 J jnl
A Nonvolatile AI-Edge Processor With SLC-MLC Hybrid ReRAM Compute-in-Memory Macro Using Current-Voltage-Hybrid Readout Scheme.
IEEE J. Solid State Circuits
Hung-Hsi Hsu, Tai-Hao Wen, Wei-Hsing Huang, Win-San Khwa, Yun-Chen Lo, Chuan-Jia Jhang, Yu-Hsiang Chin, Yu-Chiao Chen, Chung-Chuan Lo, Ren-Shuo Liu, Kea-Tiong Tang, Chih-Cheng Hsieh, Yu-Der Chih, Tsung-Yung Jonathan Chang, Meng-Fan Chang
2024 J jnl
An 8b-Precision 8-Mb STT-MRAM Near-Memory-Compute Macro Using Weight-Feature and Input-Sparsity Aware Schemes for Energy-Efficient Edge AI Devices.
IEEE J. Solid State Circuits
De-Qi You, Yen-Cheng Chiu, Win-San Khwa, Chung-Yuan Li, Fang-Ling Hsieh, Yu-An Chien, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Yu-Der Chih, Tsung-Yung Jonathan Chang, Meng-Fan Chang
2024 J jnl
EMBER: Efficient Multiple-Bits-Per-Cell Embedded RRAM Macro for High-Density Digital Storage.
IEEE J. Solid State Circuits
Akash Levy, Luke R. Upton, Michael D. Scott, Dennis Rich, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Subhasish Mitra, Boris Murmann, Priyanka Raina
2024 J jnl
Efficient Processing of MLPerf Mobile Workloads Using Digital Compute-In-Memory Macros.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Xiaoyu Sun, Weidong Cao, Brian Crafton, Kerem Akarvardar, Haruki Mori, Hidehiro Fujiwara, Hiroki Noguchi, Yu-Der Chih, Meng-Fan Chang, Yih Wang, Tsung-Yung Jonathan Chang
2024 — conf
MINOTAUR: An Edge Transformer Inference and Training Accelerator with 12 MBytes On-Chip Resistive RAM and Fine-Grained Spatiotemporal Power Gating.
VLSI Technology and Circuits
Kartik Prabhu, Robert M. Radway, Y. Jeffrey, Kai Bartolone, Massimo Giordano, Fabian Peddinghaus, Yonatan Urman, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Subhasish Mitra, Priyanka Raina
2023 J jnl
8-b Precision 8-Mb ReRAM Compute-in-Memory Macro Using Direct-Current-Free Time-Domain Readout Scheme for AI Edge Devices.
IEEE J. Solid State Circuits
Je-Min Hung, Tai-Hao Wen, Yen-Hsiang Huang, Sheng-Po Huang, Fu-Chun Chang, Chin-I Su, Win-San Khwa, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Yu-Der Chih, Tsung-Yung Jonathan Chang, Meng-Fan Chang
2023 — conf
A 16nm 32Mb Embedded STT-MRAM with a 6ns Read-Access Time, a 1M-Cycle Write Endurance, 20-Year Retention at 150°C and MTJ-OTP Solutions for Magnetic Immunity.
ISSCC
Po-Hao Lee, Chia-Fu Lee, Yi-Chun Shih, Hon-Jarn Lin, Yen-An Chang, Cheng-Han Lu, Yu-Lin Chen, Chieh-Pu Lo, Chung-Chieh Chen, Cheng-Hsiung Kuo, Tan-Li Chou, Chia-Yu Wang, J. J. Wu, Roger Wang, Harry Chuang, Yih Wang, Yu-Der Chih, Tsung-Yung Jonathan Chang
2023 — conf
A 2.38 MCells/mm
VLSI Technology and Circuits
Samuel D. Spetalnick, Muya Chang, Shota Konno, Brian Crafton, Ashwin Sanjay Lele, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Arijit Raychowdhury
2023 — conf
A 22nm 8Mb STT-MRAM Near-Memory-Computing Macro with 8b-Precision and 46.4-160.1TOPS/W for Edge-AI Devices.
ISSCC
Yen-Cheng Chiu, Win-San Khwa, Chung-Yuan Li, Fang-Ling Hsieh, Yu-An Chien, Guan-Yi Lin, Po-Jung Chen, Tsen-Hsiang Pan, De-Qi You, Fang-Yi Chen, Andrew Lee, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Yu-Der Chih, Tsung-Yung Jonathan Chang, Meng-Fan Chang
2023 — conf
A 28nm Nonvolatile AI Edge Processor using 4Mb Analog-Based Near-Memory-Compute ReRAM with 27.2 TOPS/W for Tiny AI Edge Devices.
VLSI Technology and Circuits
Tai-Hao Wen, Je-Min Hung, Hung-Hsi Hsu, Yuan Wu, Fu-Chun Chang, Chung-Yuan Li, Chih-Han Chien, Chin-I Su, Win-San Khwa, Jui-Jen Wu, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Mon-Shu Ho, Yu-Der Chih, Tsung-Yung Jonathan Chang, Meng-Fan Chang
2023 — conf
A 4nm 6163-TOPS/W/b $\mathbf{4790-TOPS/mm^{2}/b}$ SRAM Based Digital-Computing-in-Memory Macro Supporting Bit-Width Flexibility and Simultaneous MAC and Weight Update.
ISSCC
Haruki Mori, Wei-Chang Zhao, Cheng-En Lee, Chia-Fu Lee, Yu-Hao Hsu, Chao-Kai Chuang, Takeshi Hashizume, Hao-Chun Tung, Yao-Yi Liu, Shin-Rung Wu, Kerem Akarvardar, Tan-Li Chou, Hidehiro Fujiwara, Yih Wang, Yu-Der Chih, Yen-Huei Chen, Hung-Jen Liao, Tsung-Yung Jonathan Chang
2023 — conf
A 73.53TOPS/W 14.74TOPS Heterogeneous RRAM In-Memory and SRAM Near-Memory SoC for Hybrid Frame and Event-Based Target Tracking.
ISSCC
Muya Chang, Ashwin Sanjay Lele, Samuel D. Spetalnick, Brian Crafton, Shota Konno, Zishen Wan, Ashwin Bhat, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Arijit Raychowdhury
2023 — conf
A Nonvolatile Al-Edge Processor with 4MB SLC-MLC Hybrid-Mode ReRAM Compute-in-Memory Macro and 51.4-251TOPS/W.
ISSCC
Wei-Hsing Huang, Tai-Hao Wen, Je-Min Hung, Win-San Khwa, Yun-Chen Lo, Chuan-Jia Jhang, Hung-Hsi Hsu, Yu-Hsiang Chin, Yu-Chiao Chen, Chung-Chuan Lo, Ren-Shuo Liu, Kea-Tiong Tang, Chih-Cheng Hsieh, Yu-Der Chih, Tsung-Yung Jonathan Chang, Meng-Fan Chang
2023 — conf
EMBER: A 100 MHz, 0.86 mm
ESSCIRC
Luke R. Upton, Akash Levy, Michael D. Scott, Dennis Rich, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Subhasish Mitra, Priyanka Raina, Boris Murmann
2022 — conf
A 12nm 121-TOPS/W 41.6-TOPS/mm2 All Digital Full Precision SRAM-based Compute-in-Memory with Configurable Bit-width For AI Edge Applications.
VLSI Technology and Circuits
Chia-Fu Lee, Cheng-Han Lu, Cheng-En Lee, Haruki Mori, Hidehiro Fujiwara, Yi-Chun Shih, Tan-Li Chou, Yu-Der Chih, Tsung-Yung Jonathan Chang
2022 J jnl
A 22-nm 1-Mb 1024-b Read Data-Protected STT-MRAM Macro With Near-Memory Shift-and-Rotate Functionality and 42.6-GB/s Read Bandwidth for Security-Aware Mobile Device.
IEEE J. Solid State Circuits
Yen-Cheng Chiu, Tung-Cheng Chang, Chun-Ying Lee, Je-Min Hung, Kuang-Tang Chang, Cheng-Xin Xue, Ssu-Yen Wu, Hui-Yao Kao, Peng Chen, Hsiao-Yu Huang, Shih-Hsih Teng, Chieh-Pu Lo, Yi-Chun Shih, Yu-Der Chih, Tsung-Yung Jonathan Chang, Yier Jin, Meng-Fan Chang
2022 — conf
A 22nm 4Mb STT-MRAM Data-Encrypted Near-Memory Computation Macro with a 192GB/s Read-and-Decryption Bandwidth and 25.1-55.1TOPS/W 8b MAC for AI Operations.
ISSCC
Yen-Cheng Chiu, Chia-Sheng Yang, Shih-Hsih Teng, Hsiao-Yu Huang, Fu-Chun Chang, Yuan Wu, Yu-An Chien, Fang-Ling Hsieh, Chung-Yuan Li, Guan-Yi Lin, Po-Jung Chen, Tsen-Hsiang Pan, Chung-Chuan Lo, Win-San Khwa, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Chieh-Pu Lo, Yu-Der Chih, Tsung-Yung Jonathan Chang, Meng-Fan Chang
2022 J jnl
A 40-nm 118.44-TOPS/W Voltage-Sensing Compute-in-Memory RRAM Macro With Write Verification and Multi-Bit Encoding.
IEEE J. Solid State Circuits
Jong-Hyeok Yoon, Muya Chang, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Arijit Raychowdhury
2022 J jnl
A 40-nm, 64-Kb, 56.67 TOPS/W Voltage-Sensing Computing-In-Memory/Digital RRAM Macro Supporting Iterative Write With Verification and Online Read-Disturb Detection.
IEEE J. Solid State Circuits
Jong-Hyeok Yoon, Muya Chang, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Arijit Raychowdhury
2022 — conf
A 40nm 60.64TOPS/W ECC-Capable Compute-in-Memory/Digital 2.25MB/768KB RRAM/SRAM System with Embedded Cortex M3 Microprocessor for Edge Recommendation Systems.
ISSCC
Muya Chang, Samuel D. Spetalnick, Brian Crafton, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Arijit Raychowdhury
2022 — conf
A 40nm 64kb 26.56TOPS/W 2.37Mb/mm
ISSCC
Samuel D. Spetalnick, Muya Chang, Brian Crafton, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Arijit Raychowdhury
2022 — conf
A 5-nm 254-TOPS/W 221-TOPS/mm
ISSCC
Hidehiro Fujiwara, Haruki Mori, Wei-Chang Zhao, Mei-Chen Chuang, Rawan Naous, Chao-Kai Chuang, Takeshi Hashizume, Dar Sun, Chia-Fu Lee, Kerem Akarvardar, Saman Adham, Tan-Li Chou, Mahmut Ersin Sinangil, Yih Wang, Yu-Der Chih, Yen-Huei Chen, Hung-Jen Liao, Tsung-Yung Jonathan Chang
2022 — conf
An 8-Mb DC-Current-Free Binary-to-8b Precision ReRAM Nonvolatile Computing-in-Memory Macro using Time-Space-Readout with 1286.4-21.6TOPS/W for Edge-AI Devices.
ISSCC
Je-Min Hung, Yen-Hsiang Huang, Sheng-Po Huang, Fu-Chun Chang, Tai-Hao Wen, Chin-I Su, Win-San Khwa, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Yu-Der Chih, Tsung-Yung Jonathan Chang, Meng-Fan Chang
2022 J jnl
CHIMERA: A 0.92-TOPS, 2.2-TOPS/W Edge AI Accelerator With 2-MByte On-Chip Foundry Resistive RAM for Efficient Training and Inference.
IEEE J. Solid State Circuits
Kartik Prabhu, Albert Gural, Zainab F. Khan, Robert M. Radway, Massimo Giordano, Kalhan Koul, Rohan Doshi, John W. Kustin, Timothy Liu, Gregorio B. Lopes, Victor Turbiner, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Guénolé Lallement, Boris Murmann, Subhasish Mitra, Priyanka Raina
2021 — conf
29.1 A 40nm 64Kb 56.67TOPS/W Read-Disturb-Tolerant Compute-in-Memory/Digital RRAM Macro with Active-Feedback-Based Read and In-Situ Write Verification.
ISSCC
Jong-Hyeok Yoon, Muya Chang, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Arijit Raychowdhury
2021 — conf
A 16Kb Antifuse One-Time-Programmable Memory in 5nm High-K Metal-Gate Fin-FET CMOS Featuring Bootstrap High Voltage Scheme, Read Endpoint Detection and Pseudo-Differential Sensing.
VLSI Circuits
Shaun Chou, Gu-Huan Li, Shawn Chen, Jun-Hao Chang, Wan-Hsueh Cheng, Shao-Ding Wu, Philex Fan, Chia-En Huang, Yu-Der Chih, Yih Wang, Jonathan Chang
2021 — conf
A 22nm 4Mb 8b-Precision ReRAM Computing-in-Memory Macro with 11.91 to 195.7TOPS/W for Tiny AI Edge Devices.
ISSCC
Cheng-Xin Xue, Je-Min Hung, Hui-Yao Kao, Yen-Hsiang Huang, Sheng-Po Huang, Fu-Chun Chang, Peng Chen, Ta-Wei Liu, Chuan-Jia Jhang, Chin-I Su, Win-San Khwa, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Yu-Der Chih, Tsung-Yung Jonathan Chang, Meng-Fan Chang
2021 — conf
A 40nm 100Kb 118.44TOPS/W Ternary-weight Computein-Memory RRAM Macro with Voltage-sensing Read and Write Verification for reliable multi-bit RRAM operation.
CICC
Jong-Hyeok Yoon, Muya Chang, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Arijit Raychowdhury
2021 — conf
An 89TOPS/W and 16.3TOPS/mm
ISSCC
Yu-Der Chih, Po-Hao Lee, Hidehiro Fujiwara, Yi-Chun Shih, Chia-Fu Lee, Rawan Naous, Yu-Lin Chen, Chieh-Pu Lo, Cheng-Han Lu, Haruki Mori, Wei-Cheng Zhao, Dar Sun, Mahmut E. Sinangil, Yen-Huei Chen, Tan-Li Chou, Kerem Akarvardar, Hung-Jen Liao, Yih Wang, Meng-Fan Chang, Tsung-Yung Jonathan Chang
2021 — conf
CHIMERA: A 0.92 TOPS, 2.2 TOPS/W Edge AI Accelerator with 2 MByte On-Chip Foundry Resistive RAM for Efficient Training and Inference.
VLSI Circuits
Massimo Giordano, Kartik Prabhu, Kalhan Koul, Robert M. Radway, Albert Gural, Rohan Doshi, Zainab F. Khan, John W. Kustin, Timothy Liu, Gregorio B. Lopes, Victor Turbiner, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Guénolé Lallement, Boris Murmann, Subhasish Mitra, Priyanka Raina
2021 J jnl
RRAM-DNN: An RRAM and Model-Compression Empowered All-Weights-On-Chip DNN Accelerator.
IEEE J. Solid State Circuits
Ziyun Li, Zhehong Wang, Li Xu, Qing Dong, Bowen Liu, Chin-I Su, Wen-Ting Chu, George Tsou, Yu-Der Chih, Tsung-Yung Jonathan Chang, Dennis Sylvester, Hun-Seok Kim, David T. Blaauw
2020 — conf
13.3 A 22nm 32Mb Embedded STT-MRAM with 10ns Read Speed, 1M Cycle Write Endurance, 10 Years Retention at 150°C and High Immunity to Magnetic Field Interference.
ISSCC
Yu-Der Chih, Yi-Chun Shih, Chia-Fu Lee, Yen-An Chang, Po-Hao Lee, Hon-Jarn Lin, Yu-Lin Chen, Chieh-Pu Lo, Meng-Chun Shih, Kuei-Hung Shen, Harry Chuang, Tsung-Yung Jonathan Chang
2020 — conf
A 22nm 96KX144 RRAM Macro with a Self-Tracking Reference and a Low Ripple Charge Pump to Achieve a Configurable Read Window and a Wide Operating Voltage Range.
VLSI Circuits
Chung-Cheng Chou, Zheng-Jun Lin, Chien-An Lai, Chin-I Su, Pei-Ling Tseng, Wei-Chi Chen, Wu-Chin Tsai, Wen-Ting Chu, Tong-Chern Ong, Harry Chuang, Yu-Der Chih, Tsung-Yung Jonathan Chang
2020 — conf
An All-Weights-on-Chip DNN Accelerator in 22nm ULL Featuring 24×1 Mb eRRAM.
VLSI Circuits
Zhehong Wang, Ziyun Li, Li Xu, Qing Dong, Chin-I Su, Wen-Ting Chu, George Tsou, Yu-Der Chih, Tsung-Yung Jonathan Chang, Dennis Sylvester, Hun-Seok Kim, David T. Blaauw
2019 J jnl
A 1-Mb 28-nm 1T1MTJ STT-MRAM With Single-Cap Offset-Cancelled Sense Amplifier and In Situ Self-Write-Termination.
IEEE J. Solid State Circuits
Qing Dong, Zhehong Wang, Jongyup Lim, Yiqun Zhang, Mahmut E. Sinangil, Yi-Chun Shih, Yu-Der Chih, Tsung-Yung Jonathan Chang, David T. Blaauw, Dennis Sylvester
2019 J jnl
A ReRAM Macro Using Dynamic Trip-Point-Mismatch Sampling Current-Mode Sense Amplifier and Low-DC Voltage-Mode Write-Termination Scheme Against Resistance and Write-Delay Variation.
IEEE J. Solid State Circuits
Chieh-Pu Lo, Wen-Zhang Lin, Wei-Yu Lin, Huan-Ting Lin, Tzu-Hsien Yang, Yen-Ning Chiang, Ya-Chin King, Chrong Jung Lin, Yu-Der Chih, Tsung-Yung Jonathon Chang, Meng-Fan Chang
2019 J jnl
Logic Process Compatible 40-nm 16-Mb, Embedded Perpendicular-MRAM With Hybrid-Resistance Reference, Sub- $\mu$ A Sensing Resolution, and 17.5-nS Read Access Time.
IEEE J. Solid State Circuits
Yi-Chun Shih, Chia-Fu Lee, Yen-An Chang, Po-Hao Lee, Hon-Jarn Lin, Yu-Lin Chen, Ku-Feng Lin, Ta-Ching Yeh, Hung-Chang Yu, Harry Chuang, Yu-Der Chih, Tsung-Yung Jonathan Chang
2018 — conf
A 1Mb 28nm STT-MRAM with 2.8ns read access time at 1.2V VDD using single-cap offset-cancelled sense amplifier and in-situ self-write-termination.
ISSCC
Qing Dong, Zhehong Wang, Jongyup Lim, Yiqun Zhang, Yi-Chun Shih, Yu-Der Chih, Tsung-Yung Jonathan Chang, David T. Blaauw, Dennis Sylvester
2018 — conf
A 28NM Integrated True Random Number Generator Harvesting Entropy from MRAM.
VLSI Circuits
Kaiyuan Yang, Qing Dong, Zhehong Wang, Yi-Chun Shih, Yu-Der Chih, Tsung-Yung Jonathan Chang, David T. Blaauw, Dennis Sylvester
2018 — conf
An N40 256K×44 embedded RRAM macro with SL-precharge SA and low-voltage current limiter to improve read and write performance.
ISSCC
Chung-Cheng Chou, Zheng-Jun Lin, Pei-Ling Tseng, Chih-Feng Li, Chih-Yang Chang, Wei-Chi Chen, Yu-Der Chih, Tsung-Yung Jonathan Chang
2018 — conf
Logic Process Compatible 40NM 16MB, Embedded Perpendicular-MRAM with Hybrid-Resistance Reference, Sub-μA Sensing Resolution, and 17.5NS Read Access Time.
VLSI Circuits
Yi-Chun Shih, Chia-Fu Lee, Yen-An Chang, Po-Hao Lee, Hon-Jarn Lin, Yu-Lin Chen, Ku-Feng Lin, Ta-Ching Yeh, Hung-Chang Yu, Harry Chuang, Yu-Der Chih, Tsung-Yung Jonathan Chang
2018 — conf
Logic Process Compatible 40nm 256K×144 Embedded RRAM with Low Voltage Current Limiter and Ambient Compensation Scheme to Improve the Read Window.
A-SSCC
Chien-An Lai, Chung-Cheng Chou, Chi-Hsiang Weng, Zheng-Jun Lin, Pei-Ling Tseng, Chien-Fan Wang, Chih-Chen Wang, Chin-I Su, Wei-Chi Chen, Yu-Cheng Lin, Tong-Chern Ong, Chi Chang, Yu-Der Chih, Tsung-Yung Jonathan Chang
2017 — conf
11.2 A 1Mb embedded NOR flash memory with 39µW program power for mm-scale high-temperature sensor nodes.
ISSCC
Qing Dong, Yejoong Kim, Inhee Lee, Myungjoon Choi, Ziyun Li, Jingcheng Wang, Kaiyuan Yang, Yen-Po Chen, Junjie Dong, Minchang Cho, Gyouho Kim, Wei-Keng Chang, Yun-Sheng Chen, Yu-Der Chih, David T. Blaauw, Dennis Sylvester
2017 — conf
11.3 A 10nm 32Kb low-voltage logic-compatible anti-fuse one-time-programmable memory with anti-tampering sensing scheme.
ISSCC
Shau-Yu Chou, Yu-Shiang Chen, Jun-Hao Chang, Yu-Der Chih, Tsung-Yung Jonathan Chang
2017 — conf
A 1.4Mb 40-nm embedded ReRAM macro with 0.07um
A-SSCC
Chia-Fu Lee, Hon-Jarn Lin, Chiu-Wang Lien, Yu-Der Chih, Tsung-Yung Jonathan Chang
2015 J jnl
An Asymmetric-Voltage-Biased Current-Mode Sensing Scheme for Fast-Read Embedded Flash Macros.
IEEE J. Solid State Circuits
Meng-Fan Chang, Yu-Fan Lin, Yen-Chen Liu, Jui-Jen Wu, Shin-Jang Shen, Wu-Chin Tsai, Yu-Der Chih
2015 J jnl
Low VDDmin Swing-Sample-and-Couple Sense Amplifier and Energy-Efficient Self-Boost-Write-Termination Scheme for Embedded ReRAM Macros Against Resistance and Switch-Time Variations.
IEEE J. Solid State Circuits
Meng-Fan Chang, Jui-Jen Wu, Tun-Fei Chien, Yen-Chen Liu, Ting-Chin Yang, Wen-Chao Shen, Ya-Chin King, Chrong Jung Lin, Ku-Feng Lin, Yu-Der Chih, Tsung-Yung Jonathan Chang
2014 — conf
19.4 embedded 1Mb ReRAM in 28nm CMOS with 0.27-to-1V read using swing-sample-and-couple sense amplifier and self-boost-write-termination scheme.
ISSCC
Meng-Fan Chang, Jui-Jen Wu, Tun-Fei Chien, Yen-Chen Liu, Ting-Chin Yang, Wen-Chao Shen, Ya-Chin King, Chorng-Jung Lin, Ku-Feng Lin, Yu-Der Chih, Sreedhar Natarajan, Tsung-Yung Jonathan Chang
2014 J jnl
Area-Efficient Embedded Resistive RAM (ReRAM) Macros Using Logic-Process Vertical-Parasitic-BJT (VPBJT) Switches and Read-Disturb-Free Temperature-Aware Current-Mode Read Scheme.
IEEE J. Solid State Circuits
Meng-Fan Chang, Chia-Chen Kuo, Shyh-Shyuan Sheu, Chorng-Jung Lin, Ya-Chin King, Frederick T. Chen, Tzu-Kun Ku, Ming-Jinn Tsai, Jui-Jen Wu, Yu-Der Chih
2013 — conf
A 180 MHz direct access read 4.6Mb embedded flash in 90nm technology operating under wide range power supply from 2.1V to 3.6V.
VLSI-DAT
Hung-Chang Yu, Ku-Feng Lin, Kai-Chun Lin, Yu-Der Chih, Sreedhar Natarajan
2013 — conf
A 55-nm, 0.86-Volt operation, 75MHz high speed, 96uA/MHz low power, wide voltage supply range 2M-bit split-gate embedded Flash.
VLSI-DAT
Caleb Y.-S. Cho, J. C. Wang, Lion Huang, Milo Weng, Yu-Fan Lin, Chia-Fu Lee, C. W. Lien, H. C. Feng, Tassa Yang, S. P. Liao, J. J. Wu, Yu-Der Chih, Sreedhar Natarajan
2013 J jnl
A Low-Voltage Bulk-Drain-Driven Read Scheme for Sub-0.5 V 4 Mb 65 nm Logic-Process Compatible Embedded Resistive RAM (ReRAM) Macro.
IEEE J. Solid State Circuits
Meng-Fan Chang, Che-Wei Wu, Chia-Chen Kuo, Shin-Jang Shen, Sue-Meng Yang, Ku-Feng Lin, Wen-Chao Shen, Ya-Chin King, Chorng-Jung Lin, Yu-Der Chih
2013 J jnl
An Offset-Tolerant Fast-Random-Read Current-Sampling-Based Sense Amplifier for Small-Cell-Current Nonvolatile Memory.
IEEE J. Solid State Circuits
Meng-Fan Chang, Shin-Jang Shen, Chia-Chi Liu, Che-Wei Wu, Yu-Fan Lin, Ya-Chin King, Chorng-Jung Lin, Hung-Jen Liao, Yu-Der Chih, Hiroyuki Yamauchi
2013 — conf
Cycling endurance optimization scheme for 1Mb STT-MRAM in 40nm technology.
ISSCC
Hung-Chang Yu, Kai-Chun Lin, Ku-Feng Lin, Chin-Yi Huang, Yu-Der Chih, Tong-Chern Ong, Tsung-Yung Jonathan Chang, Sreedhar Natarajan, Luan C. Tran
2012 — conf
A 0.5V 4Mb logic-process compatible embedded resistive RAM (ReRAM) in 65nm CMOS using low-voltage current-mode sensing scheme with 45ns random read time.
ISSCC
Meng-Fan Chang, Che-Wei Wu, Chia-Chen Kuo, Shin-Jang Shen, Ku-Feng Lin, Shu-Meng Yang, Ya-Chin King, Chorng-Jung Lin, Yu-Der Chih
2011 — conf
An offset-tolerant current-sampling-based sense amplifier for Sub-100nA-cell-current nonvolatile memory.
ISSCC
Meng-Fan Chang, Shin-Jang Shen, Chia-Chi Liu, Che-Wei Wu, Yu-Fan Lin, Shang-Chi Wu, Chia-En Huang, Han-Chao Lai, Ya-Chin King, Chorng-Jung Lin, Hung-Jen Liao, Yu-Der Chih, Hiroyuki Yamauchi