Yu-Chin Hsu

56 papers A* 11A 9Misc 2Journal 23Unranked 10
YearRankTypeTitle / Venue / Authors
2020 — conf
Intelligent Chips and Technologies for AIoT Era.
A-SSCC
Yu-Chin Hsu, Robert Chen-Hao Chang
2018 J jnl
Risk assessment in new software development projects at the front end: a fuzzy logic approach.
J. Ambient Intell. Humaniz. Comput.
Ming-Yuan Hsieh, Yu-Chin Hsu, Ching-Torng Lin
2016 — conf
Towards Understanding Senior Citizens' Gateball Participations Behavior and Well-Being: An Application of the Theory of Planned Behavior.
HCI (5)
Chia-Chien Hsu, Yu-Chin Hsu, Ching-Torng Lin
2012 Misc conf
Identifying ill tool combinations via Gibbs sampler for semiconductor manufacturing yield diagnosis.
WSC
Yu-Chin Hsu, Rong-Huei Chen, Chih-Ming Fan
2011 A* conf
A method to leverage pre-silicon collateral and analysis for post-silicon testing and validation.
DAC
Gary Miller, Bandana Bhattarai, Yu-Chin Hsu, Jay Dutt, Xi Chen, George Bakewell
2008 Misc conf
A General Failure Candidate Ranking Framework for Silicon Debug.
VTS
Chia-Chih Yen, Ten Lin, Hermes Lin, Kai Yang, Ta-Yung Liu, Yu-Chin Hsu
2007 — conf
Bridging RTL and gate: correlating different levels of abstraction for design debugging.
HLDVT
Eric Cheung, Xi Chen, Fur-Shing Tsai, Yu-Chin Hsu, Harry Hsieh
2006 — conf
Diagnosing Silicon Failures Based on Functional Test Patterns.
MTV
Chia-Chih Yen, Ten Lin, Hermes Lin, Kai Yang, Ta-Yung Liu, Yu-Chin Hsu
2006 A* conf
Visibility enhancement for silicon debug.
DAC
Yu-Chin Hsu, Fur-Shing Tsai, Wells Jong, Ying-Tsai Chang
2003 A* conf
Advanced techniques for RTL debugging.
DAC
Yu-Chin Hsu, Bassam Tabbara, Yirng-An Chen, Fur-Shing Tsai
2002 J jnl
Optimal time borrowing analysis and timing budgeting optimization for latch-based designs.
ACM Trans. Design Autom. Electr. Syst.
Shi-Zheng Eric Lin, Chieh Changfan, Yu-Chin Hsu, Fur-Shing Tsai
2000 J jnl
Timing optimization on routed designs with incremental placementand routing characterization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Chieh Changfan, Yu-Chin Hsu, Fur-Shing Tsai
1999 A conf
FSMD Functional Partitioning for Low Power.
DATE
Enoch Hwang, Frank Vahid, Yu-Chin Hsu
1999 — conf
Post-routing timing optimization with routing characterization.
ISPD
Chieh Changfan, Yu-Chin Hsu, Fur-Shing Tsai
1998 J jnl
Eliminating false loops caused by sharing in control path.
ACM Trans. Design Autom. Electr. Syst.
Alan Su, Yu-Chin Hsu, Ta-Yung Liu, Mike Tien-Chien Lee
1998 J jnl
Functional partitioning improvements over structural partitioning for packaging constraints and synthesis: tool performance.
ACM Trans. Design Autom. Electr. Syst.
Frank Vahid, Thuy Dm Le, Yu-Chin Hsu
1997 J jnl
Domain-Specific High-Level Modeling and Synthesis for ATM Switch Prototyping.
Des. Autom. Embed. Syst.
Mike Tien-Chien Lee, Yu-Chin Hsu, Ben Chen, Masahiro Fujita
1997 J jnl
Layout Modeling and Design Space Exploration in Pss1 System.
VLSI Design
Fur-Shing Tsai, Yu-Chin Hsu
1997 — conf
On the control-subroutine implementation of subprogram synthesis.
ASP-DAC
Cheng-Tsung Hwang, Hsiao-Chien Weng, Yu-Chin Hsu, Mike Tien-Chien Lee
1996 — conf
A Comparison of Functional and Structural Partitioning.
ISSS
Frank Vahid, Thuy Dm Le, Yu-Chin Hsu
1996 J jnl
Cell height driven transistor sizing in a cell based static CMOS module design.
IEEE J. Solid State Circuits
How-Rern Lin, Yu-Chin Hsu, TingTing Hwang
1996 A* conf
Domain-Specific High-Level Modeling and Synthesis for ATM Switch Design Using VHDL.
DAC
Mike Tien-Chien Lee, Yu-Chin Hsu, Ben Chen, Masahiro Fujita
1996 — conf
Eliminating False Loops Caused by Sharing in Control Path.
ISSS
Alan Su, Ta-Yung Liu, Yu-Chin Hsu, Mike Tien-Chien Lee
1995 J jnl
A new approach to schedule operations across nested-ifs and nested-loops.
Microprocess. Microprogramming
Shih-Hsu Huang, Cheng-Tsung Hwang, Yu-Chin Hsu, Yen-Jen Oyang
1995 J jnl
A new scheduling algorithm for synthesizing the control blocks of control-dominated circuits.
Microprocess. Microprogramming
Shih-Hsu Huang, Yu-Chin Hsu, Yen-Jen Oyang
1995 — conf
Synthesis of false loop free circuits.
ASP-DAC
Shih-Hsu Huang, Ta-Yung Liu, Yu-Chin Hsu, Yen-Jen Oyang
1994 — conf
Cell Height Driven Transistor Sizing in a Cell Based Module Design.
EDAC-ETC-EUROASIC
How-Rern Lin, Ching-Lung Chou, Yu-Chin Hsu, TingTing Hwang
1994 J jnl
MULTIPAR: behavioral partition for synthesizing multiprocessor architectures.
IEEE Trans. Very Large Scale Integr. Syst.
Yunn Yen Chen, Yu-Chin Hsu, Chung-Ta King
1994 J jnl
Rectilinear Steiner tree construction by local and global refinement.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Ting-Hai Chao, Yu-Chin Hsu
1993 J jnl
An efficient layout style for two-metal CMOS leaf cells and its automatic synthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Chi-Yi Hwang, Yung-Ching Hsieh, Youn-Long Lin, Yu-Chin Hsu
1993 A conf
High throughput pipelined data path synthesis by conserving the regularity of nested loops.
ICCAD
Yuan-Long Jeang, Yu-Chin Hsu, Jhing-Fa Wang, Jau-Yien Lee
1993 J jnl
PLS: a scheduler for pipeline synthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Cheng-Tsung Hwang, Yu-Chin Hsu, Youn-Long Lin
1993 J jnl
Zone scheduling.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Cheng-Tsung Hwang, Yu-Chin Hsu
1992 A* conf
A new approach to schedule operations across nested-ifs and nested-loops.
MICRO
Shih-Hsu Huang, Cheng-Tsung Hwang, Yu-Chin Hsu, Yen-Jen Oyang
1992 J jnl
STAR: An automatic data path allocator.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Fur-Shing Tsai, Yu-Chin Hsu
1992 A* conf
Zero Skew Clock Net Routing.
DAC
Ting-Hai Chao, Yu-Chin Hsu, Jan-Ming Ho
1991 J jnl
A formal approach to the scheduling problem in high level synthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Cheng-Tsung Hwang, Jiahn-Humg Lee, Yu-Chin Hsu
1991 A* conf
An Efficient Layout Style for 2-Metal CMOS Leaf Cells And Their Automatic Generation.
DAC
Chi-Yi Hwang, Yung-Ching Hsieh, Youn-Long Lin, Yu-Chin Hsu
1991 J jnl
Combining Logic Minimization and Folding for PLA's.
IEEE Trans. Computers
Yu-Chin Hsu, Youn-Long Lin, Hang-Ching Hsieh, Ting-Hai Chao
1991 A conf
Efficient Microcode Arrangement and Controller Synthesis for Application Specific Integrated Circuits.
ICCAD
Shi-Zheng Lin, Cheng-Tsung Hwang, Yu-Chin Hsu
1991 J jnl
LiB: a CMOS cell compiler.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Yung-Ching Hsieh, Chi-Yi Hwang, Youn-Long Lin, Yu-Chin Hsu
1991 A* conf
Scheduling for Functional Pipelining and Loop Winding.
DAC
Cheng-Tsung Hwang, Yu-Chin Hsu, Youn-Long Lin
1990 J jnl
A fast transistor-chaining algorithm for CMOS cell layout.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Chi-Yi Hwang, Yung-Chin Hsieh, Youn-Long Lin, Yu-Chin Hsu
1990 J jnl
A new algorithm for tile generation.
Integr.
Youn-Long Lin, Yu-Chin Hsu
1990 A* conf
Data Path Allocation Based on Bipartite Weighted Matching.
DAC
Chu-Yi Huang, Yen-Shen Chen, Youn-Long Lin, Yu-Chin Hsu
1990 A conf
Data Path Construction and Refinement.
ICCAD
Fur-Shing Tsai, Yu-Chin Hsu
1990 J jnl
Hybrid routing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Youn-Long Lin, Yu-Chin Hsu, Fur-Shing Tsai
1990 A* conf
LiB: A Cell Layout Generator.
DAC
Yung-Ching Hsieh, Chi-Yi Hwang, Youn-Long Lin, Yu-Chin Hsu
1990 A* conf
Optimum and Heuristic Data Path Scheduling Under Resource Constraints.
DAC
Cheng-Tsung Hwang, Yu-Chin Hsu, Youn-Long Lin
1990 A conf
Rectilinear Steiner Tree Construction by Local and Global Refinement.
ICCAD
Ting-Hai Chao, Yu-Chin Hsu
1989 A conf
A new integer linear programming formulation for the scheduling problem in data path synthesis.
ICCAD
Jiahn-Humg Lee, Yu-Chin Hsu, Youn-Long Lin
1989 A conf
An optimal transistor-chaining algorithm for CMOS cell layout.
ICCAD
Chi-Yi Hwang, Yung-Ching Hsieh, Youn-Long Lin, Yu-Chin Hsu
1989 A conf
Routing using a pyramid data structure.
ICCAD
Youn-Long Lin, Yu-Chin Hsu, Fur-Shing Tsai
1989 J jnl
SILK: a simulated evolution router.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Youn-Long Lin, Yu-Chin Hsu, Fur-Shing Tsai
1988 A conf
A detailed router based on simulated evolution.
ICCAD
Youn-Long Lin, Yu-Chin Hsu, Fur-Shing Tsai
1987 — —
Floor Planning and Global Routing in an Automated Chip Design System
Yu-Chin Hsu