Yow-Tyng Nieh

16 papers A* 4A 4Journal 7Unranked 1
YearRankTypeTitle / Venue / Authors
2016 J jnl
Skew Minimization With Low Power for Wide-Voltage-Range Multipower-Mode Designs.
IEEE Trans. Very Large Scale Integr. Syst.
Chung-Han Chou, Hua-Hsin Yeh, Shih-Hsu Huang, Yow-Tyng Nieh, Shih-Chieh Chang, Yung-Tai Chang
2015 J jnl
Clock Period Minimization with Minimum Leakage Power.
ACM Trans. Design Autom. Electr. Syst.
Shih-Hsu Huang, Hua-Hsin Yeh, Yow-Tyng Nieh
2014 A conf
Leakage-power-aware clock period minimization.
DATE
Hua-Hsin Yeh, Shih-Hsu Huang, Yow-Tyng Nieh
2013 A conf
Low-power timing closure methodology for ultra-low voltage designs.
ICCAD
Wen-Pin Tu, Chung-Han Chou, Shih-Hsu Huang, Shih-Chieh Chang, Yow-Tyng Nieh, Chien-Yung Chou
2009 J jnl
Opposite-phase register switching for peak current minimization.
ACM Trans. Design Autom. Electr. Syst.
Shih-Hsu Huang, Chia-Ming Chang, Yow-Tyng Nieh
2007 J jnl
A Fast Register Scheduling Approach to the Architecture of Multiple Clocking Domains.
J. Inf. Sci. Eng.
Shih-Hsu Huang, Chia-Ming Chang, Yow-Tyng Nieh
2007 A* conf
Clock Period Minimization with Minimum Delay Insertion.
DAC
Shih-Hsu Huang, Chun-Hua Cheng, Chia-Ming Chang, Yow-Tyng Nieh
2007 J jnl
Clock skew scheduling with race conditions considered.
ACM Trans. Design Autom. Electr. Syst.
Shih-Hsu Huang, Yow-Tyng Nieh
2007 J jnl
Opposite-Phase Clock Tree for Peak Current Reduction.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Yow-Tyng Nieh, Shih-Hsu Huang, Sheng-Yu Hsu
2006 — conf
Fast multi-domain clock skew scheduling for peak current reduction.
ASP-DAC
Shih-Hsu Huang, Chia-Ming Chang, Yow-Tyng Nieh
2006 A* conf
Register binding for clock period minimization.
DAC
Shih-Hsu Huang, Chun-Hua Cheng, Yow-Tyng Nieh, Wei-Chieh Yu
2006 A conf
State re-encoding for peak current minimization.
ICCAD
Shih-Hsu Huang, Chia-Ming Chang, Yow-Tyng Nieh
2006 J jnl
Synthesis of nonzero clock skew circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Shih-Hsu Huang, Yow-Tyng Nieh
2005 A* conf
Minimizing peak current via opposite-phase clock tree.
DAC
Yow-Tyng Nieh, Shih-Hsu Huang, Sheng-Yu Hsu
2005 A* conf
Race-condition-aware clock skew scheduling.
DAC
Shih-Hsu Huang, Yow-Tyng Nieh, Feng-Pin Lu
2003 A conf
Clock Period Minimization of Non-Zero Clock Skew Circuits.
ICCAD
Shih-Hsu Huang, Yow-Tyng Nieh