Youngsoo Shin - RankMe

179 papers A* 13A 26C 18Misc 2Journal 60Unranked 58

Year	Rank	Type	Title / Venue / Authors
2026	—	`conf`	Augmenting Human Motivation: A Co-Creative Inquiry into AR Glass Interactions for Everyday Thriving. CHI Extended Abstracts Youngsoo Shin, Jonathan W. Williams, Bumho Lee
2026	—	`conf`	Empowering Users Through Conversational Explanations: Interplay of Choice Architecture and Linguistic Styles in Music Recommenders. CHI Extended Abstracts Youngsoo Shin, Krithik Ranjan
2026	—	`conf`	Integrated Re-Fragmentation and Curve Correction for Curvilinear Optical Proximity Correction. ASP-DAC Seohyun Kim, Shilong Zhang, Junha Jang, Youngsoo Shin
2026	J	`jnl`	Smart Parenting, Smarter Planet: Designing Human-Centered IoT Solutions for Eco-Friendly Motherhood. Int. J. Hum. Comput. Interact. Youngsoo Shin, Minseok Kim, Chanhee Shin, Hyunsoo Jang, Yejin Kim
2025	—	`conf`	An Island Style Multi-Objective Evolutionary Framework for Synthesis of Memristor-Aided Logic. ASP-DAC Umar Afzaal, Seunggyu Lee, Youngsoo Shin
2025	C	`conf`	Fast and Accurate Analysis of Power Distribution Network Impedance for DRAM Design. ISCAS MinSeung Shin, Shilong Zhang, Youngsoo Shin
2025	—	`conf`	ML for Computational Lithography: Practical Recipes. ASP-DAC Youngsoo Shin
2025	—	`conf`	On-Chip Decoupling Capacitor Placement with Impedance Constraint for DRAM Design. MLCAD MinSeung Shin, Shilong Zhang, Geuna Chang, Youngsoo Shin
2025	J	`jnl`	Toward personalized AI-powered recommender systems to support users' daily music choice experiences. Int. J. Hum. Comput. Stud. Youngsoo Shin, Krithik Ranjan, Michael C. Kowalski, Jungkyoon Yoon
2025	—	`conf`	Verilog Code Generation of Hierarchical Design Using LLMs. MLCAD Geuna Chang, Shilong Zhang, Seohyun Kim, Woojin Kim, Youngsoo Shin
2024	J	`jnl`	Accurate Interpolation of Library Timing Parameters Through Recurrent Convolutional Neural Network. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Daijoon Hyun, Younggwang Jung, Youngsoo Shin
2024	J	`jnl`	Decap Insertion With Local Cell Relocation Minimizing IR-Drop Violations and Routing DRVs. IEEE Trans. Very Large Scale Integr. Syst. Daijoon Hyun, Younggwang Jung, Youngsoo Shin
2024	A	`conf`	Fast IR-Drop Prediction of Analog Circuits Using Recurrent Synchronized GCN and Y-Net Model. DATE Seunggyu Lee, Daijoon Hyun, Younggwang Jung, Gangmin Cho, Youngsoo Shin
2024	—	`conf`	Fast and Accurate Curvilinear OPC with ML-Guided Curve Correction. ISOCC Seohyun Kim, Gangmin Cho, Shilong Zhang, Youngsoo Shin
2024	—	`conf`	Integrated Netlist Synthesis and In-Memory Mapping for Memristor-Aided Logic. ACM Great Lakes Symposium on VLSI Seunggyu Lee, Wonjae Lee, Youngsoo Shin
2023	—	`conf`	AI-EDA: Toward a Holistic Approach to AI-Powered EDA. MLCAD Youngsoo Shin
2023	J	`jnl`	Airgap Insertion and Layer Reassignment Under Setup and Hold Timing Constraints. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Daijoon Hyun, Younggwang Jung, Youngsoo Shin
2023	C	`conf`	Block-Level Power Net Routing of Analog Circuit Using Reinforcement Learning. ISCAS TaeYoung Kim, Gangmin Cho, Youngsoo Shin
2023	—	`conf`	Decoupling Capacitor Insertion Minimizing IR-Drop Violations and Routing DRVs. ASP-DAC Daijoon Hyun, Younggwang Jung, Insu Cho, Youngsoo Shin
2023	J	`jnl`	Integrated Power Distribution Network Synthesis for Mixed Macro Blocks and Standard Cells. IEEE Trans. Circuits Syst. II Express Briefs Daijoon Hyun, Wonjae Lee, JinHyeong Park, Youngsoo Shin
2023	A*	`conf`	Lightning Talk 21: EDA with ML, Rule-Based, or Both? DAC Youngsoo Shin
2023	C	`conf`	Multisource Clock Tree Synthesis Through Sink Clustering and Fast Clock Latency Prediction. ISCAS ByungHo Choi, Yonghwi Kwon, Umar Afzaal, Youngsoo Shin
2023	A	`conf`	Power Distribution Network Optimization Using HLA-GCN for Routability Enhancement. ICCAD Younggwang Jung, Daijoon Hyun, Soyoon Choi, Youngsoo Shin
2023	J	`jnl`	Routability Optimization of Extreme Aspect Ratio Design through Non-uniform Placement Utilization and Selective Flip-flop Stacking. ACM Trans. Design Autom. Electr. Syst. Daijoon Hyun, Sunwha Koh, Younggwang Jung, TaeYoung Kim, Youngsoo Shin
2023	—	`conf`	Routability-Driven Power Distribution Network Synthesis with IR-Drop Budgeting. MLCAD Wonjae Lee, Insu Cho, Gangmin Cho, Youngsoo Shin
2023	—	`conf`	Simultaneous Clock Wire Sizing and Shield Insertion for Minimizing Routing Blockage. MLCAD Yoonsang Song, Gangmin Cho, Wonjae Lee, Youngsoo Shin
2023	Misc	`conf`	Too Many or Too Little: Investigating Different Decision-making Experiences of Maximizers and Satisficers in HCIs. OZCHI Youngsoo Shin, Jungkyoon Yoon
2022	—	`conf`	Fast Prediction of Dynamic IR-Drop Using Recurrent U-Net Architecture. MLCAD Yonghwi Kwon, Youngsoo Shin
2022	—	`conf`	Supporting Users' Decision-Making Experiences through Hyper-Personalized Human-Technology Interactions. onference on Designing Interactive Systems (Companion Volume) Youngsoo Shin
2021	J	`jnl`	Computational Lithography Using Machine Learning Models. IPSJ Trans. Syst. LSI Des. Methodol. Youngsoo Shin
2021	C	`conf`	Dynamic IR Drop Prediction Using Image-to-Image Translation Neural Network. ISCAS Yonghwi Kwon, Giyoon Jung, Daijoon Hyun, Youngsoo Shin
2021	—	`conf`	PENCODER: Design for Prospective Memory and Older Adults. CHI Extended Abstracts Youngsoo Shin, Ruth Barankevich, Jina Lee, Saleh Kalantari
2021	C	`conf`	Routability Optimization for Extreme Aspect Ratio Design Using Convolutional Neural Network. ISCAS Sunwha Koh, Younggwang Jung, Daijoon Hyun, Youngsoo Shin
2021	—	`conf`	Towards Designing Human-Centered Time Management Interfaces: The Development of 14 UX Design Guidelines for Time-related Experiences in Mobile HCI. MobileHCI (Extended Abstracts) Youngsoo Shin, Jungkyoon Yoon
2020	—	`conf`	Fast ECO Leakage Optimization Using Graph Convolutional Network. ACM Great Lakes Symposium on VLSI Wonjae Lee, Yonghwi Kwon, Youngsoo Shin
2020	—	`conf`	Integrated Airgap Insertion and Layer Reassignment for Circuit Timing optimization. ASP-DAC Younggwang Jung, Daijoon Hyun, Youngsoo Shin
2020	A	`conf`	Pre-layout clock tree estimation and optimization using artificial neural network. ISLPED Sunwha Koh, Yonghwi Kwon, Youngsoo Shin
2019	A	`conf`	Accurate Wirelength Prediction for Placement-Aware Synthesis through Machine Learning. DATE Daijoon Hyun, Yuepeng Fan, Youngsoo Shin
2019	A	`conf`	Clock Gating Synthesis of Netlist with Cyclic Logic Paths. ICCAD Yonghwi Kwon, Inhak Han, Youngsoo Shin
2019	J	`jnl`	Cut Optimization for Redundant Via Insertion in Self-Aligned Double Patterning. ACM Trans. Design Autom. Electr. Syst. Youngsoo Song, Daijoon Hyun, Jingon Lee, Jinwook Jung, Youngsoo Shin
2019	A	`conf`	Endurance Enhancement of Multi-Level Cell Phase Change Memory. ICCAD Cheongwon Lee, Youngsoo Song, Youngsoo Shin
2019	J	`jnl`	Integrated Approach of Airgap Insertion for Circuit Timing Optimization. ACM Trans. Design Autom. Electr. Syst. Daijoon Hyun, Youngsoo Shin
2019	J	`jnl`	Integrated Latch Placement and Cloning for Timing Optimization. ACM Trans. Design Autom. Electr. Syst. Jinwook Jung, Gi-Joon Nam, Woohyun Chung, Youngsoo Shin
2019	J	`jnl`	Neural Network Classifier-Based OPC With Imbalanced Training Data. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Suhyeong Choi, Seongbo Shim, Youngsoo Shin
2019	J	`jnl`	Selective Use of Stitch-Induced Via for V0 Mask Reduction: Standard Cell Design and Placement Optimization. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Daijoon Hyun, Younggwang Jung, Youngsoo Shin
2019	C	`conf`	Standard Cell Layout Design and Placement Optimization for TFET-Based Circuits. ISCAS Youngsoo Song, Jinwook Jung, Youngsoo Shin
2018	—	`ed.`	23rd Asia and South Pacific Design Automation Conference, ASP-DAC 2018, Jeju, Korea (South), January 22-25, 2018 ASP-DAC Youngsoo Shin
2018	—	`conf`	Automatic insertion of airgap with design rule constraints. ASP-DAC Daijoon Hyun, Youngsoo Shin
2018	J	`jnl`	Data-centered persuasion: Nudging user's prosocial behavior and designing social innovation. Comput. Hum. Behav. Youngsoo Shin, Jinwoo Kim
2018	J	`jnl`	Electrothermal Analysis With Nonconvective Boundary Conditions. IEEE Trans. Circuits Syst. II Express Briefs Suhyeong Choi, Seongbo Shim, Youngsoo Shin
2018	—	`conf`	Fast Timing Analysis of Non-Tree Clock Network with Shorted Wires. ACM Great Lakes Symposium on VLSI Kiwon Yoon, Daijoon Hyun, Youngsoo Shin
2018	C	`conf`	Fast Timing Analysis of Transistor-Level Full Custom Digital Circuits. ISCAS Jingon Lee, Jinwook Jung, Youngsoo Shin
2018	J	`jnl`	Folded Circuit Synthesis: Min-Area Logic Synthesis Using Dual-Edge-Triggered Flip-Flops. ACM Trans. Design Autom. Electr. Syst. Inhak Han, Youngsoo Shin
2018	C	`conf`	Library Optimization for Near-Threshold Voltage Design. ISCAS Daijoon Hyun, Jaewoo Seo, Youngsoo Shin
2018	J	`jnl`	Memory-Efficient Parametric Semiglobal Matching. IEEE Signal Process. Lett. Yeongmin Lee, Min-Gyu Park, Youngbae Hwang, Youngsoo Shin, Chong-Min Kyung
2018	J	`jnl`	Module grouping to reduce the area of test wrappers in SoCs. Integr. Sangmin Kim, Youngsoo Shin
2018	J	`jnl`	OWARU: Free Space-Aware Timing-Driven Incremental Placement With Critical Path Smoothing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jinwook Jung, Gi-Joon Nam, Lakshmi N. Reddy, Iris Hui-Ru Jiang, Youngsoo Shin
2018	—	`conf`	Optimization of Machine Learning Guided Optical Proximity Correction. MWSCAS Joonhyuk Cho, Gangmin Cho, Youngsoo Shin
2018	J	`jnl`	Recap of the 23rd Asia and South Pacific Design Automation Conference (ASP-DAC). IEEE Des. Test Youngsoo Shin
2018	C	`conf`	Transient Clock Power Estimation of Pre-CTS Netlist. ISCAS Yonghwi Kwon, Jinwook Jung, Inhak Han, Youngsoo Shin
2017	—	`conf`	Clock tree optimization through selective airgap insertion. ISQED Daijoon Hyun, Wachirawit Ponghiran, Youngsoo Shin
2017	A	`conf`	Cut mask optimization for multi-patterning directed self-assembly lithography. DATE Wachirawit Ponghiran, Seongbo Shim, Youngsoo Shin
2017	J	`jnl`	Design for experience innovation: understanding user experience in new product development. Behav. Inf. Technol. Youngsoo Shin, Chaerin Im, Hyosun Oh, Jinwoo Kim
2017	J	`jnl`	Fast Verification of Guide-Patterns for Directed Self-Assembly Lithography. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Seongbo Shim, Youngsoo Shin
2017	J	`jnl`	Lithography Defect Probability and Its Application to Physical Design Optimization. IEEE Trans. Very Large Scale Integr. Syst. Seongbo Shim, Woohyun Chung, Youngsoo Shin
2017	A*	`conf`	Pin Accessibility-Driven Cell Layout Redesign and Placement Optimization. DAC Jaewoo Seo, Jinwook Jung, Sangmin Kim, Youngsoo Shin
2017	—	`conf`	Redundant Via Insertion with Cut Optimization for Self-Aligned Double Patterning. ACM Great Lakes Symposium on VLSI Youngsoo Song, Jinwook Jung, Youngsoo Shin
2017	C	`conf`	Redundant Via insertion in SADP process with cut merging and optimization. VLSI-SoC Youngsoo Song, Jinwook Jung, Youngsoo Shin
2017	A	`conf`	Timing-aware wire width optimization for SADP process. DATE Youngsoo Song, Sangmin Kim, Youngsoo Shin
2016	—	`conf`	Area efficient neuromorphic circuit based on stochastic computation. ISOCC Kiwon Yoon, Suhyeong Choi, Youngsoo Shin
2016	—	`conf`	Buffer insertion to remove hold violations at multiple process corners. ASP-DAC Inhak Han, Daijoon Hyun, Youngsoo Shin
2016	C	`conf`	Crosslink insertion for minimizing OCV clock skew. ISCAS Kiwon Yoon, Seongbo Shim, Youngsoo Shin
2016	—	`conf`	Localized DNA circuit design with majority gates. BioCAS Jinwook Jung, Youngsoo Shin
2016	—	`conf`	Machine learning (ML)-based lithography optimizations. APCCAS Seongbo Shim, Suhyeong Choi, Youngsoo Shin
2016	—	`conf`	Mask optimization for directed self-assembly lithography: Inverse DSA and inverse lithography. ASP-DAC Seongbo Shim, Youngsoo Shin
2016	A	`conf`	OWARU: free space-aware timing-driven incremental placement. ICCAD Jinwook Jung, Gi-Joon Nam, Lakshmi N. Reddy, Iris Hui-Ru Jiang, Youngsoo Shin
2016	J	`jnl`	One-Cycle Correction of Timing Errors in Pipelines With Standard Clocked Elements. IEEE Trans. Very Large Scale Integr. Syst. Insup Shin, Jae-Joon Kim, Yu-Shiang Lin, Youngsoo Shin
2016	—	`conf`	Placement optimization for MP-DSAL compliant layout. ICICDT Seongbo Shim, Woohyun Chung, Youngsoo Shin
2016	A*	`conf`	Redundant via insertion for multiple-patterning directed-self-assembly lithography. DAC Seongbo Shim, Woohyun Chung, Youngsoo Shin
2016	A	`conf`	Redundant via insertion in directed self-assembly lithography. DATE Woohyun Chung, Seongbo Shim, Youngsoo Shin
2016	—	`conf`	Register grouping for synthesis of clock gating logic. ICICDT Inhak Han, Jonggyu Kim, Joonhwan Yi, Youngsoo Shin
2016	J	`jnl`	Synthesis of Dual-Mode Circuits Through Library Design, Gate Sizing, and Clock-Tree Optimization. ACM Trans. Design Autom. Electr. Syst. Sangmin Kim, Seokhyeong Kang, Youngsoo Shin
2016	—	`ed.`	VLSI-SoC: Design for Reliability, Security, and Low Power - 23rd IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2015, Daejeon, Korea, October 5-7, 2015, Revised Selected Papers VLSI-SoC (Selected Papers) Youngsoo Shin, Chi-Ying Tsui, Jae-Joon Kim, Kiyoung Choi, Ricardo Reis
2016	J	`jnl`	Wakeup scheduling and its buffered tree synthesis for power gating circuits. Integr. Sangmin Kim, Seungwhun Paik, Seokhyeong Kang, Youngsoo Shin
2015	J	`jnl`	Aggressive Voltage Scaling Through Fast Correction of Multiple Errors With Seamless Pipeline Operation. IEEE Trans. Circuits Syst. I Regul. Pap. Insup Shin, Jae-Joon Kim, Youngsoo Shin
2015	J	`jnl`	An Analytical Approach to Thermal Design and Optimization With a Temperature-Dependent Power Model. IEEE Trans. Circuits Syst. I Regul. Pap. Seongbo Shim, Jae Wook Lee, Youngsoo Shin
2015	A	`conf`	Defect Probability of Directed Self-Assembly Lithography: Fast Identification and Post-Placement Optimization. ICCAD Seongbo Shim, Woohyun Chung, Youngsoo Shin
2015	A	`conf`	Identifying redundant inter-cell margins and its application to reducing routing congestion. DATE Woohyun Chung, Seongbo Shim, Youngsoo Shin
2015	C	`conf`	Message from the technical program chairs. VLSI-SoC Youngsoo Shin, Chi-Ying Tsui
2015	C	`conf`	Physical design and mask optimization for directed self-assembly lithography (DSAL). VLSI-SoC Seongbo Shim, Youngsoo Shin
2015	C	`conf`	Physical synthesis of DNA circuits with spatially localized gates. ICCD Jinwook Jung, Daijoon Hyun, Youngsoo Shin
2015	J	`jnl`	Prosocial Activists in SNS: The Impact of Isomorphism and Social Presence on Prosocial Behaviors. Int. J. Hum. Comput. Interact. Youngsoo Shin, Bumho Lee, Jinwoo Kim
2014	—	`conf`	Design and Optimization of Multiple-Mesh Clock Network. VLSI-SoC (Selected Papers) Jinwook Jung, Dongsoo Lee, Youngsoo Shin
2014	J	`jnl`	HAPL: Heterogeneous Array of Programmable Logic Using Selective Mask Patterning. IEEE Trans. Circuits Syst. I Regul. Pap. Youngsoo Shin, Insup Shin, Donkyu Baek, Duckhwan Kim, Seungwhun Paik
2014	—	`conf`	Lithographic defect aware placement using compact standard Cells without inter-cell margin. ASP-DAC Seongbo Shim, Yoojong Lee, Youngsoo Shin
2014	—	`conf`	Power minimization of pipeline architecture through 1-cycle error correction and voltage scaling. ASP-DAC Insup Shin, Jae-Joon Kim, Youngsoo Shin
2014	J	`jnl`	Simplifying Clock Gating Logic by Matching Factored Forms. IEEE Trans. Very Large Scale Integr. Syst. Inhak Han, Youngsoo Shin
2013	A	`conf`	A pipeline architecture with 1-cycle timing error correction for low voltage operations. ISLPED Insup Shin, Jae-Joon Kim, Yu-Shiang Lin, Youngsoo Shin
2013	J	`jnl`	Accurate gate delay Extraction for Timing Analysis of Body-Biased Circuits. J. Circuits Syst. Comput. Donkyu Baek, Insup Shin, Youngsoo Shin
2013	C	`conf`	Analysis and minimization of short-circuit current in mesh clock network. ICCD Seongbo Shim, Minyoung Mo, Sangmin Kim, Youngsoo Shin
2013	—	`conf`	Folded circuit synthesis: Logic simplification using dual edge-triggered flip-flops. ICICDT Inhak Han, Youngsoo Shin
2013	—	`conf`	Pulsed-latch ASIC synthesis in industrial design flow. ASP-DAC Sangmin Kim, Duckhwan Kim, Youngsoo Shin
2012	J	`jnl`	Clock Gating Synthesis of Pulsed-Latch Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Seungwhun Paik, Inhak Han, Sangmin Kim, Youngsoo Shin
2012	—	`conf`	Gate delay modeling for static timing analysis of body-biased circuits. ICICDT Donkyu Baek, Insup Shin, Youngsoo Shin
2012	J	`jnl`	HLS-dv: A High-Level Synthesis Framework for Dual-Vdd Architectures. IEEE Trans. Very Large Scale Integr. Syst. Insup Shin, Seungwhun Paik, Dongwan Shin, Youngsoo Shin
2012	—	`conf`	Introducing irregularity to routing architecture of structured ASIC for better routability. FPT Insup Shin, Donkyu Baek, Youngsoo Shin
2012	J	`jnl`	Maximizing Frequency and Yield of Power-Constrained Designs Using Programmable Power-Gating. IEEE Trans. Very Large Scale Integr. Syst. Nam Sung Kim, Abhishek A. Sinkar, Jun Seomun, Youngsoo Shin
2012	J	`jnl`	Synthesis of Active-Mode Power-Gating Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jun Seomun, Insup Shin, Youngsoo Shin
2012	—	`conf`	Synthesis of clock gating logic through factored form matching. ICICDT Inhak Han, Youngsoo Shin
2011	—	`conf`	Compact thermal models: Assessment and pitfalls. ISOCC Jaeha Kung, Youngsoo Shin
2011	J	`jnl`	Design and Optimization of Power-Gated Circuits With Autonomous Data Retention. IEEE Trans. Very Large Scale Integr. Syst. Jun Seomun, Youngsoo Shin
2011	A	`conf`	Implementation of pulsed-latch and pulsed-register circuits to minimize clocking power. ICCAD Seungwhun Paik, Gi-Joon Nam, Youngsoo Shin
2011	J	`jnl`	Pulsed-Latch Aware Placement for Timing-Integrity Optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yi-Lin Chuang, Sangmin Kim, Youngsoo Shin, Yao-Wen Chang
2011	J	`jnl`	Pulsed-Latch Circuits: A New Dimension in ASIC Design. IEEE Des. Test Comput. Youngsoo Shin, Seungwhun Paik
2011	—	`conf`	Pulser gating: A clock gating of pulsed-latch circuits. ASP-DAC Sangmin Kim, Inhak Han, Seungwhun Paik, Youngsoo Shin
2011	J	`jnl`	Retiming Pulsed-Latch Circuits With Regulating Pulse Width. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Seungwhun Paik, Seonggwan Lee, Youngsoo Shin
2011	J	`jnl`	Sampling Correlation Sources for Timing Yield Analysis of Sequential Circuits with Clock Networks. J. Circuits Syst. Comput. Lee-eun Yu, Changsik Shin, Seungwhun Paik, Jing-Jia Liou, Youngsoo Shin
2011	—	`conf`	Selectively patterned masks: Structured ASIC with asymptotically ASIC performance. ASP-DAC Donkyu Baek, Insup Shin, Seungwhun Paik, Youngsoo Shin
2011	A*	`conf`	Thermal signature: a simple yet accurate thermal index for floorplan optimization. DAC Jaeha Kung, Inhak Han, Sachin S. Sapatnekar, Youngsoo Shin
2010	—	`conf`	Bounded potential slack: enabling time budgeting for dual-Vt allocation of hierarchical design. ASP-DAC Jun Seomun, Seungwhun Paik, Youngsoo Shin
2010	J	`jnl`	HLS-l: A High-Level Synthesis Framework for Latch-Based Architectures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Seungwhun Paik, Insup Shin, Taewhan Kim, Youngsoo Shin
2010	J	`jnl`	Lookup Table-Based Adaptive Body biasing of Multiple Macros for Process Variation Compensation and Low Leakage. J. Circuits Syst. Comput. Byunghee Choi, Youngsoo Shin
2010	J	`jnl`	Power gating: Circuits, design methodologies, and best practice for standard-cell VLSI designs. ACM Trans. Design Autom. Electr. Syst. Youngsoo Shin, Jun Seomun, Kyu-Myung Choi, Takayasu Sakurai
2010	J	`jnl`	Pulse Width Allocation and Clock Skew Scheduling: Optimizing Sequential Circuits Based on Pulsed Latches. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Hyein Lee, Seungwhun Paik, Youngsoo Shin
2010	A*	`conf`	Pulsed-latch aware placement for timing-integrity optimization. DAC Yi-Lin Chuang, Sangmin Kim, Youngsoo Shin, Yao-Wen Chang
2010	—	`conf`	Statistical time borrowing for pulsed-latch circuit designs. ASP-DAC Seungwhun Paik, Lee-eun Yu, Youngsoo Shin
2010	J	`jnl`	Supply Switching With Ground Collapse for Low-Leakage Register Files in 65-nm CMOS. IEEE Trans. Very Large Scale Integr. Syst. Hyung-Ock Kim, Bong Hyun Lee, Jong-Tae Kim, Jung Yun Choi, Kyu-Myung Choi, Youngsoo Shin
2010	A*	`conf`	Synthesis and implementation of active mode power gating circuits. DAC Jun Seomun, Insup Shin, Youngsoo Shin
2010	A	`conf`	Wakeup synthesis and its buffered tree construction for power gating circuit designs. ISLPED Seungwhun Paik, Sangmin Kim, Youngsoo Shin
2009	A	`conf`	Frequency and yield optimization using power gates in power-constrained designs. ISLPED Nam Sung Kim, Jun Seomun, Abhishek A. Sinkar, Jungseob Lee, Tae Hee Han, Ken Choi, Youngsoo Shin
2009	A	`conf`	HLS-l: High-level synthesis of high performance latch-based circuits. DATE Seungwhun Paik, Insup Shin, Youngsoo Shin
2009	J	`jnl`	Minimizing leakage power of sequential circuits through mixed- ACM Trans. Design Autom. Electr. Syst. Jaehyun Kim, Chungki Oh, Youngsoo Shin
2009	A*	`conf`	Register allocation for high-level synthesis using dual supply voltages. DAC Insup Shin, Seungwhun Paik, Youngsoo Shin
2009	A	`conf`	Retiming and time borrowing: Optimizing high-performance pulsed-latch-based circuits. ICCAD Seonggwan Lee, Seungwhun Paik, Youngsoo Shin
2009	J	`jnl`	Semicustom Design of Zigzag Power-Gated Circuits in Standard Cell Elements. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Youngsoo Shin, Seungwhun Paik, Hyung-Ock Kim
2009	J	`jnl`	ssr HLShbox-ssr pg: High-Level Synthesis of Power-Gated Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Eunjoo Choi, Changsik Shin, Youngsoo Shin
2008	C	`conf`	3-D thermal simulation with dynamic power profiles. ISCAS Eunjoo Choi, Youngsoo Shin
2008	A*	`conf`	Multiobjective optimization of sleep vector for zigzag power-gated circuits in standard cell elements. DAC Seungwhun Paik, Youngsoo Shin
2008	A	`conf`	Power-gating-aware high-level synthesis. ISLPED Eunjoo Choi, Changsik Shin, Taewhan Kim, Youngsoo Shin
2008	A	`conf`	Pulse width allocation with clock skew scheduling for optimizing pulsed latch-based sequential circuits. ICCAD Hyein Lee, Seungwhun Paik, Youngsoo Shin
2008	J	`jnl`	Skewed Flip-Flop and Mixed-V IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jun Seomun, Jae-Hyun Kim, Youngsoo Shin
2008	—	`conf`	Statistical mixed Vt allocation of body-biased circuits for reduced leakage variation. ASP-DAC Jinseob Jeong, Seungwhun Paik, Youngsoo Shin
2007	—	`conf`	Cell-Based Semicustom Design of Zigzag Power Gating Circuits. ISQED Youngsoo Shin, Hyung-Ock Kim
2007	—	`conf`	Lookup Table-Based Adaptive Body Biasing of Multiple Macros. ISQED Byunghee Choi, Youngsoo Shin
2007	A	`conf`	Minimizing leakage power in sequential circuits by using mixed ICCAD Jaehyun Kim, Youngsoo Shin
2007	J	`jnl`	Semicustom Design Methodology of Power Gated Circuits for Low Leakage Applications. IEEE Trans. Circuits Syst. II Express Briefs Hyung-Ock Kim, Youngsoo Shin
2007	—	`conf`	Simultaneous Control of Subthreshold and Gate Leakage Current in Nanometer-Scale CMOS Circuits. ASP-DAC Youngsoo Shin, Sewan Heo, Hyung-Ock Kim, Jung Yun Choi
2007	A*	`conf`	Skewed Flip-Flop Transformation for Minimizing Leakage in Sequential Circuits. DAC Jun Seomun, Jaehyun Kim, Youngsoo Shin
2007	J	`jnl`	Supply Switching With Ground Collapse: Simultaneous Control of Subthreshold and Gate Leakage Current in Nanometer-Scale CMOS Circuits. IEEE Trans. Very Large Scale Integr. Syst. Youngsoo Shin, Sewan Heo, Hyung-Ock Kim, Jung Yun Choi
2006	—	`conf`	Analysis and optimization of gate leakage current of power gating circuits. ASP-DAC Hyung-Ock Kim, Youngsoo Shin
2006	A*	`conf`	Physical design methodology of power gating circuits for standard-cell-based design. DAC Hyung-Ock Kim, Youngsoo Shin, Hyuk Kim, Iksoo Eo
2006	J	`jnl`	Power Analysis of VLSI Interconnect with RLC Tree Models and Model Reduction. J. Circuits Syst. Comput. Youngsoo Shin, Junghyup Lee
2005	—	`conf`	A Mask Reuse Methodology for Reducing System-on-a-Chip Cost. ISQED Subhrajit Bhattacharya, John A. Darringer, Daniel L. Ostapko, Youngsoo Shin
2005	—	`conf`	Analysis of power consumption in VLSI global interconnects. ISCAS (5) Youngsoo Shin, Hyung-Ock Kim
2005	—	`conf`	Power-aware slack distribution for hierarchical VLSI design. ISCAS (4) Hyung-Ock Kim, Youngsoo Shin
2005	J	`jnl`	μITRON-LP: power-conscious real-time OS based on cooperative voltage scaling for multimedia applications. IEEE Trans. Multim. Hiroshi Kawaguchi, Youngsoo Shin, Takayasu Sakurai
2004	A	`conf`	Architecting voltage islands in core-based system-on-a-chip designs. ISLPED Jingcao Hu, Youngsoo Shin, Nagu R. Dhanwada, Radu Marculescu
2003	Misc	`conf`	SEAS: a system for early analysis of SoCs. CODES+ISSS Reinaldo A. Bergamaschi, Youngsoo Shin, Nagu R. Dhanwada, Subhrajit Bhattacharya, William E. Dougherty, Indira Nair, John A. Darringer, Sarala Paliwal
2002	J	`jnl`	Early analysis tools for system-on-a-chip design. IBM J. Res. Dev. John A. Darringer, Reinaldo A. Bergamaschi, Subhrajit Bhattacharya, Daniel Brand, Andreas Herkersdorf, Joseph K. Morrell, Indira Nair, Patricia Sagmeister, Youngsoo Shin
2002	J	`jnl`	Power distribution analysis of VLSI interconnects using model orderreduction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Youngsoo Shin, Takayasu Sakurai
2001	—	`conf`	Cooperative voltage scaling (CVS) between OS and applications for low-power real-time systems. CICC Youngsoo Shin, Hiroshi Kawaguchi, Takayasu Sakurai
2001	A*	`conf`	Coupling-Driven Bus Design for Low-Power Application-Specific Systems. DAC Youngsoo Shin, Takayasu Sakurai
2001	A	`conf`	Estimation of power distribution in VLSI interconnects. ISLPED Youngsoo Shin, Takayasu Sakurai
2001	J	`jnl`	Narrow bus encoding for low-power DSP systems. IEEE Trans. Very Large Scale Integr. Syst. Youngsoo Shin, Kiyoung Choi, Young-Hoon Chang
2001	J	`jnl`	Partial bus-invert coding for power optimization of application-specific systems. IEEE Trans. Very Large Scale Integr. Syst. Youngsoo Shin, Soo-Ik Chae, Kiyoung Choi
2001	J	`jnl`	Power-conscious Scheduling for Real-time Embedded Systems Design. VLSI Design Youngsoo Shin, Kiyoung Choi, Takayasu Sakurai
2000	—	`conf`	Narrow bus encoding for low power systems. ASP-DAC Youngsoo Shin, Kiyoung Choi
2000	A	`conf`	Power Optimization of Real-Time Embedded Systems on Variable Speed Processors. ICCAD Youngsoo Shin, Kiyoung Choi, Takayasu Sakurai
2000	A*	`conf`	Schedulability-driven performance analysis of multiple mode embedded real-time systems. DAC Youngsoo Shin, Daehong Kim, Kiyoung Choi
1999	A*	`conf`	Power Conscious Fixed Priority Scheduling for Hard Real-Time Systems. DAC Youngsoo Shin, Kiyoung Choi
1998	J	`jnl`	An Integrated Cosimulation Environment for Heterogeneous Systems Prototyping. Des. Autom. Embed. Syst. Yongjoo Kim, Kyuseok Kim, Youngsoo Shin, Taekyoon Ahn, Kiyoung Choi
1998	A	`conf`	Partial bus-invert coding for power optimization of system level bus. ISLPED Youngsoo Shin, Soo-Ik Chae, Kiyoung Choi
1998	—	`conf`	Rate Assignment for Embedded Reactive Real-Time Systems. EUROMICRO Youngsoo Shin, Kiyoung Choi
1997	—	`conf`	Enforcing Schedulability of Multi-Task Systems by Hardware-Software Codesign. CODES Youngsoo Shin, Kiyoung Choi
1996	C	`conf`	An integrated hardware-software cosimulation environment with automated interface generation. RSP Kyuseok Kim, Yongjoo Kim, Youngsoo Shin, Kiyoung Choi
1996	A	`conf`	Software synthesis through task decomposition by dependency analysis. ICCAD Youngsoo Shin, Kiyoung Choi
1996	—	`conf`	Thread-based software synthesis for embedded system design. ED&TC Youngsoo Shin, Kiyoung Choi
1995	—	`conf`	An integrated hardware-software cosimulation environment for heterogeneous systems prototyping. ASP-DAC Yongjoo Kim, Kyuseok Kim, Youngsoo Shin, Taekyoon Ahn, Wonyong Sung, Kiyoung Choi, Soonhoi Ha
1995	C	`conf`	Efficient Prototyping System Based on Incremental Design and Module-by-Module Verification. ISCAS Yongjoo Kim, Youngsoo Shin, Kyuseok Kim, Jae-Hee Won, Kiyoung Choi