Younghyun Lim

24 papers Journal 13Unranked 11
YearRankTypeTitle / Venue / Authors
2026 J jnl
A Command-Aware Hybrid LDO With Ultra-Small Voltage Droop and Fast Settling Time for Power-Supply-Induced Jitter Mitigation in HBM Interfaces.
IEEE J. Solid State Circuits
Jaeho Kim, Myeongho Han, Hyunjun Song, Jooeun Bang, Younghyun Lim, Jaehyouk Choi
2025 — conf
8.5 A Command-Aware Hybrid LDO for Advanced HBM Interfaces with 150μA Quiescent Current and 20pF On-Chip Capacitor Achieving Sub-10mV Voltage Droop in 400ps Settling Time.
ISSCC
Jaeho Kim, Myeongho Han, Jooeun Bang, Younghyun Lim, Jaehyouk Choi
2025 J jnl
An Area-Efficient CMOS Cross-Coupled LC-VCO Using Nested Intertwined Tail Inductors.
IEEE Trans. Circuits Syst. II Express Briefs
Hyogyoung An, Hyeonjun Nam, Sungjin Kim, Younghyun Lim, Heein Yoon
2024 J jnl
A 12.8-15.0-GHz Low-Jitter Fractional-N Subsampling PLL Using a Voltage-Domain Quantization-Error Cancellation.
IEEE J. Solid State Circuits
Juyeop Kim, Yongwoo Jo, Hangi Park, Taeho Seong, Younghyun Lim, Jaehyouk Choi
2023 J jnl
A Wideband LO Generator for 5G FR1 Bands Using a Single LC-VCO-Based Subsampling PLL and a Ring-VCO-Based Fractional-Resolution Frequency Multiplier.
IEEE J. Solid State Circuits
Yongwoo Jo, Juyeop Kim, Yuhwan Shin, Hangi Park, Chanwoong Hwang, Younghyun Lim, Jaehyouk Choi
2022 J jnl
A Wide-Lock-In-Range and Low-Jitter 12-14.5 GHz SSPLL Using a Low-Power Frequency-Disturbance-Detecting and Correcting Loop.
IEEE J. Solid State Circuits
Younghyun Lim, Juyeop Kim, Yongwoo Jo, Jooeun Bang, Jaehyouk Choi
2021 — conf
32.4 A 104fsrms-Jitter and -61dBc-Fractional Spur 15GHz Fractional-N Subsampling PLL Using a Voltage-Domain Quantization-Error Cancelation Technique.
ISSCC
Juyeop Kim, Yongwoo Jo, Younghyun Lim, Taeho Seong, Hangi Park, Seyeon Yoo, Yongsun Lee, Seojin Choi, Jaehyouk Choi
2021 J jnl
A Low-Jitter and Low-Reference-Spur Ring-VCO- Based Injection-Locked Clock Multiplier Using a Triple-Point Background Calibrator.
IEEE J. Solid State Circuits
Seyeon Yoo, Seojin Choi, Yongsun Lee, Taeho Seong, Younghyun Lim, Jaehyouk Choi
2020 — conf
17.8 A 170MHz-Lock-In-Range and -253dB-FoMjitter 12-to-14.5GHz Subsampling PLL with a 150µW Frequency-Disturbance-Correcting Loop Using a Low-Power Unevenly Spaced Edge Generator.
ISSCC
Younghyun Lim, Juyeop Kim, Yongwoo Jo, Jooeun Bang, Seyeon Yoo, Hangi Park, Heein Yoon, Jaehyouk Choi
2019 — conf
A 0.5V-VIN, 0.29ps-Transient-FOM, and Sub-2mV-Accuracy Adaptive-Sampling Digital LDO Using Single-VCO-Based Edge-Racing Time Quantizer.
VLSI Circuits
Jeonghyun Lee, Jooeun Bang, Younghyun Lim, Jaehyouk Choi
2019 — conf
A 140fsrms-Jitter and -72dBc-Reference-Spur Ring-VCO-Based Injection-Locked Clock Multiplier Using a Background Triple-Point Frequency/Phase/Slope Calibrator.
ISSCC
Seyeon Yoo, Seojin Choi, Yongsun Lee, Taeho Seong, Younghyun Lim, Jaehyouk Choi
2019 — conf
A 76fsrms Jitter and -40dBc Integrated-Phase-Noise 28-to-31GHz Frequency Synthesizer Based on Digital Sub-Sampling PLL Using Optimally Spaced Voltage Comparators and Background Loop-Gain Optimization.
ISSCC
Juyeop Kim, Heein Yoon, Younghyun Lim, Yongsun Lee, Yoonseo Cho, Taeho Seong, Jaehyouk Choi
2019 J jnl
An Ultra-Low-Jitter 22.8-GHz Ring-LC-Hybrid Injection-Locked Clock Multiplier With a Multiplication Factor of 114.
IEEE J. Solid State Circuits
Seojin Choi, Seyeon Yoo, Yongsun Lee, Yongwoo Jo, Jeonghyun Lee, Younghyun Lim, Jaehyouk Choi
2019 J jnl
An Ultra-Low-Jitter, mmW-Band Frequency Synthesizer Based on Digital Subsampling PLL Using Optimally Spaced Voltage Comparators.
IEEE J. Solid State Circuits
Juyeop Kim, Younghyun Lim, Heein Yoon, Yongsun Lee, Hangi Park, Yoonseo Cho, Taeho Seong, Jaehyouk Choi
2018 — conf
153 FSRMS-Integrated-Jitter and 114-Multiplication Factor PVT-Robust 22.8 GHZ Ring-LC-Hybrid Injection-Locked Clock Multiplier.
VLSI Circuits
Seojin Choi, Seyeon Yoo, Yongsun Lee, Yongwoo Jo, Jeonghyun Lee, Younghyun Lim, Jaehyouk Choi
2018 — conf
A -31dBc integrated-phase-noise 29GHz fractional-N frequency synthesizer supporting multiple frequency bands for backward-compatible 5G using a frequency doubler and injection-locked frequency multipliers.
ISSCC
Heein Yoon, Juyeop Kim, Suneui Park, Younghyun Lim, Yongsun Lee, Jooeun Bang, Kyoohyun Lim, Jaehyouk Choi
2018 — conf
A 320µV-Output Ripple and 90ns-Settling Time at 0.5V Supply Digital-Analog-Hybrid LDO Using Multi-Level Gate-Voltage Generator and Fast-Decision PD Detector.
ESSCIRC
Younghyun Lim, Jeonghyun Lee, Yongsun Lee, Seyeon Yoo, Jaehyouk Choi
2018 J jnl
A 65-nm CMOS 2×2 MIMO Multi-Band LTE RF Transceiver for Small Cell Base Stations.
IEEE J. Solid State Circuits
Kyoohyun Lim, Sanghoon Lee, Yongha Lee, Byeongmoo Moon, Hwahyeong Shin, Kisub Kang, Seungbeom Kim, Jinhyeok Lee, Hyungsuk Lee, Hyunchul Shim, Chulhoon Sung, Kumyoung Park, Garam Lee, Minjung Kim, Seokyeong Park, Hyosun Jung, Younghyun Lim, Changhun Song, Jaehyeon Seong, Heechang Cho, Jaehyouk Choi, Jong-Ryul Lee, Sangwoo Han
2018 J jnl
An External Capacitorless Low-Dropout Regulator With High PSR at All Frequencies From 10 kHz to 1 GHz Using an Adaptive Supply-Ripple Cancellation Technique.
IEEE J. Solid State Circuits
Younghyun Lim, Jeonghyun Lee, Suneui Park, Yongwoo Jo, Jaehyouk Choi
2018 — conf
An external-capacitor-less high-PSR low-dropout regulator using an adaptive supply-ripple cancellation technique to the body-gate.
ASP-DAC
Younghyun Lim, Jeonghyun Lee, Suneui Park, Jaehyouk Choi
2017 J jnl
An External Capacitor-Less Ultralow-Dropout Regulator Using a Loop-Gain Stabilizing Technique for High Power-Supply Rejection Over a Wide Range of Load Current.
IEEE Trans. Very Large Scale Integr. Syst.
Younghyun Lim, Jeonghyun Lee, Yongsun Lee, Seong-Sik Song, Hong-Teuk Kim, Ockgoo Lee, Jaehyouk Choi
2017 — conf
An extemal-capacitor-less low-dropout regulator with less than -36dB PSRR at all frequencies from 10kHz to 1GHz using an adaptive supply-ripple cancellation technique to the body-gate.
CICC
Younghyun Lim, Jeonghyun Lee, Suneui Park, Jaehyouk Choi
2016 J jnl
A 0.56-2.92 GHz Wideband and Low Phase Noise Quadrature LO-Generator Using a Single LC-VCO for 2G-4G Multistandard Cellular Transceivers.
IEEE J. Solid State Circuits
Heein Yoon, Yongsun Lee, Younghyun Lim, Geum-Young Tak, Hong-Teuk Kim, Yo-Chuol Ho, Jaehyouk Choi
2016 J jnl
A PVT-Robust and Low-Jitter Ring-VCO-Based Injection-Locked Clock Multiplier With a Continuous Frequency-Tracking Loop Using a Replica-Delay Cell and a Dual-Edge Phase Detector.
IEEE J. Solid State Circuits
Seojin Choi, Seyeon Yoo, Younghyun Lim, Jaehyouk Choi