Younghwi Yang

16 papers C 1Journal 12Unranked 3
YearRankTypeTitle / Venue / Authors
2022 — conf
A 1Tb 3b/Cell 8th-Generation 3D-NAND Flash Memory with 164MB/s Write Throughput and a 2.4Gb/s Interface.
ISSCC
Moosung Kim, Sung-Won Yun, Jungjune Park, Hyun Kook Park, Jungyu Lee, Yeong Seon Kim, Dae-Hoon Na, Sara Choi, Youngsun Song, Jonghoon Lee, Hyun-Jun Yoon, Kangbin Lee, Byunghoon Jeong, Sanglok Kim, Junhong Park, Cheon An Lee, Jaeyun Lee, Ji-Sang Lee, Jin Young Chun, Joonsuc Jang, Younghwi Yang, Seung Hyun Moon, Myung-Hoon Choi, Wontae Kim, Jungsoo Kim, Seok-Min Yoon, Pansuk Kwak, Myunghun Lee, Raehyun Song, Sunghoon Kim, Chiweon Yoon, Dongku Kang, Jin-Yub Lee, Jai Hyuk Song
2019 J jnl
Variation-Tolerant WL Driving Scheme for High-Capacity NAND Flash Memory.
IEEE Trans. Very Large Scale Integr. Syst.
Junyoung Ko, Younghwi Yang, Jisu Kim, Cheon An Lee, Young-Sun Min, Jin-Young Chun, Moosung Kim, Seong-Ook Jung
2017 J jnl
Incremental Bitline Voltage Sensing Scheme With Half-Adaptive Threshold Reference Scheme in MLC PRAM.
IEEE Trans. Circuits Syst. I Regul. Pap.
Junyoung Ko, Younghwi Yang, Jisu Kim, Younghoon Oh, Hyun Kook Park, Seong-Ook Jung
2017 J jnl
Power-Gated 9T SRAM Cell for Low-Energy Operation.
IEEE Trans. Very Large Scale Integr. Syst.
Tae Woo Oh, Hanwool Jeong, Kyoman Kang, Juhyun Park, Younghwi Yang, Seong-Ook Jung
2017 J jnl
SRAM Operational Mismatch Corner Model for Efficient Circuit Design and Yield Analysis.
IEEE Trans. Circuits Syst. I Regul. Pap.
Tae Hoon Choi, Hanwool Jeong, Younghwi Yang, Juhyun Park, Seong-Ook Jung
2016 J jnl
Full-Swing Local Bitline SRAM Architecture Based on the 22-nm FinFET Technology for Low-Voltage Operation.
IEEE Trans. Very Large Scale Integr. Syst.
Kyoman Kang, Hanwool Jeong, Younghwi Yang, Juhyun Park, Ki-Ryong Kim, Seong-Ook Jung
2016 J jnl
Single Bit-Line 7T SRAM Cell for Near-Threshold Voltage Operation With Enhanced Performance and Energy in 14 nm FinFET Technology.
IEEE Trans. Circuits Syst. I Regul. Pap.
Younghwi Yang, Hanwool Jeong, Seung Chul Song, Joseph Wang, Geoffrey Yeap, Seong-Ook Jung
2016 C conf
WL under-driving scheme with decremental step voltage and incremental step time for high-capacity NAND flash memory.
ISCAS
Junyoung Ko, Younghwi Yang, Seong-Ook Jung, Jisu Kim, Cheon An Lee, Young-Sun Min, Jin-Young Chun, Moosung Kim
2015 J jnl
Architecture-Aware Analytical Yield Model for Read Access in Static Random Access Memory.
IEEE Trans. Very Large Scale Integr. Syst.
Heechai Kang, Jisu Kim, Hanwool Jeong, Younghwi Yang, Seong-Ook Jung
2015 J jnl
Offset-Compensated Cross-Coupled PFET Bit-Line Conditioning and Selective Negative Bit-Line Write Assist for High-Density Low-Power SRAM.
IEEE Trans. Circuits Syst. I Regul. Pap.
Hanwool Jeong, Taewon Kim, Younghwi Yang, Taejoong Song, Gyu-Hong Kim, Hyo-Sig Won, Seong-Ook Jung
2015 J jnl
SRAM Design for 22-nm ETSOI Technology: Selective Cell Current Boosting and Asymmetric Back-Gate Write-Assist Circuit.
IEEE Trans. Circuits Syst. I Regul. Pap.
Younghwi Yang, Juhyun Park, Seung Chul Song, Joseph Wang, Geoffrey Yeap, Seong-Ook Jung
2015 J jnl
Single-Ended 9T SRAM Cell for Near-Threshold Voltage Operation With Enhanced Read Performance in 22-nm FinFET Technology.
IEEE Trans. Very Large Scale Integr. Syst.
Younghwi Yang, Juhyun Park, Seung Chul Song, Joseph Wang, Geoffrey Yeap, Seong-Ook Jung
2014 J jnl
One-Sided Static Noise Margin and Gaussian-Tail-Fitting Method for SRAM.
IEEE Trans. Very Large Scale Integr. Syst.
Hanwool Jeong, Younghwi Yang, Junha Lee, Jisu Kim, Seong-Ook Jung
2013 J jnl
Dynamic mixed serial-parallel content addressable memory (DMSP CAM).
Int. J. Circuit Theory Appl.
Mingu Kang, Jisu Kim, Younghwi Yang, Seong-Ook Jung
2012 — conf
Impact of fin thickness and height on read stability / write ability in tri-gate FinFET based SRAM.
ISOCC
Junha Lee, Hanwool Jeong, Younghwi Yang, Jisu Kim, Seong-Ook Jung
2012 — conf
Static read stability and write ability metrics in FinFET based SRAM considering read and write-assist circuits.
ICECS
Hanwool Jeong, Younghwi Yang, Junha Lee, Jisu Kim, Seong-Ook Jung