Young-Soo Sohn

39 papers Journal 15Unranked 24

Year	Rank	Type	Title / Venue / Authors
2026	—	`conf`	15.6 A 36GB 3.3TB/S HBM4 DRAM with Per-Channel TSV RDQS Auto Calibration and Fully-Programmable MBIST. ISSCC Sunghwan Joo, Jinyeon Kim, Yongsun Lee, Ji-Young Kim, Youngsik Lee, Yong-Min Kim, Chi Sung Oh, Kyu-Ha Shim, Haesuk Lee, Young-Yong Byun, Changhyun Bae, Joohwan Kim, Je-Min Ryu, Shin-Haeng Kang, Jaehoon Lee, Young-Uk Chang, Jaekyung Lee, Jong Tae Hwang, Daehwan Seo, Ki-Heon Na, Young Guen Song, Daihyun Lim, Kyung-Soo Ha, Young-Soo Sohn, Sangjoon Hwang
2024	—	`conf`	13.2 A 32Gb 8.0Gb/s/pin DDR5 SDRAM with a Symmetric-Mosaic Architecture in a 5 ISSCC IkJoon Choi, Seunghwan Hong, Kihyun Kim, Jeongsik Hwang, Seunghan Woo, Young-Sang Kim, Cheongryong Cho, Eun-Young Lee, Hun-Jae Lee, Min-su Jung, Hee-Yun Jung, Ju-Seong Hwang, Junsub Yoon, Wonmook Lim, Hyeong-Jin Yoo, Won-Ki Lee, Jung-Kyun Oh, Dong-Su Lee, Jong-eun Lee, Jun-Hyung Kim, Young-Kwan Kim, Su-Jin Park, Byung-Kyu Ho, Byongwook Na, Hye-In Choi, Chung-Ki Lee, Soo-Jung Lee, Hyunsung Shin, Young-Kyu Lee, Jang-Woo Ryu, Sangwoong Shin, Sungchul Park, Daihyun Lim, Seung-Jun Bae, Young-Soo Sohn, Tae-Young Oh, Sangjoon Hwang
2023	—	`conf`	A 1.01V 8.5Gb/s/pin 16Gb LPDDR5x SDRAM with Self-Pre-Emphasized Stacked-Tx, Supply Voltage Insensitive Rx, and Optimized Clock Using 4th-Generation 10nm DRAM Process for High-Speed and Low-Power Applications. A-SSCC Hyun-A. Ahn, Yoo-Chang Sung, Yong-Hun Kim, Janghoo Kim, Kihan Kim, Donghun Lee, Young-Gil Go, Jae-Woo Lee, Jae-Woo Jung, Yong-Hyun Kim, Garam Choi, Jun-Seo Park, Bo-Hyeon Lee, Jin-Hyeok Baek, Daesik Moon, Daihyun Lim, Seung-Jun Bae, Young-Soo Sohn, Changsik Yoo, Tae-Young Oh
2023	—	`conf`	A 1.1V 6.4Gb/s/pin 24-Gb DDR5 SDRAM with a Highly-Accurate Duty Corrector and NBTI-Tolerant DLL. ISSCC Daehyun Kwon, Heon Su Jeong, Jaemin Choi, Wijong Kim, Jae Woong Kim, Junsub Yoon, Jungmin Choi, Sanguk Lee, Hyunsub Norbert Rie, Jin-Il Lee, Jongbum Lee, Taeseong Jang, Junhyung Kim, Sanghee Kang, Jung-Bum Shin, Yanggyoon Loh, Chang-Yong Lee, Junmyung Woo, Hye-Seung Yu, Changhyun Bae, Reum Oh, Young-Soo Sohn, Changsik Yoo, Jooyoung Lee
2021	—	`conf`	Aquabolt-XL: Samsung HBM2-PIM with in-memory processing for ML accelerators and beyond. HCS Jin Hyun Kim, Shinhaeng Kang, Sukhan Lee, Hyeonsu Kim, Woongjae Song, Yuhwan Ro, Seungwon Lee, David Wang, Hyunsung Shin, BengSeng Phuah, Jihyun Choi, Jinin So, Yeongon Cho, Joon-Ho Song, Jangseok Choi, Jeonghyeon Cho, Kyomin Sohn, Young-Soo Sohn, Kwang-Il Park, Nam Sung Kim
2021	—	`conf`	Industry's First 7.2 Gbps 512GB DDR5 Module. HCS Sung Joo Park, Jonghoon J. Kim, Kun Joo, Young-Ho Lee, Kyoungsun Kim, Young-Tae Kim, Woo-Jin Na, IkJoon Choi, Hye-Seung Yu, Wonyoung Kim, Ju-Yeon Jung, Jaejun Lee, Dohyung Kim, Young-Uk Chang, Gong-Heum Han, Hangi-Jung, Sunwon Kang, Jeonghyeon Cho, Hoyoung Song, Tae-Young Oh, Young-Soo Sohn, Sangjoon Hwang, Jooyoung Lee
2020	—	`conf`	22.2 An 8.5Gb/s/pin 12Gb-LPDDR5 SDRAM with a Hybrid-Bank Architecture using Skew-Tolerant, Low-Power and Speed-Boosting Techniques in a 2nd generation 10nm DRAM Process. ISSCC Hyung-Joon Chi, Chang-Kyo Lee, Junghwan Park, Jin-Seok Heo, Jaehoon Jung, Dongkeon Lee, Dae-Hyun Kim, Dukha Park, Kihan Kim, Sang-Yun Kim, Jinsol Park, Hyunyoon Cho, Sukhyun Lim, YeonKyu Choi, Youngil Lim, Daesik Moon, Geuntae Park, Jin-Hun Jang, Kyungho Lee, Isak Hwang, Cheol Kim, Younghoon Son, Gil-Young Kang, Kiwon Park, Seungjun Lee, Su-Yeon Doo, Chang-Ho Shin, Byongwook Na, Ji-Suk Kwon, Kyung Ryun Kim, Hye-In Choi, Seouk-Kyu Choi, Soobong Chang, Wonil Bae, Hyuck-Joon Kwon, Young-Soo Sohn, Seung-Jun Bae, Kwang-Il Park, Jung-Bae Lee
2020	J	`jnl`	A 7.5 Gb/s/pin 8-Gb LPDDR5 SDRAM With Various High-Speed and Low-Power Techniques. IEEE J. Solid State Circuits Kyung-Soo Ha, SeungSeob Lee, Youn-Sik Park, Hyuck-Joon Kwon, Tae-Young Oh, Young-Soo Sohn, Seung-Jun Bae, Kwang-Il Park, Jung-Bae Lee, Chang-Kyo Lee, Dongkeon Lee, Daesik Moon, Hyong-Ryol Hwang, Dukha Park, Young-Hwa Kim, Young Hoon Son, Byongwook Na
2019	J	`jnl`	A 16-Gb, 18-Gb/s/pin GDDR6 DRAM With Per-Bit Trainable Single-Ended DFE and PLL-Less Clocking. IEEE J. Solid State Circuits Young-Ju Kim, Hye-Jung Kwon, Su-Yeon Doo, Min-Su Ahn, Yong-Hun Kim, Yong Jae Lee, Dong-Seok Kang, Sung-Geun Do, Chang-Yong Lee, Gun-hee Cho, Jae-Koo Park, Jae-Sung Kim, Kyung-Bae Park, Seung-Hoon Oh, Sang-Yong Lee, Ji-Hak Yu, Ki-Hun Yu, Chul-Hee Jeon, Sang-Sun Kim, Hyun-Soo Park, Jeong-Woo Lee, Seung-Hyun Cho, Keon-woo Park, Yong-Jun Kim, Young-Hun Seo, Chang-Ho Shin, Chan-Yong Lee, Sam-Young Bang, Youn-Sik Park, Seouk-Kyu Choi, Byung-Cheol Kim, Gong-Heum Han, Seung-Jun Bae, Hyuk-Jun Kwon, Jung-Hwan Choi, Young-Soo Sohn, Kwang-Il Park, Seong-Jin Jang, Gyo-Young Jin
2019	—	`conf`	A 5Gb/s/pin 16Gb LPDDR4/4X Reconfigurable SDRAM with Voltage-High Keeper and a Prediction-based Fast-tracking ZQ Calibration. VLSI Circuits Jin-Seok Heo, Kihan Kim, Dong-Hoon Lee, Chang-Kyo Lee, Daesik Moon, Kiho Kim, Jin-Hyeok Baek, Sung-Woo Yoon, Hui-Kap Yang, Kyungryun Kim, Youngjae Kim, Bokgue Park, Su-Jin Park, Joung-Wook Moon, Jae-Hyung Lee, Yun-Sik Park, Soobong Jang, Seok-Hun Hyun, Hyuck-Joon Kwon, Jung-Hwan Choi, Young-Soo Sohn, Seung-Jun Bae, Kwang-Il Park, Jung-Bae Lee
2019	—	`conf`	A 7.5Gb/s/pin LPDDR5 SDRAM With WCK Clocking and Non-Target ODT for High Speed and With DVFS, Internal Data Copy, and Deep-Sleep Mode for Low Power. ISSCC Kyung-Soo Ha, Chang-Kyo Lee, Dongkeon Lee, Daesik Moon, Jin-Hun Jang, Hyong-Ryol Hwang, Hyung-Joon Chi, Junghwan Park, Seungjun Shin, Dukha Park, Sang-Yun Kim, Sukhyun Lim, Kiwon Park, YeonKyu Choi, Young-Hwa Kim, Younghoon Son, Hyunyoon Cho, Byongwook Na, Hyo-Joo Ahn, SeungSeob Lee, Seouk-Kyu Choi, Youn-Sik Park, Seok-Hun Hyun, Soobong Chang, Hyuck-Joon Kwon, Jung-Hwan Choi, Tae-Young Oh, Young-Soo Sohn, Kwang-Il Park, Seong-Jin Jang
2018	—	`conf`	A 16Gb 18Gb/S/pin GDDR6 DRAM with per-bit trainable single-ended DFE and PLL-less clocking. ISSCC Young-Ju Kim, Hye-Jung Kwon, Su-Yeon Doo, Yoon-Joo Eom, Young-Sik Kim, Min-Su Ahn, Yong-Hun Kim, Sang-Hoon Jung, Sung-Geun Do, Chang-Yong Lee, Jae-Sung Kim, Dong-Seok Kang, Kyung-Bae Park, Jung-Bum Shin, Jong-Ho Lee, Seung-Hoon Oh, Sang-Yong Lee, Ji-Hak Yu, Ji-Suk Kwon, Ki-Hun Yu, Chul-Hee Jeon, Sang-Sun Kim, Min-Woo Won, Gun-hee Cho, Hyun-Soo Park, Hyung-Kyu Kim, Jeong-Woo Lee, Seung-Hyun Cho, Keon-woo Park, Jae-Koo Park, Yong Jae Lee, Yong-Jun Kim, Young-Hun Seo, Beob-Rae Cho, Chang-Ho Shin, Chan-Yong Lee, Youngseok Lee, Yoon-Gue Song, Sam-Young Bang, Youn-Sik Park, Seouk-Kyu Choi, Byeong-Cheol Kim, Gong-Heum Han, Seung-Jun Bae, Hyuk-Jun Kwon, Jung-Hwan Choi, Young-Soo Sohn, Kwang-Il Park, Seong-Jin Jang
2018	—	`conf`	A 16Gb LPDDR4X SDRAM with an NBTI-tolerant circuit solution, an SWD PMOS GIDL reduction technique, an adaptive gear-down scheme and a metastable-free DQS aligner in a 10nm class DRAM process. ISSCC Ki Chul Chun, Yonggyu Chu, Jin-Seok Heo, Tae-sung Kim, Soohwan Kim, Hui-Kap Yang, Mi-Jo Kim, Chang-Kyo Lee, Ju-Hwan Kim, Hyunchul Yoon, Chang-Ho Shin, Sang-uhn Cha, Hyung-Jin Kim, Young-Sik Kim, Kyungryun Kim, Young-Ju Kim, Won-Jun Choi, Daesik Yim, Inkyu Moon, Young-Ju Kim, Junha Lee, Young Choi, Yongmin Kwon, Sung-Won Choi, Jung-Wook Kim, Yoon-Suk Park, Woongdae Kang, Jinil Chung, Seunghyun Kim, Yesin Ryu, Seong-Jin Cho, Hoon Shin, Hangyun Jung, Sanghyuk Kwon, Kyuchang Kang, Jongmyung Lee, Yujung Song, Youngjae Kim, Eun-Ah Kim, Kyung-Soo Ha, Kyoung-Ho Kim, Seok-Hun Hyun, Seung-Bum Ko, Jung-Hwan Choi, Young-Soo Sohn, Kwang-Il Park, Seong-Jin Jang
2018	—	`conf`	A sub-0.85V, 6.4GBP/S/Pin TX-Interleaved Transceiver with Fast Wake-Up Time Using 2-Step Charging Control and VOHCalibration in 20NM DRAM Process. VLSI Circuits Jin-Hyeok Baek, Chang-Kyo Lee, Kiho Kim, Daesik Moon, Gil-Hoon Cha, Jin-Seok Heo, Min-Su Ahn, Dong-Ju Kim, Jae-Joon Song, Seokhong Kwon, Jongmin Kim, Kyung-Soo Kim, Jinoh Ahn, Jeong-Sik Nam, Byung-Cheol Kim, Jeong-Hyeon Cho, Jeonghoon Oh, Seung-Jun Bae, Indal Song, Seok-Hun Hyun, Ilgweon Kim, Hyuck-Joon Kwon, Young-Soo Sohn, Jung-Hwan Choi, Kwang-Il Park, Seong-Jin Jang
2018	—	`conf`	An Enhanced Built-off-Test Transceiver with Wide-range, Self-calibration Engine for 3.2 Gb/s/pin DDR4 SDRAM. A-SSCC Joung-Wook Moon, Hye-Sung Yoo, Hundai Choi, Il-Won Park, Seok-Yong Kang, Jun-Bae Kim, Haeyoung Chung, Kiho Kim, Dong-Hun Lee, Ki-Jae Song, Seok-Hun Hyun, Indal Song, Young-Soo Sohn, Yong-Ho Cho, Jung-Hwan Choi, Kwang-Il Park, Seong-Jin Jang
2018	J	`jnl`	Dual-Loop Two-Step ZQ Calibration for Dynamic Voltage-Frequency Scaling in LPDDR4 SDRAM. IEEE J. Solid State Circuits Chang-Kyo Lee, Junha Lee, Kiho Kim, Jin-Seok Heo, Jin-Hyeok Baek, Gil-Hoon Cha, Daesik Moon, Dong-Hun Lee, Jong-Wook Park, Seunseob Lee, Si-Hyeong Cho, Young-Ryeol Choi, Kyung-Soo Ha, Eunsung Seo, Youn-Sik Park, Seung-Jun Bae, Indal Song, Seok-Hun Hyun, Hyuck-Joon Kwon, Young-Soo Sohn, Jung-Hwan Choi, Kwang-Il Park, Seong-Jin Jang
2017	J	`jnl`	A 1.2 V 20 nm 307 GB/s HBM DRAM With At-Speed Wafer-Level IO Test Scheme and Adaptive Refresh Considering Temperature Distribution. IEEE J. Solid State Circuits Kyomin Sohn, Won-Joo Yun, Reum Oh, Chi-Sung Oh, Seong-Young Seo, Min-Sang Park, Dong-Hak Shin, Won-Chang Jung, Sang-Hoon Shin, Je-Min Ryu, Hye-Seung Yu, Jae-Hun Jung, Hyunui Lee, Seok-Yong Kang, Young-Soo Sohn, Jung-Hwan Choi, Yong-Cheol Bae, Seong-Jin Jang, Gyo-Young Jin
2017	—	`conf`	Dual-loop 2-step ZQ calibration for dedicated power supply voltage in LPDDR4 SDRAM. A-SSCC Chang-Kyo Lee, Junha Lee, Kiho Kim, Jin-Seok Heo, Gil-Hoon Cha, Jin-Hyeok Baek, Daesik Moon, Yoon-Joo Eom, Tae-sung Kim, Hyunyoon Cho, Young Hoon Son, Seonghwan Kim, Jong-Wook Park, Sewon Eom, Si-Hyeong Cho, Young-Ryeol Choi, SeungSeob Lee, Kyoung-Soo Ha, Youngseok Kim, Bo-Tak Lim, Dae-Hee Jung, Eungsung Seo, Kyoung-Ho Kim, Yoon-Gyu Song, Youn-Sik Park, Tae-Young Oh, Seung-Jun Bae, Indal Song, Seok-Hun Hyun, Joon-Young Park, Hyuck-Joon Kwon, Young-Soo Sohn, Jung-Hwan Choi, Kwang-Il Park, Seong-Jin Jang
2016	—	`conf`	18.1 A 20nm 9Gb/s/pin 8Gb GDDR5 DRAM with an NBTI monitor, jitter reduction techniques and improved power distribution. ISSCC Hye-Yoon Joo, Seung-Jun Bae, Young-Soo Sohn, Young-Sik Kim, Kyung-Soo Ha, Min-Su Ahn, Young-Ju Kim, Yong-Jun Kim, Ju-Hwan Kim, Won-Jun Choi, Chang-Ho Shin, Soo Hwan Kim, Byeong-Cheol Kim, Seung-Bum Ko, Kwang-Il Park, Seong-Jin Jang, Gyo-Young Jin
2016	—	`conf`	18.2 A 1.2V 20nm 307GB/s HBM DRAM with at-speed wafer-level I/O test scheme and adaptive refresh considering temperature distribution. ISSCC Kyomin Sohn, Won-Joo Yun, Reum Oh, Chi-Sung Oh, Seong-Young Seo, Min-Sang Park, Dong-Hak Shin, Won-Chang Jung, Sang-Hoon Shin, Je-Min Ryu, Hye-Seung Yu, Jae-Hun Jung, Kyung-Woo Nam, Seouk-Kyu Choi, Jae-Wook Lee, Uksong Kang, Young-Soo Sohn, Jung-Hwan Choi, Chi-Wook Kim, Seong-Jin Jang, Gyo-Young Jin
2016	J	`jnl`	A 40 mV-Differential-Channel-Swing Transceiver Using a RX Current-Integrating TIA and a TX Pre-Emphasis Equalizer With a CML Driver at 9 Gb/s. IEEE Trans. Circuits Syst. I Regul. Pap. Il-Min Yi, Soo-Min Lee, Seung-Jun Bae, Young-Soo Sohn, Jung-Hwan Choi, Seong-Jin Jang, Byungsub Kim, Jae-Yoon Sim, Hong-June Park
2016	—	`conf`	A low-EMI four-bit four-wire single-ended DRAM interface by using a three-level balanced coding scheme. VLSI Circuits Il-Min Yi, Seung-Jun Bae, Min-Kyun Chae, Soo-Min Lee, Young Jae Jang, Young-Chul Cho, Young-Soo Sohn, Jung-Hwan Choi, Seong-Jin Jang, Byungsub Kim, Jae-Yoon Sim, Hong-June Park
2014	J	`jnl`	A 40-mV-Swing Single-Ended Transceiver for TSV with a Switched-Diode RX Termination. IEEE Trans. Circuits Syst. II Express Briefs Il-Min Yi, Soo-Min Lee, Seung-Jun Bae, Young-Soo Sohn, Jung-Hwan Choi, Byungsub Kim, Jae-Yoon Sim, Hong-June Park
2012	—	`conf`	An 8GB/s quad-skew-cancelling parallel transceiver in 90nm CMOS for high-speed DRAM interface. ISSCC Young-Sik Kim, Seon-Kyoo Lee, Seung-Jun Bae, Young-Soo Sohn, Jung-Bae Lee, Joo-Sun Choi, Hong-June Park, Jae-Yoon Sim
2012	—	`conf`	An on-chip TSV emulation using metal bar surrounded by metal ring to develop interface circuits. ISOCC Il-Min Yi, Seung-Jun Bae, Young-Soo Sohn, Jae-Yoon Sim, Hong-June Park
2011	—	`conf`	A 40nm 2Gb 7Gb/s/pin GDDR5 SDRAM with a programmable DQ ordering crosstalk equalizer and adjustable clock-tracking BW. ISSCC Seung-Jun Bae, Young-Soo Sohn, Tae-Young Oh, Si-Hong Kim, Yun-Seok Yang, Dae-Hyun Kim, Sang-Hyup Kwak, Ho-Seok Seol, Chang-Ho Shin, Min-Sang Park, Gong-Heom Han, Byeong-Cheol Kim, Yong-Ki Cho, Hye-Ran Kim, Su-Yeon Doo, Young-Sik Kim, Dong-Seok Kang, Young-Ryeol Choi, Sam-Young Bang, Sun-Young Park, Yong-Jae Shin, Gil-Shin Moon, Cheol-Goo Park, Woo-Seop Kim, Hyang-Ja Yang, Jeong-Don Lim, Kwang-Il Park, Joo-Sun Choi, Young-Hyun Jun
2011	J	`jnl`	A 7 Gb/s/pin 1 Gbit GDDR5 SDRAM With 2.5 ns Bank to Bank Active Time and No Bank Group Restriction. IEEE J. Solid State Circuits Tae-Young Oh, Young-Soo Sohn, Seung-Jun Bae, Min-Sang Park, Ji-Hoon Lim, Yong-Ki Cho, Dae-Hyun Kim, Dong-Min Kim, Hye-Ran Kim, Hyun-Joong Kim, Jin-hyun Kim, Jin-Kook Kim, Young-Sik Kim, Byeong-Cheol Kim, Sang-Hyup Kwak, Jae-Hyung Lee, Jae-Young Lee, Chang-Ho Shin, Yun-Seok Yang, Beom-Sig Cho, Sam-Young Bang, Hyang-Ja Yang, Young-Ryeol Choi, Gil-Shin Moon, Cheol-Goo Park, Seokwon Hwang, Jeong-Don Lim, Kwang-Il Park, Joo-Sun Choi, Young-Hyun Jun
2011	J	`jnl`	A Single-Loop SS-LMS Algorithm With Single-Ended Integrating DFE Receiver for Multi-Drop DRAM Interface. IEEE J. Solid State Circuits Hyung-Joon Chi, Jae-Seung Lee, Seong-Hwan Jeon, Seung-Jun Bae, Young-Soo Sohn, Jae-Yoon Sim, Hong-June Park
2010	—	`conf`	A 7Gb/s/pin GDDR5 SDRAM with 2.5ns bank-to-bank active time and no bank-group restriction. ISSCC Tae-Young Oh, Young-Soo Sohn, Seung-Jun Bae, Min-Sang Park, Ji-Hoon Lim, Yong-Ki Cho, Dae-Hyun Kim, Dong-Min Kim, Hye-Ran Kim, Hyun-Joong Kim, Jin-hyun Kim, Jin-Kook Kim, Young-Sik Kim, Byeong-Cheol Kim, Sang-Hyup Kwak, Jae-Hyung Lee, Jae-Young Lee, Chang-Ho Shin, Yun-Seok Yang, Beom-Sig Cho, Sam-Young Bang, Hyang-Ja Yang, Young-Ryeol Choi, Gil-Shin Moon, Cheol-Goo Park, Seokwon Hwang, Jeong-Don Lim, Kwang-Il Park, Joo-Sun Choi, Young-Hyun Jun
2010	—	`conf`	A crosstalk-and-ISI equalizing receiver in 2-drop single-ended SSTL memory channel. CICC Jun-Hyun Bae, Young-Soo Sohn, Seung-Jun Bae, Kwang-Il Park, Joo-Sun Choi, Young-Hyun Jun, Jae-Yoon Sim, Hong-June Park
2009	J	`jnl`	A 2-Gb/s CMOS Integrating Two-Tap DFE Receiver for Four-Drop Single-Ended Signaling. IEEE Trans. Circuits Syst. I Regul. Pap. Seung-Jun Bae, Hyung-Joon Chi, Young-Soo Sohn, Jae-Seung Lee, Jae-Yoon Sim, Hong-June Park
2008	—	`conf`	A 60nm 6Gb/s/pin GDDR5 Graphics DRAM with Multifaceted Clocking and ISI/SSN-Reduction Techniques. ISSCC Seung-Jun Bae, Young-Soo Sohn, Kwang-Il Park, Kyoung-Ho Kim, Dae-Hyun Chung, Jingook Kim, Si-Hong Kim, Min-Sang Park, Jae-Hyung Lee, Sam-Young Bang, Ho-Kyung Lee, In-Soo Park, Jae-Sung Kim, Dae-Hyun Kim, Hye-Ran Kim, Yong-Jae Shin, Cheol-Goo Park, Gil-Shin Moon, Ki-Woong Yeom, Kang-Young Kim, Jae-Young Lee, Hyang-Ja Yang, Seong-Jin Jang, Joo-Sun Choi, Young-Hyun Jun, Kinam Kim
2007	J	`jnl`	Design and fabrication of a vibration sensor using a conductive ball. Microelectron. J. Yong-Soo Cho, Sung-Wook Jang, Young-Soo Sohn, Sie-Young Choi
2006	J	`jnl`	A 20-gb/s 256-mb DRAM with an inductorless quadrature PLL and a cascaded pre-emphasis transmitter. IEEE J. Solid State Circuits Kyu-Hyoun Kim, Young-Soo Sohn, Chan-Kyoung Kim, Moon-Sook Park, Dong-Jin Lee, Woo-Seop Kim, Changhyun Kim
2006	J	`jnl`	Field emission characteristics of an oxidized porous polysilicon field emitter using the electrochemical oxidation process. Microelectron. J. Soon-il Kwon, Sung-Won You, Young-Soo Sohn, Yong-Soo Cho, Byung-Nam Park, Sie-Young Choi
2005	J	`jnl`	A VCDL-based 60-760-MHz dual-loop DLL with infinite phase-shift capability and adaptive-bandwidth scheme. IEEE J. Solid State Circuits Seung-Jun Bae, Hyung-Joon Chi, Young-Soo Sohn, Hong-June Park
2003	—	`conf`	A 2.2 Gbps CMOS look-ahead DFE receiver for multidrop channel with pin-to-pin time skew compensation. CICC Young-Soo Sohn, Seung-Jun Bae, Hong-June Park, Changhyun Kim, Soo-In Cho
2002	J	`jnl`	A CMOS transceiver for DRAM bus system with a demultiplexed equalization scheme. IEEE J. Solid State Circuits Jae-Yoon Sim, Jang-Jin Nam, Young-Soo Sohn, Hong-June Park, Chang-Hyun Kim, Soo-In Cho
1999	J	`jnl`	A 1-Gb/s bidirectional I/O buffer using the current-mode scheme. IEEE J. Solid State Circuits Jae-Yoon Sim, Young-Soo Sohn, Seung-Chan Heo, Hong-June Park, Soo-In Cho