Young-Ho Kwak

14 papers Journal 9Unranked 5
YearRankTypeTitle / Venue / Authors
2025 J jnl
A Variation-Robust 20-Gb/s Wireline Transceiver With Real-Time Calibration in 28-nm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap.
Sangwan Lee, Hyeongmin Seo, Wookjin Shin, Dongju Yang, Gaeryun Sung, Sanghun Lee, Dong-Ho Choi, Young-Ho Kwak, Soon-Jae Won, Ickhyun Song, Jaeduk Han
2024 J jnl
A Variation-Tolerant Voltage-Mode Transmitter With 3+1 Tap FFE in 28-nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs
Wookjin Shin, Hyeongmin Seo, Sangwan Lee, Dong-Ho Choi, Young-Ho Kwak, Soon-Jae Won, Jaeduk Han
2013 J jnl
10-315-MHz Cascaded Hybrid Phase-Locked Loop for Pixel Clock Generation.
IEEE Trans. Very Large Scale Integr. Syst.
Minyoung Song, Young-Ho Kwak, Sunghoon Ahn, Hojin Park, Chulwoo Kim
2013 J jnl
A 1.62 Gb/s-2.7 Gb/s Referenceless Transceiver for DisplayPort v1.1a With Weighted Phase and Frequency Detection.
IEEE Trans. Circuits Syst. I Regul. Pap.
Junyoung Song, Inhwa Jung, Minyoung Song, Young-Ho Kwak, Sewook Hwang, Chulwoo Kim
2013 J jnl
A 20 Gb/s Clock and Data Recovery With a Ping-Pong Delay Line for Unlimited Phase Shifting in 65 nm CMOS Process.
IEEE Trans. Circuits Syst. I Regul. Pap.
Young-Ho Kwak, Yongtae Kim, Sewook Hwang, Chulwoo Kim
2012 J jnl
A 3.5 GHz Spread-Spectrum Clock Generator With a Memoryless Newton-Raphson Modulation Profile.
IEEE J. Solid State Circuits
Sewook Hwang, Minyoung Song, Young-Ho Kwak, Inhwa Jung, Chulwoo Kim
2011 J jnl
250 Mbps-5 Gbps Wide-Range CDR With Digital Vernier Phase Shifting and Dual-Mode Control in 0.13 μ m CMOS.
IEEE J. Solid State Circuits
Sang-Yoon Lee, Hyung-Rok Lee, Young-Ho Kwak, Woo-Seok Choi, Byoung-Joo Yoo, Daeyun Shim, Chulwoo Kim, Deog-Kyoon Jeong
2011 — conf
A 0.076mm
ISSCC
Sewook Hwang, Minyoung Song, Young-Ho Kwak, Inhwa Jung, Chulwoo Kim
2010 J jnl
A Gb/s+ Slew-Rate/Impedance-Controlled Output Driver With Single-Cycle Compensation Time.
IEEE Trans. Circuits Syst. II Express Briefs
Young-Ho Kwak, Inhwa Jung, Chulwoo Kim
2009 — conf
A 10MHz to 315MHz cascaded hybrid PLL with piecewise linear calibrated TDC.
CICC
Minyoung Song, Young-Ho Kwak, Sunghoon Ahn, Wooseok Kim, Byeongha Park, Chulwoo Kim
2008 — conf
A slew-rate controlled output driver with one-cycle tuning time.
ASP-DAC
Young-Ho Kwak, Inhwa Jung, Chulwoo Kim
2007 — conf
A One-Cycle Lock Time Slew-Rate-Controlled Output Driver.
ISSCC
Young-Ho Kwak, Inhwa Jung, Hyung-Dong Lee, Young-Jung Choi, Yogendera Kumar, Chulwoo Kim
2006 J jnl
A 120-MHz-1.8-GHz CMOS DLL-Based Clock Generator for Dynamic Frequency Scaling.
IEEE J. Solid State Circuits
Jin-Han Kim, Young-Ho Kwak, Moo-young Kim, Soo-Won Kim, Chulwoo Kim
2005 — conf
Differential Pass Transistor Pulsed Latch.
SoCC
Moo-young Kim, Inhwa Jung, Young-Ho Kwak, Sunghoon Ahn, Chulwoo Kim