Young-Chan Jang

48 papers C 2Journal 35Unranked 11
YearRankTypeTitle / Venue / Authors
2026 J jnl
A 6-Gsps/Lane MIPI C-PHY Receiver With Glitch Noise-Free Clock Recovery Circuit.
IEEE Access
Dong-Seob Shin, Jong-Ho Park, Jaeho Bae, Young-Chan Jang
2025 J jnl
A 1.62 - 10-Gb/s CDR Using Wide-Range VCO With Linearized KVCO.
IEEE Trans. Circuits Syst. II Express Briefs
Dong-Seob Shin, Young-Chan Jang
2025 J jnl
A 1.8-V 95.8-dB SNDR Incremental Delta-Sigma ADC With Analog Noise Reduction Techniques for Sensor ROIC.
IEEE Access
Juncheol Kim, Young-Chan Jang
2025 J jnl
A second-order CIFF delta-sigma modulator with wide input voltage range using double feedback integration.
Microelectron. J.
Neungin Jeon, Juncheol Kim, Seong Bok, Young-Chan Jang
2025 J jnl
An 88 dB SNDR second-order CIFF delta-sigma modulator with 3-bit quantizer and capacitor sharing circuit.
Microelectron. J.
Wonkyu Do, Juncheol Kim, Hoyong Jung, Neungin Jeon, Young-Chan Jang
2024 — conf
3-Gsymbol/s/lane MIPI C-PHY Receiver with Feed-forward Level-dependent Equalization.
ISOCC
Jong-Ho Park, Minjun Cho, Juncheol Kim, Haewoon Son, Hyeon-Ho Kim, Young-Chan Jang
2024 J jnl
A 1-kS/s 12-bit SAR ADC With Burst Conversion for Anti-Leakage Current.
IEEE Access
Haewoon Son, Hoyong Jung, Young-Chan Jang
2024 J jnl
A 24-Gb/s MIPI C-/D-PHY Receiver Bridge Chip With Phase Error Calibration Supporting FPGA-Based Frame Grabber.
IEEE Trans. Very Large Scale Integr. Syst.
Changmin Song, Hoyong Jung, KyoungSeop Chang, Kwanglae Cho, Seungyong Yoon, Young-Chan Jang
2024 — conf
Clock Recovery Circuit for 3-Gsymbol/s/lane MIPI C-PHY Receiver.
ISOCC
Dong-Seob Shin, Jong-Ho Park, Changmin Song, Seong-Yun Kim, Hyeonseok Lee, Jinyeong Lee, Young-Chan Jang
2023 — conf
1-kS/s 12-bit SAR ADC with Burst Conversion.
ISOCC
Haewoon Son, WonSeok Yang, Hoyong Jung, Young-Chan Jang
2023 C conf
4.5 Gsymbol/s/lane MIPI C-PHY Receiver with Channel Mismatch Calibration.
ISCAS
Changmin Song, Minjun Cho, Sihan Kim, Young-Chan Jang
2023 — conf
A 10-Gb/s Dual-Loop Reference-less CDR with FD Controller.
ISOCC
Sihan Kim, Changmin Song, Jinseok Kim, Yonghun Oh, Changwan Kim, Young-Chan Jang
2023 — conf
First-order Continuous Time Delta-sigma Modulator with 3-bit SAR ADC and PNM DAC.
ISOCC
Hye-Min Shin, Hae-Won Son, Tai-Soon Park, Tae-Woo Oh, Young-Chan Jang
2022 — conf
Second-order Incremental Delta-sigma Modulator with 3-bit SAR ADC and Capacitor Sharing Scheme.
ISOCC
Wonkyu Do, Neungin Jeon, Hoyong Jung, Young-Chan Jang
2021 — conf
A 0.2 ‒ 1.2GHz Adaptive Bandwidth PLL with Controllable KVCO.
ISOCC
Changmin Song, Se-Hyeon Cho, Young-Chan Jang
2021 J jnl
A 3.0 Gsymbol/s/lane MIPI C-PHY Receiver with Adaptive Level-Dependent Equalizer for Mobile CMOS Image Sensor.
Sensors
Seokwon Choi, Changmin Song, Young-Chan Jang
2021 — conf
Second-order Noise Shaping SAR ADC using 3-input Comparator with Voltage Gain Calibration.
ISOCC
Hoyong Jung, Neungin Jeon, Young-Chan Jang
2020 J jnl
A 6.84 Gbps/lane MIPI C-PHY Transceiver Bridge Chip With Level-Dependent Equalization.
IEEE Trans. Circuits Syst.
Pil-Ho Lee, Young-Chan Jang
2019 J jnl
A 10-bit 10-MS/s single-ended asynchronous SAR ADC with CDAC boosting common-mode voltage and controlling input voltage range.
IEICE Electron. Express
Jisu Son, Young-Chan Jang
2019 J jnl
A 20-Gb/s Receiver Bridge Chip With Auto-Skew Calibration for MIPI D-PHY Interface.
IEEE Trans. Consumer Electron.
Pil-Ho Lee, Young-Chan Jang
2019 J jnl
A 3Gbps/Lane MIPI D-PHY Transmission Buffer Chip.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Pil-Ho Lee, Young-Chan Jang
2018 — conf
12-bit 20M-S/s SAR ADC using C-R DAC and Capacitor Calibration.
ISOCC
Eunji Youn, Young-Chan Jang
2017 C conf
0.5 kHz-32 MHz digital fractional-N frequency synthesizer with burst-frequency switch.
ISCAS
Seung-Hun Shin, Pil-Ho Lee, Jin-Woo Park, Yu-Jeong Hwang, Young-Chan Jang
2017 J jnl
A 10 Gbps D-PHY Transmitter Bridge Chip for FPGA-Based Frame Generator Supporting MIPI DSI of Mobile Display.
IEICE Trans. Electron.
Ho-Seong Kim, Pil-Ho Lee, Jin-Wook Han, Seung-Hun Shin, Seung-Wuk Baek, Doo-Ill Park, Yongkyu Seo, Young-Chan Jang
2017 J jnl
A 10-Gbps receiver bridge chip with deserializer for FPGA-based frame grabber supporting MIPI CSI-2.
IEEE Trans. Consumer Electron.
Pil-Ho Lee, Han-Yeol Lee, Yeong-Woong Kim, Han-Young Hong, Young-Chan Jang
2017 — conf
A clock recovery for 2.56 GSymbol/s MIPI C-PHY receiver.
ISOCC
Jin-Wook Han, Pil-Ho Lee, Yeong-Woong Kim, Sang-Dong Kim, Jin-Woo Park, Young-Chan Jang
2017 J jnl
An On-Chip Monitoring Circuit for Signal-Integrity Analysis of 8-Gb/s Chip-to-Chip Interfaces With Source-Synchronous Clock.
IEEE Trans. Very Large Scale Integr. Syst.
Pil-Ho Lee, Han-Yeol Lee, Hyun Bae Lee, Young-Chan Jang
2016 J jnl
A 10-bit 20-MS/s Asynchronous SAR ADC with Meta-Stability Detector Using Replica Comparators.
IEICE Trans. Electron.
Sang-Min Park, Yeon-Ho Jeong, Yu-Jeong Hwang, Pil-Ho Lee, Yeong-Woong Kim, Jisu Son, Han-Yeol Lee, Young-Chan Jang
2016 J jnl
An On-Chip Monitoring Circuit with 51-Phase PLL-Based Frequency Synthesizer for 8-Gb/s ODR Single-Ended Signaling Integrity Analysis.
IEICE Trans. Electron.
Pil-Ho Lee, Yu-Jeong Hwang, Han-Yeol Lee, Hyun Bae Lee, Young-Chan Jang
2014 J jnl
A 10-bit CMOS Digital-to-Analog Converter with Compact Size for Display Applications.
IEICE Trans. Electron.
Mungyu Kim, Hoon-Ju Chung, Young-Chan Jang
2014 J jnl
A 125MHz 64-Phase Delay-Locked Loop with Coarse-Locking Circuit Independent of Duty Cycle.
IEICE Trans. Electron.
Pil-Ho Lee, Hyun Bae Lee, Young-Chan Jang
2014 J jnl
A 2-Gb/s CMOS SLVS Transmitter with Asymmetric Impedance Calibration for Mobile Interfaces.
IEICE Trans. Electron.
Kwang-Hun Lee, Young-Chan Jang
2013 J jnl
An 8-Bit 100-kS/s CMOS Single-Ended SA ADC for 8×8 Point EEG/MEG Acquisition System.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Ji-Hun Eo, Yeon-Ho Jeong, Young-Chan Jang
2012 J jnl
A 1.8 V 0.18-μm 1 GHz CMOS Fast-Lock Phase-Locked Loop using a Frequency-to-Digital Converter.
J. Inform. and Commun. Convergence Engineering
Kwang-Hun Lee, Young-Chan Jang
2012 J jnl
A 1.8 V 40-MS/sec 10-bit 0.18-㎛ CMOS Pipelined ADC using a Bootstrapped Switch with Constant Resistance.
J. Inform. and Commun. Convergence Engineering
Ji-Hun Eo, Sang-Hun Kim, Mungyu Kim, Young-Chan Jang
2012 J jnl
A true single-phase clocked flip-flop with leakage current compensation.
IEICE Electron. Express
Han-Yeol Lee, Young-Chan Jang
2012 J jnl
Mirrored Serpentine Microstrip Lines for Reduction of Far-End Crosstalk.
IEICE Trans. Electron.
Hyun Bae Lee, Young-Chan Jang
2011 J jnl
A 1 V 200 kS/s 10-bit Successive Approximation ADC for a Sensor Interface.
IEICE Trans. Electron.
Ji-Hun Eo, Sang-Hun Kim, Young-Chan Jang
2011 J jnl
A Bootstrapped Analog Switch with Constant On-Resistance.
IEICE Trans. Electron.
Sang-Hun Kim, Yong-Hwan Lee, Hoon-Ju Chung, Young-Chan Jang
2011 J jnl
A Self-Calibrating Per-Pin Phase Adjuster for Source Synchronous Double Data Rate Signaling in Parallel Interface.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Young-Chan Jang
2010 J jnl
A Swing Level Controlled Transmitter for Single-Ended Signaling with Center-Tapped Termination.
IEICE Trans. Electron.
Young-Chan Jang
2010 J jnl
A digital phase corrector with a duty cycle detector and transmitter for a Quad Data Rate I/O scheme.
IEICE Electron. Express
Young-Chan Jang
2010 J jnl
An unmatched source synchronous I/O link for jitter reduction in a multi-phase clock system.
IEICE Electron. Express
Young-Chan Jang
2009 J jnl
BER Measurement of a 5.8-Gb/s/pin Unidirectional Differential I/O for DRAM Application With DIMM Channel.
IEEE J. Solid State Circuits
Young-Chan Jang, Hoeju Chung, Youngdon Choi, Hwan-Wook Park, Jaekwan Kim, Soouk Lim, Jung Sunwoo, Moon-Sook Park, Hyung-Seuk Kim, Sang-Yun Kim, Yun-Sang Lee, Woo-Seop Kim, Jung-Bae Lee, Jei-Hwan Yoo, Changhyun Kim
2007 J jnl
An 8 Gb/s/pin 9.6 ns Row-Cycle 288 Mb Deca-Data Rate SDRAM With an I/O Error Detection Scheme.
IEEE J. Solid State Circuits
Kyu-Hyoun Kim, Hoeju Chung, Woo-Seop Kim, Moon-Sook Park, Young-Chan Jang, Jinyoung Kim, Hwan-Wook Park, Uksong Kang, Paul W. Coteus, Joo-Sun Choi, Changhyun Kim
2007 J jnl
An 8.8-GS/s 6-bit CMOS Time-Interleaved Flash Analog-to-Digital Converter with Multi-Phase Clock Generator.
IEICE Trans. Electron.
Young-Chan Jang, Jun-Hyun Bae, Sang-Hune Park, Jae-Yoon Sim, Hong-June Park
2006 J jnl
A Digital CMOS PWCL With Fixed-Delay Rising Edge and Digital Stability Control.
IEEE Trans. Circuits Syst. II Express Briefs
Young-Chan Jang, Jun-Hyun Bae, Hong-June Park
2006 — conf
An 8Gb/s/pin 9.6ns Row-Cycle 288Mb Deca-Data Rate SDRAM with an I/O Error-Detection Scheme.
ISSCC
Kyu-Hyoun Kim, Uksong Kang, Hoeju Chung, Dukha Park, Woo-Seop Kim, Young-Chan Jang, Moon-Sook Park, Hoon Lee, Jinyoung Kim, Jung Sunwoo, Hwan-Wook Park, Hyun-Kyung Kim, Su-Jin Chung, Jae-Kwan Kim, Hyung-Seuk Kim, Kee-Won Kwon, Young-Taek Lee, Joo-Sun Choi, Changhyun Kim