Youn-Long Lin - RankMe

107 papers A* 11A 16C 3Misc 1Journal 44Unranked 32

Year	Rank	Type	Title / Venue / Authors
2024	—	`conf`	Development and Applications of a Memory-Traffic-Efficient Convolutional Neural Network. A-SSCC Youn-Long Lin
2023	—	`conf`	NeighborTrack: Single Object Tracking by Bipartite Matching with Neighbor Tracklets and Its Applications to Sports. CVPR Workshops Yu-Hsi Chen, Chien-Yao Wang, Cheng-Yun Yang, Hung-Shuo Chang, Youn-Long Lin, Yung-Yu Chuang, Hong-Yuan Mark Liao
2022	J	`jnl`	HarDNet-DFUS: An Enhanced Harmonically-Connected Network for Diabetic Foot Ulcer Image Segmentation and Colonoscopy Polyp Segmentation. CoRR Ting-Yu Liao, Ching-Hui Yang, Yu-Wen Lo, Kuan-Ying Lai, Po-Huai Shen, Youn-Long Lin
2022	—	`conf`	HarDNet-DFUS: Enhancing Backbone and Decoder of HarDNet-MSEG for Diabetic Foot Ulcer Image Segmentation. DFUC@MICCAI Ting-Yu Liao, Ching-Hui Yang, Yu-Wen Lo, Kuan-Ying Lai, Po-Huai Shen, Youn-Long Lin
2022	J	`jnl`	NeighborTrack: Improving Single Object Tracking by Bipartite Matching with Neighbor Tracklets. CoRR Yu-Hsi Chen, Chien-Yao Wang, Cheng-Yun Yang, Hung-Shuo Chang, Youn-Long Lin, Yung-Yu Chuang, Hong-Yuan Mark Liao
2022	A	`conf`	SearchTrack: Multiple Object Tracking with Object-Customized Search and Motion-Aware Features. BMVC Zhong-Min Tsai, Yu-Ju Tsai, Chien-Yao Wang, Hong-Yuan Mark Liao, Youn-Long Lin, Yung-Yu Chuang
2022	J	`jnl`	SearchTrack: Multiple Object Tracking with Object-Customized Search and Motion-Aware Features. CoRR Zhong-Min Tsai, Yu-Ju Tsai, Chien-Yao Wang, Hong-Yuan Mark Liao, Youn-Long Lin, Yung-Yu Chuang
2021	—	`conf`	Exploring the power of lightweight YOLOv4. ICCVW Chien-Yao Wang, Hong-Yuan Mark Liao, I-Hau Yeh, Yung-Yu Chuang, Youn-Long Lin
2021	—	`conf`	HarDNet-BTS: A Harmonic Shortcut Network for Brain Tumor Segmentation. BrainLes@MICCAI (1) Hung-Yu Wu, Youn-Long Lin
2021	J	`jnl`	HarDNet-MSEG: A Simple Encoder-Decoder Polyp Segmentation Neural Network that Achieves over 0.9 Mean Dice and 86 FPS. CoRR Chien-Hsiang Huang, Hung-Yu Wu, Youn-Long Lin
2020	J	`jnl`	RNNAccel: A Fusion Recurrent Neural Network Accelerator for Edge Intelligence. CoRR Chao-Yang Kao, Huang-Chih Kuo, Jian-Wen Chen, Chiung-Liang Lin, Pin-Han Chen, Youn-Long Lin
2019	A*	`conf`	HarDNet: A Low Memory Traffic Network. ICCV Ping Chao, Chao-Yang Kao, Yu-Shan Ruan, Chien-Hsiang Huang, Youn-Long Lin
2019	J	`jnl`	HarDNet: A Low Memory Traffic Network. CoRR Ping Chao, Chao-Yang Kao, Yu-Shan Ruan, Chien-Hsiang Huang, Youn-Long Lin
2013	J	`jnl`	Power-Up Sequence Control for MTCMOS Designs. IEEE Trans. Very Large Scale Integr. Syst. Shi-Hao Chen, Youn-Long Lin, Mango Chia-Tso Chao
2013	J	`jnl`	Strengthening Modern Electronics Industry Through the National Program for Intelligent Electronics in Taiwan. IEEE Access Wen-Tsuen Chen, Youn-Long Lin, Chen-Yi Lee, Jeng-Long Chiang, Meng-Fan Chang, Shih-Chieh Chang
2013	J	`jnl`	VLSI Architecture Design for H.264/AVC Intra-frame Video Encoding. IPSJ Trans. Syst. LSI Des. Methodol. Huang-Chih Kuo, Youn-Long Lin
2012	J	`jnl`	A Hybrid Algorithm for Effective Lossless Compression of Video Display Frames. IEEE Trans. Multim. Huang-Chih Kuo, Youn-Long Lin
2011	J	`jnl`	A Low-Power High-Performance H.264/AVC Intra-Frame Encoder for 1080pHD Video. IEEE Trans. Very Large Scale Integr. Syst. Huang-Chih Kuo, Li-Cian Wu, Hao-Ting Huang, Sheng-Tsung Hsu, Youn-Long Lin
2011	A	`conf`	A simple and effective lossless compression algorithm for video display frames. ICME Huang-Chih Kuo, Youn-Long Lin
2011	J	`jnl`	Three-dimensional integrated circuits implementation of multiple applications emphasising manufacture reuse. IET Comput. Digit. Tech. Chia-Ming Hung, Youn-Long Lin
2010	—	`conf`	A 3D SoC design for H.264 application with on-chip DRAM stacking. 3DIC Tao Zhang, Kui Wang, Yi Feng, Yan Chen, Qun Li, Bing Shao, Jing Xie, Xiaodi Song, Lian Duan, Yuan Xie, Xu Cheng, Youn-Long Lin
2010	J	`jnl`	A High-Performance Three-Engine Architecture for H.264/AVC Fractional Motion Estimation. IEEE Trans. Very Large Scale Integr. Syst. Chao-Yang Kao, Cheng-Long Wu, Youn-Long Lin
2010	J	`jnl`	A Memory-Efficient and Highly Parallel Architecture for Variable Block Size Integer Motion Estimation in H.264/AVC. IEEE Trans. Very Large Scale Integr. Syst. Chao-Yang Kao, Youn-Long Lin
2010	—	`conf`	A customized design of DRAM controller for on-chip 3D DRAM stacking. CICC Tao Zhang, Kui Wang, Yi Feng, Xiaodi Song, Lian Duan, Yuan Xie, Xu Cheng, Youn-Long Lin
2010	J	`jnl`	A high-throughput fully hardwired CABAC encoder for QFHD H.264/AVC main profile video. IEEE Trans. Consumer Electron. Jian-Wen Chen, Li-Cian Wu, Po-Sheng Liu, Youn-Long Lin
2010	Misc	`conf`	An elastic software cache with fast prefetching for motion compensation in video decoding. CODES+ISSS Ping Chao, Youn-Long Lin
2010	J	`jnl`	An optimal warning-zone-length assignment algorithm for real-time and multiple-QoS on-chip bus arbitration. ACM Trans. Embed. Comput. Syst. Huan-Kai Peng, Youn-Long Lin
2009	C	`conf`	A High throughput CABAC Encoder for Ultra High Resolution Video. ISCAS Li-Cian Wu, Youn-Long Lin
2009	J	`jnl`	A Two-Result-per-Cycle Deblocking Filter Architecture for QFHD H.264/AVC Decoder. IEEE Trans. Very Large Scale Integr. Syst. Yuan-Chun Lin, Youn-Long Lin
2009	J	`jnl`	A high-performance hardwired CABAC decoder for ultra-high resolution video. IEEE Trans. Consumer Electron. Jian-Wen Chen, Youn-Long Lin
2009	—	`conf`	A high-performance low-power H.264/AVC video decoder accelerator for embedded systems. ESTIMedia Huang-Chih Kuo, Jian-Wen Chen, Youn-Long Lin
2009	—	`conf`	An effective dictionary-based display frame compressor. ESTIMedia Hui-Ting Yang, Jian-Wen Chen, Huang-Chih Kuo, Youn-Long Lin
2008	A	`conf`	A high performance three-engine architecture for H.264/AVC fractional motion estimation. ICME Cheng-Long Wu, Chao-Yang Kao, Youn-Long Lin
2008	A	`conf`	A high-performance and memory-efficient architecture for H.264/AVC motion estimation. ICME Chao-Yang Kao, Youn-Long Lin
2008	C	`conf`	A motion compensation system with a high efficiency reference frame pre-fetch scheme for QFHD H.264/AVC decoding. ISCAS Ping Chao, Youn-Long Lin
2008	A	`conf`	An H.264/AVC full-mode intra-frame encoder for 1080HD video. ICME Huang-Chih Kuo, Youn-Long Lin
2008	A	`conf`	Reference frame access optimization for ultra high resolution H.264/AVC decoding. ICME Ping Chao, Youn-Long Lin
2007	—	`conf`	A High-Performance Hardwired CABAC Decoder. ICASSP (2) Jian-Wen Chen, Youn-Long Lin
2007	J	`jnl`	Integration, Verification and Layout of a Complex Multimedia SOC CoRR Chien-Liang Chen, Jiing-Yuan Lin, Youn-Long Lin
2006	—	`conf`	A High-Performance VLSI Architecture for Intra Prediction and Mode Decision in H.264/AVC Video Encoding. APCCAS Yu-Chien Kao, Huang-Chih Kuo, Yin-Tzu Lin, Chia-Wen Hou, Yi-Hsien Li, Hao-Tin Huang, Youn-Long Lin
2006	—	`conf`	A near optimal deblocking filter for H.264 advanced video coding. ASP-DAC Shen-Yu Shih, Cheng-Ru Chang, Youn-Long Lin
2006	A	`conf`	High Performance Fractional Motion Estimation and Mode Decision for H.264/AVC. ICME Chao-Yang Kao, Huang-Chih Kuo, Youn-Long Lin
2006	—	`conf`	Introduction to H.264 advanced video coding. ASP-DAC Jian-Wen Chen, Chao-Yang Kao, Youn-Long Lin
2005	—	`conf`	A hardware accelerator for context-based adaptive binary arithmetic decoding in H.264/AVC. ISCAS (5) Jian-Wen Chen, Cheng-Ru Chang, Youn-Long Lin
2005	J	`jnl`	A platform based SOC design methodology and its application in image compression. Int. J. Embed. Syst. Kai-Yuan Jan, Chih-Bin Fan, An-Chao Kuo, Wen-Chi Yen, Youn-Long Lin
2005	—	`conf`	An AMBA-compliant deblocking filter IP for H.264/AVC. ISCAS (5) Sheng-Yu Shih, Cheng-Ru Chang, Youn-Long Lin
2005	A	`conf`	Integration, Verification and Layout of a Complex Multimedia SOC. DATE Chien-Liang Chen, Jiing-Yuan Lin, Youn-Long Lin
2004	—	`conf`	A hardware accelerator IP for EBCOT Tier-1 coding in JPEG2000 Standard. ESTIMedia Tien-Wei Hsieh, Youn-Long Lin
2002	J	`jnl`	Effective enforcement of path-delay constraints inperformance-driven placement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yih-Chih Chou, Youn-Long Lin
2002	—	`conf`	Test Scheduling and Test Access Architecture Optimization for System-on-Chip. Asian Test Symposium Huan-Shan Hsu, Jing-Reng Huang, Kuo-Liang Cheng, Chih-Wea Wang, Chih-Tsun Huang, Cheng-Wen Wu, Youn-Long Lin
2002	—	`conf`	Test Scheduling of BISTed Memory Cores for SOC. Asian Test Symposium Chih-Wea Wang, Jing-Reng Huang, Yen-Fu Lin, Kuo-Liang Cheng, Chih-Tsun Huang, Cheng-Wen Wu, Youn-Long Lin
2001	—	`conf`	A 3-step approach for performance-driven whole-chip routing. ASP-DAC Yih-Chih Chou, Youn-Long Lin
2001	—	`conf`	A performance-driven standard-cell placer based on a modified force-directed algorithm. ISPD Yih-Chih Chou, Youn-Long Lin
2001	—	`conf`	Concurrent-simulation-based remote IP evaluation over the internet for system-on-a-chip design. ISSS Hung-Pin Wen, Chien-Yu Lin, Youn-Long Lin
2000	—	`conf`	A VLSI implementation of the blowfish encryption/decryption algorithm. ASP-DAC Michael C.-J. Lin, Youn-Long Lin
2000	—	`conf`	Array allocation taking into account SDRAM characteristics. ASP-DAC Hong-Kai Chang, Youn-Long Lin
2000	—	`conf`	Performance-optimal clustering with retiming for sequential circuits. ASP-DAC Tzu-Chieh Tien, Youn-Long Lin
1999	A*	`conf`	A Timing-Driven Soft-Macro Resynthesis Method in Interaction with Chip Floorplanning. DAC Hsiao-Pin Su, Allen C.-H. Wu, Youn-Long Lin
1999	J	`jnl`	A timing-driven soft-macro placement and resynthesis method in interaction with chip floorplanning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Hsiao-Pin Su, Allen C.-H. Wu, Youn-Long Lin
1999	J	`jnl`	Code generation of nested loops for DSP processors with heterogeneous registers and structural pipelining. ACM Trans. Design Autom. Electr. Syst. Wei-Kai Cheng, Youn-Long Lin
1999	—	`conf`	Layout-based Logic Decomposition for Timing Optimization. ASP-DAC Yun-Yin Lian, Youn-Long Lin
1998	A	`conf`	A graph-partitioning-based approach for multi-layer constrained via minimization. ICCAD Yih-Chih Chou, Youn-Long Lin
1998	—	`conf`	Addressing Optimization for Loop Execution Targeting DSP with Auto-Increment/Decrement Architecture. ISSS Wei-Kai Cheng, Youn-Long Lin
1998	A	`conf`	Integrating logic retiming and register placement. ICCAD Tzu-Chieh Tien, Hsiao-Pin Su, Yu-Wen Tsay, Yih-Chih Chou, Youn-Long Lin
1998	—	`conf`	Performance-driven soft-macro clustering and placement by preserving HDL design hierarchy. ISPD Hsiao-Pin Su, Allen C.-H. Wu, Youn-Long Lin
1997	J	`jnl`	A phase assignment method for virtual-wire-based hardware emulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Hsiao-Pin Su, Youn-Long Lin
1997	—	`conf`	Computing brokerage and its application in VLSI design. ASP-DAC Youn-Long Lin
1997	—	`conf`	Preserving HDL synthesis hierarchy for cell placement. ISPD Yu-Wen Tsay, Wen-Jong Fang, Allen C.-H. Wu, Youn-Long Lin
1997	J	`jnl`	Recent developments in high-level synthesis. ACM Trans. Design Autom. Electr. Syst. Youn-Long Lin
1996	J	`jnl`	Register minimization beyond sharing among variables. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Tsung-Yi Wu, Youn-Long Lin
1996	—	`conf`	Storage optimization by replacing some flip-flops with latches. EURO-DAC Youn-Long Lin, Tsung-Yi Wu
1995	A*	`conf`	A Transformation-Based Approach for Storage Optimization. DAC Wei-Kai Cheng, Youn-Long Lin
1995	J	`jnl`	A row-based cell placement method that utilizes circuit structural properties. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yu-Wen Tsay, Youn-Long Lin
1995	J	`jnl`	Combining technology mapping and placement for delay-minimization in FPGA designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Chau-Shen Chen, Yu-Wen Tsay, TingTing Hwang, Allen C.-H. Wu, Youn-Long Lin
1995	J	`jnl`	High-Level Synthesis -A Tutorial. IEICE Trans. Inf. Syst. Allen C.-H. Wu, Youn-Long Lin
1995	A*	`conf`	Register Minimization beyond Sharing among Variables. DAC Tsung-Yi Wu, Youn-Long Lin
1995	J	`jnl`	TRACER-fpga: a router for RAM-based FPGA's. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ching-Dong Chen, Yuh-Sheng Lee, Allen C.-H. Wu, Youn-Long Lin
1994	—	`conf`	A Synthesis Method for Mixed Synchronous / Asynchronous Behavior. EDAC-ETC-EUROASIC Tsung-Yi Wu, Tzu-Chieh Tien, Allen C.-H. Wu, Youn-Long Lin
1994	J	`jnl`	A transformation-based method for loop folding. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Tsing-Fa Lee, Allen C.-H. Wu, Youn-Long Lin, Daniel D. Gajski
1994	—	`conf`	Code generation for a DSP processor. HLSS Wei-Kai Cheng, Youn-Long Lin
1994	J	`jnl`	Performance-driven interconnection optimization for microarchitecture synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yi-Min Jiang, Tsing-Fa Lee, TingTing Hwang, Youn-Long Lin
1994	C	`conf`	State Assignment for Power and Area Minimization. ICCD Kuo-Hua Wang, Wen-Sing Wang, TingTing Hwang, Allen C.-H. Wu, Youn-Long Lin
1993	J	`jnl`	An efficient layout style for two-metal CMOS leaf cells and its automatic synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Chi-Yi Hwang, Yung-Ching Hsieh, Youn-Long Lin, Yu-Chin Hsu
1993	A	`conf`	Combining technology mapping and placement for delay-optimization in FPGA designs. ICCAD Chau-Shen Chen, Yu-Wen Tsay, TingTing Hwang, Allen C.-H. Wu, Youn-Long Lin
1993	J	`jnl`	PLS: a scheduler for pipeline synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Cheng-Tsung Hwang, Yu-Chin Hsu, Youn-Long Lin
1992	J	`jnl`	A Systolic Algorithm for the k-Nearest Neighbors Problem. IEEE Trans. Computers Yirng-An Chen, Youn-Long Lin, Long-Wen Chang
1992	A	`conf`	An effective methodology for functional pipelining. ICCAD Tsing-Fa Lee, Allen C.-H. Wu, Daniel Gajski, Youn-Long Lin
1991	A*	`conf`	An Efficient Layout Style for 2-Metal CMOS Leaf Cells And Their Automatic Generation. DAC Chi-Yi Hwang, Yung-Ching Hsieh, Youn-Long Lin, Yu-Chin Hsu
1991	A*	`conf`	Channel Density Reduction by Routing Over The Cells. DAC Min-Siang Lin, Hourng-Wern Perng, Chi-Yi Hwang, Youn-Long Lin
1991	J	`jnl`	Channel density reduction by routing over the cells. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Min-Siang Lin, Hourng-Wern Perng, Chi-Yi Hwang, Youn-Long Lin
1991	J	`jnl`	Combining Logic Minimization and Folding for PLA's. IEEE Trans. Computers Yu-Chin Hsu, Youn-Long Lin, Hang-Ching Hsieh, Ting-Hai Chao
1991	J	`jnl`	FLORA: A data path allocator based on branch-and-bound search. Integr. Ta-Yung Liu, Youn-Long Lin
1991	J	`jnl`	LiB: a CMOS cell compiler. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yung-Ching Hsieh, Chi-Yi Hwang, Youn-Long Lin, Yu-Chin Hsu
1991	A*	`conf`	Scheduling for Functional Pipelining and Loop Winding. DAC Cheng-Tsung Hwang, Yu-Chin Hsu, Youn-Long Lin
1990	J	`jnl`	A fast transistor-chaining algorithm for CMOS cell layout. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Chi-Yi Hwang, Yung-Chin Hsieh, Youn-Long Lin, Yu-Chin Hsu
1990	J	`jnl`	A new algorithm for tile generation. Integr. Youn-Long Lin, Yu-Chin Hsu
1990	A*	`conf`	Data Path Allocation Based on Bipartite Weighted Matching. DAC Chu-Yi Huang, Yen-Shen Chen, Youn-Long Lin, Yu-Chin Hsu
1990	J	`jnl`	Hybrid routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Youn-Long Lin, Yu-Chin Hsu, Fur-Shing Tsai
1990	A*	`conf`	LiB: A Cell Layout Generator. DAC Yung-Ching Hsieh, Chi-Yi Hwang, Youn-Long Lin, Yu-Chin Hsu
1990	A*	`conf`	Optimum and Heuristic Data Path Scheduling Under Resource Constraints. DAC Cheng-Tsung Hwang, Yu-Chin Hsu, Youn-Long Lin
1989	A	`conf`	A new integer linear programming formulation for the scheduling problem in data path synthesis. ICCAD Jiahn-Humg Lee, Yu-Chin Hsu, Youn-Long Lin
1989	A	`conf`	An optimal transistor-chaining algorithm for CMOS cell layout. ICCAD Chi-Yi Hwang, Yung-Ching Hsieh, Youn-Long Lin, Yu-Chin Hsu
1989	A	`conf`	Routing using a pyramid data structure. ICCAD Youn-Long Lin, Yu-Chin Hsu, Fur-Shing Tsai
1989	J	`jnl`	SILK: a simulated evolution router. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Youn-Long Lin, Yu-Chin Hsu, Fur-Shing Tsai
1988	A	`conf`	A detailed router based on simulated evolution. ICCAD Youn-Long Lin, Yu-Chin Hsu, Fur-Shing Tsai
1988	J	`jnl`	LES: a layout expert system. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Youn-Long Lin, Daniel D. Gajski
1987	A*	`conf`	LES: A Layout Expert System. DAC Youn-Long Lin, Daniel Gajski