Youhua Shi - RankMe

63 papers A 2C 5Journal 23Unranked 33

Year	Rank	Type	Title / Venue / Authors
2025	J	`jnl`	A Novel Security Threat Model for Automated AI Accelerator Generation Platforms. IEEE Access Chao Guo, Youhua Shi
2025	J	`jnl`	An FPGA-Based YOLOv6 Accelerator for High-Throughput and Energy-Efficient Object Detection. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Xingan Sha, Masao Yanagisawa, Youhua Shi
2025	—	`conf`	Computation-Efficient Hardware Accelerator for Unstructured-Pruned Spiking Convolutional Neural Networks. AICAS Jiaxiang Li, Youhua Shi
2025	J	`jnl`	DSE-Based Hardware Trojan Attack for Neural Network Accelerators on FPGAs. IEEE Trans. Neural Networks Learn. Syst. Chao Guo, Masao Yanagisawa, Youhua Shi
2023	—	`conf`	An Area-Power-Efficient Multiplier-less Processing Element Design for CNN Accelerators. ASICON Jiaxiang Li, Masao Yanagisawa, Youhua Shi
2023	—	`conf`	Strategy for Improving Cycle of Maximized Energy Output of Triboelectric Nanogenerators. ICICDT Yirui Su, Masao Yanagisawa, Youhua Shi
2021	—	`conf`	A Reconfigurable Area and Energy Efficient Hardware Accelerator of Five High-order Operators for Vision Sensor Based Robot Systems. ICTA Qianjin Wang, Yi Zhan, Bingqiang Liu, Jiajun Wu, Youhua Shi, Guoyi Yu, Chao Wang
2021	J	`jnl`	Power-Efficient Deep Convolutional Neural Network Design Through Zero-Gating PEs and Partial-Sum Reuse Centric Dataflow. IEEE Access Lin Ye, Jinghao Ye, Masao Yanagisawa, Youhua Shi
2020	—	`conf`	A High-Performance Symmetric Hybrid Form Design for High-Order FIR Filters. APCCAS Jinghao Ye, Masao Yanagisawa, Youhua Shi
2020	J	`jnl`	Faithfully Truncated Adder-Based Area-Power Efficient FIR Design with Predefined Output Accuracy. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Jinghao Ye, Masao Yanagisawa, Youhua Shi
2020	J	`jnl`	Transition Detector-Based Radiation-Hardened Latch for Both Single- and Multiple-Node Upsets. IEEE Trans. Circuits Syst. II Express Briefs Saki Tajima, Masao Yanagisawa, Youhua Shi
2019	—	`conf`	A Bit-Segmented Adder Chain based Symmetric Transpose Two-Block FIR Design for High-Speed Signal Processing. APCCAS Jinghao Ye, Masao Yanagisawa, Youhua Shi
2019	—	`conf`	A Zero-Gating Processing Element Design for Low-Power Deep Convolutional Neural Networks. APCCAS Lin Ye, Jinghao Ye, Masao Yanagisawa, Youhua Shi
2019	—	`conf`	An Adder-Segmentation-based FIR for High Speed Signal Processing. ASICON Jinghao Ye, Masao Yanagisawa, Youhua Shi
2019	C	`conf`	Static Error Analysis and Optimization of Faithfully Truncated Adders for Area-Power Efficient FIR Designs. ISCAS Jinghao Ye, Nozomu Togawa, Masao Yanagisawa, Youhua Shi
2018	J	`jnl`	A Low Power Soft Error Hardened Latch with Schmitt-Trigger-Based C-Element. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Saki Tajima, Nozomu Togawa, Masao Yanagisawa, Youhua Shi
2018	J	`jnl`	Extension and Performance/Accuracy Formulation for Optimal GeAr-Based Approximate Adder Designs. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Ken Hayamizu, Nozomu Togawa, Masao Yanagisawa, Youhua Shi
2018	—	`conf`	Hardware Trojan Detection Utilizing Machine Learning Approaches. TrustCom/BigDataSE Kento Hasegawa, Youhua Shi, Nozomu Togawa
2017	—	`conf`	A low cost and high speed CSD-based symmetric transpose block FIR implementation. ASICON Jinghao Ye, Youhua Shi, Nozomu Togawa, Masao Yanagisawa
2017	—	`conf`	Soft error tolerant latch designs with low power consumption (invited paper). ASICON Saki Tajima, Nozomu Togawa, Masao Yanagisawa, Youhua Shi
2016	—	`conf`	A delay variation and floorplan aware high-level synthesis algorithm with body biasing. ISQED Koki Igawa, Youhua Shi, Masao Yanagisawa, Nozomu Togawa
2016	—	`conf`	In-situ Trojan authentication for invalidating hardware-Trojan functions. ISQED Masaru Oya, Youhua Shi, Masao Yanagisawa, Nozomu Togawa
2016	J	`jnl`	Timing monitoring paths selection for wide voltage IC. IEICE Electron. Express Weiwei Shan, Wentao Dai, Youhua Shi, Peng Cao, Xiaoyan Xiang
2015	J	`jnl`	A Hardware-Trojans Identifying Method Based on Trojan Net Scoring at Gate-Level Netlists. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Masaru Oya, Youhua Shi, Noritaka Yamashita, Toshihiko Okamura, Yukiyasu Tsunoo, Satoshi Goto, Masao Yanagisawa, Nozomu Togawa
2015	—	`conf`	A low-power soft error tolerant latch scheme. ASICON Saki Tajima, Youhua Shi, Nozomu Togawa, Masao Yanagisawa
2015	—	`conf`	A process-variation-aware multi-scenario high-level synthesis algorithm for distributed-register architectures. SoCC Koki Igawa, Youhua Shi, Masao Yanagisawa, Nozomu Togawa
2015	A	`conf`	A score-based classification method for identifying hardware-trojans at gate-level netlists. DATE Masaru Oya, Youhua Shi, Masao Yanagisawa, Nozomu Togawa
2015	J	`jnl`	An Effective Suspicious Timing-Error Prediction Circuit Insertion Algorithm Minimizing Area Overhead. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Shinnosuke Yoshida, Youhua Shi, Masao Yanagisawa, Nozomu Togawa
2015	J	`jnl`	An Energy-Efficient Floorplan Driven High-Level Synthesis Algorithm for Multiple Clock Domains Design. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Shin-ya Abe, Youhua Shi, Kimiyoshi Usami, Masao Yanagisawa, Nozomu Togawa
2015	—	`conf`	Improved monitoring-path selection algorithm for suspicious timing error prediction based timing speculation. ASICON Shinnosuke Yoshida, Youhua Shi, Masao Yanagisawa, Nozomu Togawa
2014	—	`conf`	An area-overhead-oriented monitoring-path selection algorithm for suspicious timing error prediction. APCCAS Shinnosuke Yoshida, Youhua Shi, Masao Yanagisawa, Nozomu Togawa
2014	—	`conf`	In-situ timing monitoring methods for variation-resilient designs. APCCAS Youhua Shi, Nozomu Togawa
2014	—	`conf`	Secure scan design using improved random order and its evaluations. APCCAS Masaru Oya, Yuta Atobe, Youhua Shi, Masao Yanagisawa, Nozomu Togawa
2014	—	`conf`	Throughput driven check point selection in suspicious timing error prediction based designs. LASCAS Hiroaki Igarashi, Youhua Shi, Masao Yanagisawa, Nozomu Togawa
2013	—	`conf`	An energy-efficient high-level synthesis algorithm incorporating interconnection delays and dynamic multiple supply voltages. VLSI-DAT Shin-ya Abe, Youhua Shi, Kimiyoshi Usami, Masao Yanagisawa, Nozomu Togawa
2013	C	`conf`	Concurrent faulty clock detection for crypto circuits against clock glitch based DFA. ISCAS Hiroaki Igarashi, Youhua Shi, Masao Yanagisawa, Nozomu Togawa
2013	J	`jnl`	Floorplan Driven Architecture and High-Level Synthesis Algorithm for Dynamic Multiple Supply Voltages. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Shin-ya Abe, Youhua Shi, Kimiyoshi Usami, Masao Yanagisawa, Nozomu Togawa
2013	C	`conf`	Secure Scan Design with Dynamically Configurable Connection. PRDC Yuta Atobe, Youhua Shi, Masao Yanagisawa, Nozomu Togawa
2013	—	`conf`	Suspicious timing error prediction with in-cycle clock gating. ISQED Youhua Shi, Hiroaki Igarashi, Nozomu Togawa, Masao Yanagisawa
2012	—	`conf`	Dynamically changeable secure scan architecture against scan-based side channel attack. ISOCC Yuta Atobe, Youhua Shi, Masao Yanagisawa, Nozomu Togawa
2012	J	`jnl`	MH IEICE Electron. Express Shin-ya Abe, Youhua Shi, Masao Yanagisawa, Nozomu Togawa
2012	J	`jnl`	Robust Secure Scan Design Against Scan-Based Differential Cryptanalysis. IEEE Trans. Very Large Scale Integr. Syst. Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
2012	J	`jnl`	Scan-Based Attack on AES through Round Registers and Its Countermeasure. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Youhua Shi, Nozomu Togawa, Masao Yanagisawa
2012	—	`conf`	State dependent scan flip-flop with key-based configuration against scan-based side channel attack on RSA circuit. APCCAS Yuta Atobe, Youhua Shi, Masao Yanagisawa, Nozomu Togawa
2010	J	`jnl`	Improved Launch for Higher TDF Coverage With Fewer Test Patterns. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
2010	C	`conf`	State-dependent changeable scan architecture against scan-based side channel attacks. ISCAS Ryuta Nara, Hiroshi Atobe, Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
2010	—	`conf`	VLSI implementation of a fast intra prediction algorithm for H.264/AVC encoding. APCCAS Youhua Shi, Kenta Tokumitsu, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
2009	A	`conf`	Design-for-secure-test for crypto cores. ITC Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
2009	J	`jnl`	Unified Dual-Radix Architecture for Scalable Montgomery Multiplications in IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Kazuyuki Tanimura, Ryuta Nara, Shunitsu Kohara, Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
2009	J	`jnl`	X-Handling for Current X-Tolerant Compactors with More Unknowns and Maximal Compaction. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
2008	J	`jnl`	A Secure Test Technique for Pipelined Advanced Encryption Standard. IEICE Trans. Inf. Syst. Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
2008	J	`jnl`	A Unified Test Compression Technique for Scan Stimulus and Unknown Masking Data with No Test Loss. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
2008	—	`conf`	GECOM: Test data compression combined with all unknown response masking. ASP-DAC Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
2008	—	`conf`	Scalable unified dual-radix architecture for Montgomery multiplication in GF(P) and GF(2 ASP-DAC Kazuyuki Tanimura, Ryuta Nara, Shunitsu Kohara, Kazunori Shimizu, Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
2008	—	`conf`	Unknown response masking with minimized observable response loss and mask data. APCCAS Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
2007	C	`conf`	Design for Secure Test - A Case Study on Pipelined Advanced Encryption Standard. ISCAS Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
2006	—	`conf`	FCSCAN: an efficient multiscan-based test compression technique for test cost reduction. ASP-DAC Youhua Shi, Nozomu Togawa, Shinji Kimura, Masao Yanagisawa, Tatsuo Ohtsuki
2006	—	`conf`	Low-Cost IP Core Test Using Multiple-Mode Loading Scan Chain and Scan Chain Clusters. DFT Gang Zeng, Youhua Shi, Toshinori Takabatake, Masao Yanagisawa, Hideo Ito
2006	J	`jnl`	Selective Low-Care Coding: A Means for Test Data Compression in Circuits with Multiple Scan Chains. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Youhua Shi, Nozomu Togawa, Shinji Kimura, Masao Yanagisawa, Tatsuo Ohtsuki
2005	—	`conf`	Low Power Test Compression Technique for Designs with Multiple Scan Chain. Asian Test Symposium Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki, Shinji Kimura
2004	—	`conf`	Alternative Run-Length Coding through Scan Chain Reconfiguration for Joint Minimization of Test Data Volume and Power Consumption in Scan Test. Asian Test Symposium Youhua Shi, Shinji Kimura, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
2003	J	`jnl`	A Built-in Reseeding Technique for LFSR-Based Test Pattern Generation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Youhua Shi, Zhe Zhang, Shinji Kimura, Masao Yanagisawa, Tatsuo Ohtsuki
2003	—	`conf`	Multiple test set generation method for LFSR-based BIST. ASP-DAC Youhua Shi, Zhe Zhang