Yosinori Watanabe

59 papers A* 6A 13C 4Misc 3Journal 13Unranked 16

Year	Rank	Type	Title / Venue / Authors
2017	—	`ch.`	Hardware/Software Codesign Across Many Cadence Technologies. Handbook of Hardware/Software Codesign Grant Martin, Frank Schirrmeister, Yosinori Watanabe
2013	A	`conf`	Share with care: a quantitative evaluation of sharing approaches in high-level synthesis. DATE Alex Kondratyev, Luciano Lavagno, Mike Meyer, Yosinori Watanabe
2012	C	`conf`	Clearing the clutter: Unified modeling and verification methodology for system level hardware design. MEMOCODE Yosinori Watanabe, Stuart Swan
2012	A	`conf`	Exploiting area/delay tradeoffs in high-level synthesis. DATE Alex Kondratyev, Luciano Lavagno, Mike Meyer, Yosinori Watanabe
2011	A	`conf`	Realistic performance-constrained pipelining in high-level synthesis. DATE Alex Kondratyev, Luciano Lavagno, Mike Meyer, Yosinori Watanabe
2010	—	`conf`	Incremental high-level synthesis. ASP-DAC Luciano Lavagno, Alex Kondratyev, Yosinori Watanabe, Qiang Zhu, Mototsugu Fujii, Mitsuru Tatesawa, Noriyasu Nakayama
2010	J	`jnl`	Speeding-up heuristic allocation, scheduling and binding with SAT-based abstraction/refinement techniques. ACM Trans. Design Autom. Electr. Syst. Gianpiero Cabodi, Luciano Lavagno, Marco Murciano, Alex Kondratyev, Yosinori Watanabe
2009	—	`conf`	Examining Important Corner Cases: Verification of Interacting Architectural Components in System Designs. ACSD Yosinori Watanabe
2009	J	`jnl`	Runtime deadlock analysis for system level design. Des. Autom. Embed. Syst. Eric Cheung, Xi Chen, Harry Hsieh, Abhijit Davare, Alberto L. Sangiovanni-Vincentelli, Yosinori Watanabe
2008	J	`jnl`	Schedulability Analysis of Petri Nets Based on Structural Properties. Fundam. Informaticae Cong Liu, Alex Kondratyev, Yosinori Watanabe, Jörg Desel, Alberto L. Sangiovanni-Vincentelli
2006	—	`conf`	Functional Model Exploration for Multimedia Applications via Algebraic Operators. ACSD Shinjiro Kakita, Yosinori Watanabe, Douglas Densmore, Abhijit Davare, Alberto L. Sangiovanni-Vincentelli
2006	—	`conf`	Schedulability Analysis of Petri Nets Based on Structural Properties. ACSD Cong Liu, Alex Kondratyev, Yosinori Watanabe, Alberto L. Sangiovanni-Vincentelli, Jörg Desel
2005	J	`jnl`	A BMC-based formulation for the scheduling problem of hardware systems. Int. J. Softw. Tools Technol. Transf. Gianpiero Cabodi, Alex Kondratyev, Luciano Lavagno, Sergio Nocco, Stefano Quer, Yosinori Watanabe
2005	A	`conf`	A Time Slice Based Scheduler Model for System Level Design. DATE Luciano Lavagno, Claudio Passerone, Vishal Shah, Yosinori Watanabe
2005	Misc	`conf`	A structural approach to quasi-static schedulability analysis of communicating concurrent programs. EMSOFT Cong Liu, Alex Kondratyev, Yosinori Watanabe, Alberto L. Sangiovanni-Vincentelli
2005	J	`jnl`	Eliminating false positives in crosstalk noise analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yajun Ran, Alex Kondratyev, Kenneth H. Tseng, Yosinori Watanabe, Malgorzata Marek-Sadowska
2005	—	`ch.`	Quasi-Static Scheduling of Concurrent Specifications. Embedded Systems Handbook Luciano Lavagno, Claudio Passerone, Alex Kondratyev, Yosinori Watanabe
2005	J	`jnl`	Quasi-static scheduling of independent tasks for reactive systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jordi Cortadella, Alex Kondratyev, Luciano Lavagno, Claudio Passerone, Yosinori Watanabe
2005	A*	`conf`	Simulation based deadlock analysis for system level designs. DAC Xi Chen, Abhijit Davare, Harry Hsieh, Alberto L. Sangiovanni-Vincentelli, Yosinori Watanabe
2004	A	`conf`	Eliminating False Positives in Crosstalk Noise Analysis. DATE Yajun Ran, Alex Kondratyev, Yosinori Watanabe, Malgorzata Marek-Sadowska
2004	J	`jnl`	Logic of constraints: a quantitative performance and functional constraint formalism. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Xi Chen, Harry Hsieh, Felice Balarin, Yosinori Watanabe
2004	J	`jnl`	Quasi-static Scheduling for Concurrent Architectures. Fundam. Informaticae Jordi Cortadella, Alex Kondratyev, Luciano Lavagno, Alexander Taubin, Yosinori Watanabe
2004	Misc	`conf`	Separation of concerns: overhead in modeling and efficient simulation techniques. EMSOFT Guang Yang, Alberto L. Sangiovanni-Vincentelli, Yosinori Watanabe, Felice Balarin
2003	—	`conf`	A BMC-formulation for the scheduling problem in highly constrained hardware Systems. BMC@CAV Gianpiero Cabodi, Sergio Nocco, Stefano Quer, Alex Kondratyev, Luciano Lavagno, Yosinori Watanabe
2003	A	`conf`	An Efficient Hash Table Based Approach to Avoid State Space Explosion in History Driven Quasi-Static Scheduling. DATE Antonio G. Lomeña, Marisa Luisa López-Vallejo, Yosinori Watanabe, Alex Kondratyev
2003	A	`conf`	Automatic Generation of Simulation Monitors from Quantitative Constraint Formula. DATE Xi Chen, Harry Hsieh, Felice Balarin, Yosinori Watanabe
2003	A*	`conf`	Automatic trace analysis for logic of constraints. DAC Xi Chen, Harry Hsieh, Felice Balarin, Yosinori Watanabe
2003	—	`conf`	Case Studies of Model Checking for Embedded System Designs. ACSD Xi Chen, Harry Hsieh, Felice Balarin, Yosinori Watanabe
2003	J	`jnl`	Formal Verification for Embedded System Designs. Des. Autom. Embed. Syst. Xi Chen, Harry Hsieh, Felice Balarin, Yosinori Watanabe
2003	A*	`conf`	Gain-based technology mapping for discrete-size cell libraries. DAC Bo Hu, Yosinori Watanabe, Alex Kondratyev, Malgorzata Marek-Sadowska
2003	J	`jnl`	Metropolis: An Integrated Electronic System Design Environment. Computer Felice Balarin, Yosinori Watanabe, Harry Hsieh, Luciano Lavagno, Claudio Passerone, Alberto L. Sangiovanni-Vincentelli
2003	—	`conf`	Quasi-Static Scheduling for Concurrent Architectures. ACSD Jordi Cortadella, Alex Kondratyev, Luciano Lavagno, Yosinori Watanabe
2003	—	`ch.`	Simulation Trace Verification for Quantitative Constraints. Embedded Software for SoC Xi Chen, Harry Hsieh, Felice Balarin, Yosinori Watanabe
2003	—	`ch.`	State Space Compression in History Driven Quasi-Static Scheduling. Embedded Software for SoC Antonio G. Lomeña, Marisa López-Vallejo, Yosinori Watanabe, Alex Kondratyev
2003	A*	`conf`	Temporofunctional crosstalk noise analysis. DAC Donald Chai, Alex Kondratyev, Yajun Ran, Kenneth H. Tseng, Yosinori Watanabe, Malgorzata Marek-Sadowska
2003	—	`conf`	Verifying LOC based functional and performance constraints. HLDVT Xi Chen, Harry Hsieh, Felice Balarin, Yosinori Watanabe
2002	—	`conf`	Concurrent execution semantics and sequential simulation algorithms for the metropolis meta-model. CODES Felice Balarin, Luciano Lavagno, Claudio Passerone, Alberto L. Sangiovanni-Vincentelli, Yosinori Watanabe, Guang Yang
2002	A	`conf`	False Path Elimination in Quasi-Static Scheduling. DATE G. Arrigoni, L. Duchini, Claudio Passerone, Luciano Lavagno, Yosinori Watanabe
2002	—	`conf`	Formal verification of embedded system designs at multiple levels of abstraction. HLDVT Xi Chen, Fang Chen, Harry Hsieh, Felice Balarin, Yosinori Watanabe
2002	—	`conf`	Modeling and Designing Heterogeneous Systems. Concurrency and Hardware Design Felice Balarin, Luciano Lavagno, Claudio Passerone, Alberto L. Sangiovanni-Vincentelli, Marco Sgroi, Yosinori Watanabe
2002	Misc	`conf`	Processes, Interfaces and Platforms. Embedded Software Modeling in Metropolis. EMSOFT Felice Balarin, Luciano Lavagno, Claudio Passerone, Yosinori Watanabe
2002	—	`conf`	Quasi-Static Scheduling of Independent Tasksfor Reactive Systems. ICATPN Jordi Cortadella, Alex Kondratyev, Luciano Lavagno, Claudio Passerone, Yosinori Watanabe
2001	—	`conf`	Constraints specification at higher levels of abstraction. HLDVT Felice Balarin, Jerry R. Burch, Luciano Lavagno, Yosinori Watanabe, Roberto Passerone, Alberto L. Sangiovanni-Vincentelli
2001	A	`conf`	Generation of minimal size code for scheduling graphs. DATE Claudio Passerone, Yosinori Watanabe, Luciano Lavagno
2000	A*	`conf`	Area and search space control for technology mapping. DAC Dirk-Jan Jongeneel, Yosinori Watanabe, Robert K. Brayton, Ralph H. J. M. Otten
2000	A*	`conf`	Task generation and compile-time scheduling for mixed data-control embedded software. DAC Jordi Cortadella, Alex Kondratyev, Luciano Lavagno, Marc Massot, Sandra Moral, Claudio Passerone, Yosinori Watanabe, Alberto L. Sangiovanni-Vincentelli
1999	—	`conf`	Designing digital video systems: modeling and scheduling. CODES H. J. H. N. Kenter, Claudio Passerone, W. J. M. Smits, Yosinori Watanabe, Alberto L. Sangiovanni-Vincentelli
1999	—	`conf`	Quasi-Static Scheduling of Embedded Software Using Equal Conflict Nets. ICATPN Marco Sgroi, Luciano Lavagno, Yosinori Watanabe, Alberto L. Sangiovanni-Vincentelli
1997	J	`jnl`	Logic decomposition during technology mapping. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Eric Lehman, Yosinori Watanabe, Joel Grodstein, Heather Harkness
1996	J	`jnl`	Permissible functions for multioutput components in combinational logic optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yosinori Watanabe, Lisa M. Guerra, Robert K. Brayton
1995	A	`conf`	A delay model for logic synthesis of continuously-sized networks. ICCAD Joel Grodstein, Eric Lehman, Heather Harkness, Bill Grundmann, Yosinori Watanabe
1995	A	`conf`	Logic decomposition during technology mapping. ICCAD Eric Lehman, Yosinori Watanabe, Joel Grodstein, Heather Harkness
1994	—	`conf`	State Minimization of Pseudo Non-Deterministic FSM's. EDAC-ETC-EUROASIC Yosinori Watanabe, Robert K. Brayton
1993	C	`conf`	Heuristic Minimization of Synchronous Relations. ICCD Vigyan Singhal, Yosinori Watanabe, Robert K. Brayton
1993	J	`jnl`	Heuristic minimization of multiple-valued relations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yosinori Watanabe, Robert K. Brayton
1993	C	`conf`	Logic Optimization with Multi-Output Gates. ICCD Yosinori Watanabe, Lisa M. Guerra, Robert K. Brayton
1993	A	`conf`	The maximum set of permissible behaviors for FSM networks. ICCAD Yosinori Watanabe, Robert K. Brayton
1991	A	`conf`	Heuristic Minimazation of Multiple-Valued Relations. ICCAD Yosinori Watanabe, Robert K. Brayton
1991	C	`conf`	Incremental Synthesis for Engineering Changes. ICCD Yosinori Watanabe, Robert K. Brayton