Yoshitaka Murasaka

12 papers Journal 4Unranked 8
YearRankTypeTitle / Venue / Authors
2020 J jnl
CMOS Gaussian Monocycle Pulse Transceiver for Radar-Based Microwave Imaging.
IEEE Trans. Biomed. Circuits Syst.
Takamaro Kikkawa, Yoshihiro Masui, Akihiro Toya, Hiroyuki Ito, Takuichi Hirano, Tomoaki Maeda, Masahiro Ono, Yoshitaka Murasaka, Toshifumi Imamura, Tsuyoshi Matsumaru, Michimasa Yamaguchi, Mitsutoshi Sugawara, Afreen Azhari, Hang Song, Shinsuke Sasada, Atsushi Iwata
2019 — conf
Shifting Clock Jitter and Phase Interval for Impulse-Radar-Based Breast Cancer Detection.
BioCAS
Akihiro Toya, Takamaro Kikkawa, Yoshihiro Masui, Mitsutoshi Sugawara, Hiroyuki Ito, Tomoaki Maeda, Masahiro Ono, Yoshitaka Murasaka, Toshifumi Imamura, Atsushi Iwata
2018 — conf
Gaussian Monocycle Pulse Generator with Calibration Circuit for Breast Cancer Detection.
BioCAS
Yoshihiro Masui, Akihiro Toya, Mitsutoshi Sugawara, Tomoaki Maeda, Masahiro Ono, Yoshitaka Murasaka, Atsushi Iwata, Takamaro Kikkawa
2017 — conf
Differential equivalent time sampling receiver for breast cancer detection.
BioCAS
Yoshihiro Masui, Akihiro Toya, Mitsutoshi Sugawara, Tomoaki Maeda, Masahiro Ono, Yoshitaka Murasaka, Atsushi Iwata, Takamaro Kikkawa
2017 — conf
Investigation of phase noise and jitter in CMOS sampling clock generation circuits for time-domain breast cancer detection system.
BioCAS
Akihiro Toya, Yoshihiro Masui, Mitsutoshi Sugawara, Tomoaki Maeda, Masahiro Ono, Yoshitaka Murasaka, Atsushi Iwata, Takamaro Kikkawa
2011 J jnl
Background Calibration Techniques for Low-Power and High-Speed Data Conversion.
IEICE Trans. Electron.
Atsushi Iwata, Yoshitaka Murasaka, Tomoaki Maeda, Takafumi Ohmoto
2007 J jnl
Chip-Level Substrate Coupling Analysis with Reference Structures for Verification.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Daisuke Kosaka, Makoto Nagata, Yoshitaka Murasaka, Atsushi Iwata
2007 — conf
Chip-Level Substrate Noise Analysis with Emphasis of Vertical Impurity Profile for Isolation.
CICC
Daisuke Kosaka, Makoto Nagata, Yoshitaka Murasaka, Atsushi Iwata
2007 J jnl
Evaluation of Isolation Structures against High-Frequency Substrate Coupling in Analog/Mixed-Signal Integrated Circuits.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Daisuke Kosaka, Makoto Nagata, Yoshitaka Murasaka, Atsushi Iwata
2007 — conf
On-Die Supply-Voltage Noise Sensor with Real-Time Sampling Mode for Low-Power Processor Applications.
ISSCC
Tomio Sato, Atsuki Inoue, Tetsuyoshi Shiota, Tomoko Inoue, Yukihito Kawabe, Tetsutaro Hashimoto, Toshifumi Imamura, Yoshitaka Murasaka, Makoto Nagata, Atsushi Iwata
2002 — conf
Substrate Noise Analysis with Compact Digital Noise Injection and Substrate Models.
ASP-DAC/VLSI Design
Makoto Nagata, Yoshitaka Murasaka, Youichi Nishimori, Takashi Morie, Atsushi Iwata
2001 — conf
Chip-Level Substrate Noise Analysis with Network Reduction by Fundamental Matrix Computation.
ISQED
Yoshitaka Murasaka, Makoto Nagata, Takafumi Ohmoto, Takashi Morie, Atsushi Iwata