Yoshisato Yokoyama

11 papers Journal 3Unranked 8
YearRankTypeTitle / Venue / Authors
2025 J jnl
A 3 nm-FinFET 4.3 GHz 21.1 Mb/mm
IEEE J. Solid State Circuits
Masaru Haraguchi, Yorinobu Fujino, Yoshisato Yokoyama, Ming-Hung Chang, Yu-Hao Hsu, Hong-Chen Cheng, Koji Nii, Yih Wang, Tsung-Yung Jonathan Chang
2024 — conf
15.3 A 3nm FinFET 4.3GHz 21.1Mb/mm2 Double-Pumping 1-Read and 1-Write Pseudo-2-Port SRAM with Folded-Bitline Multi-Bank Architecture.
ISSCC
Masaru Haraguchi, Yorinobu Fujino, Yoshisato Yokoyama, Ming-Hung Chang, Yu-Hao Hsu, Hong-Chen Cheng, Koji Nii, Yih Wang, Tsung-Yung Jonathan Chang
2023 J jnl
Disturbance Aware Dynamic Power Reduction in Synchronous 2RW Dual-Port 8T SRAM by Self-Adjusting Wordline Pulse Timing.
IEEE J. Solid State Circuits
Yoshisato Yokoyama, Koji Nii, Yuichiro Ishii, Shinji Tanaka, Kazutoshi Kobayashi
2021 J jnl
Cost-Effective Test Screening Method on 40-nm Embedded SRAMs for Low-Power MCUs.
IEEE Trans. Very Large Scale Integr. Syst.
Yoshisato Yokoyama, Yuichiro Ishii, Koji Nii, Kazutoshi Kobayashi
2020 — conf
A 29.2 Mb/mm
VLSI Circuits
Yoshisato Yokoyama, Miki Tanaka, Koji Tanaka, Masao Morimoto, Makoto Yabuuchi, Yuichiro Ishii, Shinji Tanaka
2019 — conf
A Cost Effective Test Screening Circuit for embedded SRAM with Resume Standby on 110-nm SoC/MCU.
A-SSCC
Yoshisato Yokoyama, Kenji Goto, Tomohiro Miura, Yukari Ouchi, Daisuke Nakamura, Jiro Ishikawa, Shunya Nagata, Yoshiki Tsujihashi, Yuichiro Ishii
2018 — conf
40-nm 64-kbit Buffer/Backup SRAM with 330 nW Standby Power at 65°C Using 3.3 V IO MOSs for PMIC less MCU in IoT Applications.
A-SSCC
Yoshisato Yokoyama, Tomohiro Miura, Yukari Ouchi, Daisuke Nakamura, Jiro Ishikawa, Shunya Nagata, Makoto Yabuuchi, Yuichiro Ishii, Koji Nii
2017 — conf
A dynamic power reduction in synchronous 2RW 8T dual-port SRAM by adjusting wordline pulse timing with same/different row access mode.
A-SSCC
Yoshisato Yokoyama, Yuichiro Ishii, Haruyuki Okuda, Koji Nii
2015 — conf
A cost effective test screening method on 40-nm 4-Mb embedded SRAM for low-power MCU.
A-SSCC
Yoshisato Yokoyama, Yuichiro Ishii, Toshihiro Inada, Koji Tanaka, Miki Tanaka, Yoshiki Tsujihashi, Koji Nii
2014 — conf
40 nm Dual-port and two-port SRAMs for automotive MCU applications under the wide temperature range of -40 to 170°C with test screening against write disturb issues.
A-SSCC
Yoshisato Yokoyama, Yuichiro Ishii, Koji Tanaka, Tatsuya Fukuda, Yoshiki Tsujihashi, Atsushi Miyanishi, Shinobu Asayama, Keiichi Maekawa, Kazutoshi Shiba, Koji Nii
2014 — conf
40nm Ultra-low leakage SRAM at 170 deg.C operation for embedded flash MCU.
ISQED
Yoshisato Yokoyama, Yuichiro Ishii, Hidemitsu Kojima, Atsushi Miyanishi, Yoshiki Tsujihashi, Shinobu Asayama, Kazutoshi Shiba, Koji Tanaka, Tatsuya Fukuda, Koji Nii, Kazumasa Yanagisawa