Yoshio Matsuda

57 papers A* 1A 2C 4Journal 33Unranked 17

Year	Rank	Type	Title / Venue / Authors
2022	J	`jnl`	Users' Content Memorization in Multi-User Interactive Public Displays. Int. J. Hum. Comput. Interact. Narumi Sugiura, Rikako Ogura, Yoshio Matsuda, Takashi Komuro, Kayo Ogawa
2020	A	`conf`	Dynamic layout optimization for multi-user interaction with a large display. IUI Yoshio Matsuda, Takashi Komuro
2020	—	`conf`	Palm-Controlled Pointing Interface Using a Dynamic Photometric Stereo Camera. HCI (48) Yoshio Matsuda, Takashi Komuro, Takuya Yoda, Hajime Nagahara, Shoji Kawahito, Keiichiro Kagawa
2019	J	`jnl`	A Cost-Effective 1T-4MTJ Embedded MRAM Architecture with Voltage Offset Self-Reference Sensing Scheme for IoT Applications. IEICE Trans. Electron. Masanori Hayashikoshi, Hiroaki Tanizaki, Yasumitsu Murai, Takaharu Tsuji, Kiyoshi Kawabata, Koji Nii, Hideyuki Noda, Hiroyuki Kondo, Yoshio Matsuda, Hideto Hidaka
2019	—	`conf`	Design and Implementation of Ultra-Low-Latency Video Encoder Using High-Level Synthesis. ISPACS Kosuke Fukava, Kaito Mori, Kousuke Imamura, Yoshio Matsuda, Tetsuya Matsumura, Seiji Mochizuki
2019	—	`conf`	Scalable Architecture for High-Resolution Real-time Optical Flow Processor. IoTaIS Kousuke Imamura, Satoshi Kanda, Saya Ohira, Yoshio Matsuda, Tetsuya Matsumura
2019	—	`conf`	Simultaneous interaction with a large display by many users. PerDis Yuriko Sakakibara, Yoshio Matsuda, Takashi Komuro, Kayo Ogawa
2018	—	`conf`	A Multi-user Interactive Public Display with Dynamic Layout Optimization. PerDis Yoshio Matsuda, Takashi Komuro
2018	J	`jnl`	High-Performance Super-Resolution via Patch-Based Deep Neural Network for Real-Time Implementation. IEICE Trans. Inf. Syst. Reo Aoki, Kousuke Imamura, Akihiro Hirano, Yoshio Matsuda
2018	J	`jnl`	Low-Power Multi-Sensor System with Power Management and Nonvolatile Memory Access Control for IoT Applications. IEEE Trans. Multi Scale Comput. Syst. Masanori Hayashikoshi, Hideyuki Noda, Hiroyuki Kawai, Yasumitsu Murai, Sugako Otani, Koji Nii, Yoshio Matsuda, Hiroyuki Kondo
2018	—	`conf`	Ultra-low-latency Video Coding Method for Autonomous Vehicles and Virtual Reality Devices. IOTAIS Seiji Mochizuki, Kousuke Imamura, Kaito Mori, Yoshio Matsuda, Tetsuya Matsumura
2017	J	`jnl`	A 100-MHz 51.2-Gb/s Packet Lookup Engine with Automatic Table Update Function. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Kousuke Imamura, Ryota Honda, Yoshifumi Kawamura, Naoki Miura, Masami Urano, Satoshi Shigematsu, Tetsuya Matsumura, Yoshio Matsuda
2017	J	`jnl`	Design and Implementation of 176-MHz WXGA 30-fps Real-Time Optical Flow Processor. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Yu Suzuki, Masato Ito, Satoshi Kanda, Kousuke Imamura, Yoshio Matsuda, Tetsuya Matsumura
2016	J	`jnl`	A Field Programmable Sequencer and Memory with Middle Grained Programmability Optimized for MCU Peripherals. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Yoshifumi Kawamura, Naoya Okada, Yoshio Matsuda, Tetsuya Matsumura, Hiroshi Makino, Kazutami Arimoto
2016	—	`conf`	A study on fast motion estimation algorithm. GCCE Masahiro Hiramori, Ryota Bandou, Shuhei Iwade, Hiroshi Makino, Tsutomu Yoshimura, Yoshio Matsuda
2016	—	`conf`	A study on motion estimation algorithm for moving pictures. GCCE Ryota Bnadou, Masahiro Hiramori, Shuhei Iwade, Hiroshi Makino, Tutomu Yoshimura, Yoshio Matsuda
2016	—	`conf`	Automatic rule registration and deletion function on a packet lookup engine LSI. ISPACS Tetsuya Matsumura, Kousuke Imamura, Yoshifumi Kawamura, Yoshio Matsuda
2016	—	`conf`	Image denoising using non-local means for Poisson noise. ISPACS Kousuke Imamura, Naoki Kimura, Fumiaki Satou, Shigeru Sanada, Yoshio Matsuda
2015	—	`conf`	A 100-MHz 51.2-Gb/s packet lookup engine LSI based on missmatch detection circuit combined with linked-list hash table. ISPACS Yoshifumi Kawamura, Kousuke Imamura, Naoki Miura, Masami Urano, Satoshi Shigematsu, Yoshio Matsuda
2015	C	`conf`	A Design for the 178-MHz WXGA 30-fps Optical Flow Processor Based on the HOE Algorithm. DDECS Tetsuya Matsumura, Aoi Kurokawa, Kousuke Imamura, Yoshio Matsuda
2015	—	`conf`	A fast atom selection method based on the order of initial inner product values for image denoising using sparse representation. ISPACS Kousuke Imamura, Kaoru Itoh, Yoshio Matsuda
2014	—	`conf`	A new stepwise adiabatic charging circuit with a smaller capacitance in a regenerator than a load capacitance. MWSCAS Shunji Nakata, Hiroshi Makino, Yoshio Matsuda
2014	J	`jnl`	Analysis of voltage, Current and Energy dissipation of Stepwise Adiabatic Charging of a capacitor using a nonresonant inductor Current. J. Circuits Syst. Comput. Shunji Nakata, Hiroshi Makino, Ryota Honda, Masayuki Miyama, Yoshio Matsuda
2014	J	`jnl`	Energy Efficient Stepwise Charging of a Capacitor Using a DC-DC Converter With Consecutive Changes of its Duty Ratio. IEEE Trans. Circuits Syst. I Regul. Pap. Shunji Nakata, Hiroshi Makino, Junpei Hosokawa, Tsutomu Yoshimura, Shuhei Iwade, Yoshio Matsuda
2014	J	`jnl`	Increase in Read Noise Margin of Single-Bit-Line SRAM Using Adiabatic Change of Word Line Voltage. IEEE Trans. Very Large Scale Integr. Syst. Shunji Nakata, Hiroki Hanazono, Hiroshi Makino, Hiroki Morimura, Masayuki Miyama, Yoshio Matsuda
2014	C	`conf`	The LSI implementation of a memory based field programmable device for MCU peripherals. DDECS Tetsuya Matsumura, Naoya Okada, Yoshifumi Kawamura, Koji Nii, Kazutami Arimoto, Hiroshi Makino, Yoshio Matsuda
2013	—	`conf`	A cost-effective 45nm 6T-SRAM reducing 50mV Vmin and 53% standby leakage with multi-Vt asymmetric halo MOS and write assist circuitry. ISQED Koji Nii, Makoto Yabuuchi, Hidehiro Fujiwara, Yasumasa Tsukamoto, Yuichiro Ishii, Tetsuya Matsumura, Yoshio Matsuda
2013	J	`jnl`	Analysis of Pull-in Range Limit by Charge Pump Mismatch in a Linear Phase-Locked Loop. IEEE Trans. Circuits Syst. I Regul. Pap. Tsutomu Yoshimura, Shuhei Iwade, Hiroshi Makino, Yoshio Matsuda
2012	—	`conf`	Energy dissipation reduction during adiabatic charging and discharging with controlled inductor current. MWSCAS Shunji Nakata, Ryota Honda, Hiroshi Makino, Hiroki Morimura, Yoshio Matsuda
2012	J	`jnl`	General Stability of Stepwise Waveform of an Adiabatic Charge Recycling Circuit With Any Circuit Topology. IEEE Trans. Circuits Syst. I Regul. Pap. Shunji Nakata, Ryota Honda, Hiroshi Makino, Shin'ichiro Mutoh, Masayuki Miyama, Yoshio Matsuda
2012	J	`jnl`	Utilising the normal distribution of the write noise margin to easily predict the SRAM write yield. IET Circuits Devices Syst. Hiroshi Makino, Shunji Nakata, Hirotsugu Suzuki, Shin'ichiro Mutoh, Masayuki Miyama, Tsutomu Yoshimura, Shuhei Iwade, Yoshio Matsuda
2011	J	`jnl`	Reexamination of SRAM Cell Write Margin Definitions in View of Predicting the Distribution. IEEE Trans. Circuits Syst. II Express Briefs Hiroshi Makino, Shunji Nakata, Hirotsugu Suzuki, Shin'ichiro Mutoh, Masayuki Miyama, Tsutomu Yoshimura, Shuhei Iwade, Yoshio Matsuda
2011	—	`conf`	Vehicle detection and tracking with affine motion segmentation in stereo video. ICSIPA Masayuki Miyama, Yoshio Matsuda
2010	J	`jnl`	A Complete Charge Recycling TCAM with Checkerboard Array Arrangement for Low Power Applications. IEICE Trans. Electron. Katsumi Dosaka, Daisuke Ogawa, Takahito Kusumoto, Masayuki Miyama, Yoshio Matsuda
2010	J	`jnl`	A VGA 30 fps Affine Motion Model Estimation VLSI for Real-Time Video Segmentation. IEICE Trans. Inf. Syst. Yoshiki Yunbe, Masayuki Miyama, Yoshio Matsuda
2010	C	`conf`	Adiabatic SRAM with a shared access port using a controlled ground line and step-voltage circuit. ISCAS Shunji Nakata, Hirotsugu Suzuki, Ryota Honda, Takahito Kusumoto, Shin'ichiro Mutoh, Hiroshi Makino, Masayuki Miyama, Yoshio Matsuda
2010	J	`jnl`	Adiabatic charging and discharging method with minimum energy dissipation for a variable-gap capacitor system. IET Circuits Devices Syst. Shunji Nakata, Masayuki Miyama, Yoshio Matsuda
2010	J	`jnl`	Stable adiabatic circuit using advanced series capacitors and time variation of energy dissipation. IEICE Electron. Express Shunji Nakata, Shin'ichiro Mutoh, Hiroshi Makino, Masayuki Miyama, Yoshio Matsuda
2009	C	`conf`	Adiabatic SRAM with a Large Margin of VT Variation by Controlling the Cell-power-line and Word-line Voltage. ISCAS Shunji Nakata, Takahito Kusumoto, Masayuki Miyama, Yoshio Matsuda
2008	J	`jnl`	A 158 MS/s JPEG 2000 Codec with a Bit-Plane and Pass Parallel Embedded Block Coder for Low Delay Image Transmission. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Masayuki Miyama, Yuusuke Inoie, Takafumi Kasuga, Ryouichi Inada, Masashi Nakao, Yoshio Matsuda
2008	J	`jnl`	A VGA 30-fps Realtime Optical-Flow Processor Core for Moving Picture Recognition. IEICE Trans. Electron. Yuichiro Murachi, Yuki Fukuyama, Ryo Yamamoto, Junichi Miyakoshi, Hiroshi Kawaguchi, Hajime Ishihara, Masayuki Miyama, Yoshio Matsuda, Masahiko Yoshimoto
2000	J	`jnl`	A 3.6-Gb/s 340-mW 16: 1 pipe-lined multiplexer using 0.18 μm SOI-CMOS technology. IEEE J. Solid State Circuits Toru Nakura, Kimio Ueda, Kazuo Kubo, Yoshio Matsuda, Koichiro Mashiko, Tsutomu Yoshihara
2000	—	`conf`	Novel VLIW code compaction method for a 3D geometry processor. CICC Hiroaki Suzuki, Hiroshi Making, Yoshio Matsuda
1999	J	`jnl`	Source-synchronization and timing vernier techniques for 1.2-GB/s SLDRAM interface. IEEE J. Solid State Circuits Yasunobu Nakase, Yoshikazu Morooka, David J. Perlman, Daniel J. Kolor, Jae-Myoung Choi, Hyun J. Shin, Tsutomu Yoshimura, Naoya Watanabe, Yoshio Matsuda, Masaki Kumanoya, Michihiro Yamada
1999	J	`jnl`	The D30V/MPEG multimedia processor. IEEE Micro Hidehiro Takata, Tetsuya Watanabe, Tetsuo Nakajima, Takashi Takagaki, Hisakazu Sato, Atsushi Mohri, Akira Yamada, Toshiki Kanamoto, Yoshio Matsuda, Shuhei Iwade, Yasutaka Horiba
1997	J	`jnl`	Scalable Shared-Buffering ATM Switch with a Versatile Searchable Queue. IEEE J. Sel. Areas Commun. Hideaki Yamanaka, Hirotaka Saito, Harufusa Kondoh, Yasuhito Sasaki, Hirotoshi Yamada, Munenori Tsuzuki, Satoshi Nishio, Hiromi Notani, Atsushi Iwabu, Masahiko Ishiwaki, Shigeki Kohama, Yoshio Matsuda, Kazuyoshi Oshima
1996	J	`jnl`	A 622-Mb/s bit/frame synchronizer for high-speed backplane data communication. IEEE J. Solid State Circuits Tsutomu Yoshimura, Harufusa Kondoh, Yoshio Matsuda, Tadashi Sumi
1994	A*	`conf`	Multicast Function and its LSI Implementation in a Shared Multibuffer ATM Switch. INFOCOM Hirotaka Saito, Hideaki Yamanaka, Hirotoshi Yamada, Munenori Tsuzuki, Harufusa Kondoh, Yoshio Matsuda, Kazuyoshi Oshima
1993	J	`jnl`	A 622-Mb/s 8*8 ATM switch chip set with shared multibuffer architecture. IEEE J. Solid State Circuits Harufusa Kondoh, Hiromi Notani, Hideaki Yamanaka, Keiichi Higashitani, Hirotaka Saito, Isamu Hayashi, Shigeki Kohama, Yoshio Matsuda, Kazuyoshi Oshima, Masao Nakaya
1991	J	`jnl`	A circuit design of intelligent cache DRAM with automatic write-back capability. IEEE J. Solid State Circuits Kazutami Arimoto, Mikio Asakura, Hideto Hidaka, Yoshio Matsuda, Kazuyasu Fujishima
1991	J	`jnl`	A divided/shared bit-line sensing scheme for ULSI DRAM cores. IEEE J. Solid State Circuits Hideto Hidaka, Yoshio Matsuda, Kazuyasu Fujishima
1990	J	`jnl`	A speed-enhanced DRAM array architecture with embedded ECC. IEEE J. Solid State Circuits Kazutami Arimoto, Yoshio Matsuda, Kiyohiro Furutani, Masaki Tsukude, Tsukasa Ooishi, Koichiro Mashiko, Kuzuyasu Fujishima
1990	J	`jnl`	An experimental 1-Mbit cache DRAM with ECC. IEEE J. Solid State Circuits Mikio Asakura, Yoshio Matsuda, Hidaka Hidaka, Yoshinori Tanaka, Kazuyasu Fujishima
1990	J	`jnl`	The cache DRAM architecture: a DRAM with an on-chip cache memory. IEEE Micro Hideto Hidaka, Yoshio Matsuda, Mikio Asakura, Kazuyasu Fujishima
1989	J	`jnl`	A 60-ns 3.3-V-only 16-Mbit DRAM with multipurpose register. IEEE J. Solid State Circuits Kazutami Arimoto, Kazuyasu Fujishima, Yoshio Matsuda, Masaki Tsukude, Tukasa Oishi, Wataru Wakamiya, Shin'ichi Satoh, Michihiro Yamada, Takao Nakano
1989	A	`conf`	A New Array Architecture for Parallel Testing in VLSI Memories. ITC Yoshio Matsuda, Kazutami Arimoto, Masaki Tsukude, Tsukasa Oishi, Kazuyasu Fujishima
1989	J	`jnl`	Twisted bit-line architectures for multi-megabit DRAMs. IEEE J. Solid State Circuits Hideto Hidaka, Kazuyasu Fujishima, Yoshio Matsuda, Mikio Asakura, Tsutomu Yoshihara