Yoshinobu Nakagome

21 papers Journal 21

Year	Rank	Type	Title / Venue / Authors
2004	J	`jnl`	Introduction to the Special Issue. IEEE J. Solid State Circuits Yoshinobu Nakagome, Bruce Gieseke
2003	J	`jnl`	Guest Editorial. IEEE J. Solid State Circuits Shekhar Borkar, Yoshinobu Nakagome
2003	J	`jnl`	Review and future prospects of low-voltage RAM circuits. IBM J. Res. Dev. Yoshinobu Nakagome, Masashi Horiguchi, Takayuki Kawahara, Kiyoo Itoh
1999	J	`jnl`	A 5-GByte/s data-transfer scheme with bit-to-bit skew control for synchronous DRAM. IEEE J. Solid State Circuits Takashi Sato, Yoji Nishio, Toshio Sugano, Yoshinobu Nakagome
1997	J	`jnl`	A modular architecture for a 6.4-Gbyte/s, 8-Mb DRAM-integrated media chip. IEEE J. Solid State Circuits Takao Watanabe, Ryo Fujita, Kazumasa Yanagisawa, Hitoshi Tanaka, Kazushige Ayukawa, Mitsuru Soga, Yuji Tanaka, Yoshimitsu Sugie, Yoshinobu Nakagome
1997	J	`jnl`	Limitations and challenges of multigigabit DRAM chip design. IEEE J. Solid State Circuits Kiyoo Itoh, Yoshinobu Nakagome, Shin'ichiro Kimura, Takao Watanabe
1995	J	`jnl`	A 2.6-ns wave-pipelined CMOS SRAM with dual-sensing-latch circuits. IEEE J. Solid State Circuits Suguru Tachibana, Hisayuki Higuchi, Koichi Takasugi, Katsuro Sasaki, Toshiaki Yamanaka, Yoshinobu Nakagome
1995	J	`jnl`	A 4.4 ns CMOS 54⨉54-b multiplier using pass-transistor multiplexer. IEEE J. Solid State Circuits Norio Ohkubo, Makoto Suzuki, Toshinobu Shinbo, Toshiaki Yamanaka, Akihiro Shimizu, Katsuro Sasaki, Yoshinobu Nakagome
1995	J	`jnl`	An experimental 220-MHz 1-Gb DRAM with a distributed-column-control architecture. IEEE J. Solid State Circuits Takeshi Sakata, Masashi Horiguchi, Tomonori Sekiguchi, Shigeki Ueda, Hitoshi Tanaka, Eiji Yamasaki, Yoshinobu Nakagome, Masakazu Aoki, Toru Kaga, Makoto Ohkura, Ryo Nagai, Fumio Murai, Toshihiko Tanaka, Shimpei Iijima, Natsuki Yokoyama, Yasushi Gotoh, Ken'ichi Shoji, Teruaki Kisu, Hisaomi Yamashita, Takashi Nishida, Eiji Takeda
1995	J	`jnl`	Low-noise, high-speed data transmission using a ringing-canceling output buffer. IEEE J. Solid State Circuits Tomonori Sekiguchi, Masashi Horiguchi, Takeshi Sakata, Yoshinobu Nakagome, Shigeki Ueda, Masakazu Aoki
1995	J	`jnl`	Trends in low-power RAM circuit technologies. Proc. IEEE Kiyoo Itoh, Katsuro Sasaki, Yoshinobu Nakagome
1994	J	`jnl`	Sub-1-μA dynamic reference voltage generator for battery-operated DRAMs. IEEE J. Solid State Circuits Hitoshi Tanaka, Yoshinobu Nakagome, Jun Etoh, Eiji Yamasaki, Masakazu Aoki, Kazuyuki Miyazawa
1993	J	`jnl`	A 1.5-ns 32-b CMOS ALU in double pass-transistor logic. IEEE J. Solid State Circuits Makoto Suzuki, Norio Ohkubo, Toshinobu Shinbo, Toshiaki Yamanaka, Akihiro Shimizu, Katsuro Sasaki, Yoshinobu Nakagome
1993	J	`jnl`	Sub-1-V swing internal bus architecture for future low-power ULSIs. IEEE J. Solid State Circuits Yoshinobu Nakagome, Kiyoo Itoh, Masanori Isoda, Kan Takeuchi, Masakazu Aoki
1992	J	`jnl`	An experimental single-chip data flow CPU. IEEE J. Solid State Circuits Gregory A. Uvieghara, Wen-mei W. Hwu, Yoshinobu Nakagome, Deog-Kyoon Jeong, David D. Lee, David A. Hodges, Yale N. Patt
1991	J	`jnl`	A circuit technology for sub-10-ns ECL 4-Mb BiCMOS DRAM's. IEEE J. Solid State Circuits Takayuki Kawahara, Yoshiki Kawajiri, Goro Kitsukawa, Yoshinobu Nakagome, Kazuhiko Sagara, Yoshifumi Kawamoto, Takesada Akiba, Shisei Kato, Yasushi Kawase, Kiyoo Itoh
1991	J	`jnl`	An experimental 1.5-V 64-Mb DRAM. IEEE J. Solid State Circuits Yoshinobu Nakagome, Hitoshi Tanaka, Kan Takeuchi, Eiji Kume, Yasushi Watanabe, Toru Kaga, Yoshifumi Kawamoto, Fumio Murai, Ryuichi Izawa, Digh Hisamoto, Teruaki Kisu, Takashi Nishida, Eiji Takeda, Kiyoo Itoh
1991	J	`jnl`	Circuit techniques for 1.5-3.6-V battery-operated 64-Mb DRAM. IEEE J. Solid State Circuits Yoshinobu Nakagome, Kiyoo Itoh, Kan Takeuchi, Eiji Kume, Hitoshi Tanaka, Masanori Isoda, Tatsunori Musha, Toru Kaga, Teruaki Kisu, Takashi Nishida, Yoshifumi Kawamoto, Masakazu Aoki
1990	J	`jnl`	An on-chip smart memory for a data-flow CPU. IEEE J. Solid State Circuits Gregory A. Uvieghara, Yoshinobu Nakagome, Deog-Kyoon Jeong, David A. Hodges
1989	J	`jnl`	New DRAM noise generation under half-V IEEE J. Solid State Circuits Masakazu Aoki, Shin'ichi Ikenaga, Yoshinobu Nakagome, Masashi Horiguchi, Yasushi Kawase, Yoshifumi Kawamoto, Kiyoo Itoh
1988	J	`jnl`	An experimental large-capacity semiconductor file memory using 16-levels/cell storage. IEEE J. Solid State Circuits Masashi Horiguchi, Masakazu Aoki, Yoshinobu Nakagome, Shin'ichi Ikenaga, Katsuhiro Shimohigashi