Yoshinobu Higami

95 papers A 2B 2C 2Misc 4Journal 31Unranked 50

Year	Rank	Type	Title / Venue / Authors
2025	J	`jnl`	A Spatio-Temporal Graph Neural Networks Approach for Predicting Silent Data Corruption inducing Circuit-Level Faults. CoRR Shaoqi Wei, Senling Wang, Hiroshi Kai, Yoshinobu Higami, Ruijun Ma, Tianming Ni, Xiaoqing Wen, Hiroshi Takahashi
2025	J	`jnl`	SASL-JTAG+: An Enhanced Lightweight and Secure JTAG Authentication Mechanism for IoT Systems with Diverse Devices. J. Commun. Hisashi Okamoto, Shaoqi Wei, Senling Wang, Hiroshi Kai, Hiroshi Takahashi, Yoshinobu Higami, Akihiro Shimizu, Tianming Ni, Xiaoqing Wen
2025	—	`conf`	Software-Defined Secure Island for Testing Chiplet Systems. ATS Hisashi Okamoto, Senling Wang, Hiroshi Kai, Hiroyuki Yotsuyanagi, Yoshinobu Higami, Tianming Ni, Tai Song, Hiroshi Takahashi, Xiaoqing Wen
2024	—	`conf`	Test Point Selection for Multi-Cycle Logic BIST using Multivariate Temporal-Spatial GCNs. ITC-Asia Senling Wang, Shaoqi Wei, Hisashi Okamoto, Tatusya Nishikawa, Hiroshi Kai, Yoshinobu Higami, Hiroyuki Yotsuyanagi, Ruijun Ma, Tianming Ni, Hiroshi Takahashi, Xiaoqing Wen
2024	J	`jnl`	Testing and Delay-Monitoring for the High Reliability of Memory-Based Programmable Logic Device. IEICE Trans. Inf. Syst. Xihong Zhou, Senling Wang, Yoshinobu Higami, Hiroshi Takahashi
2023	—	`conf`	SASL-JTAG: A Light-Weight Dependable JTAG. DFT Senling Wang, Shaoqi Wei, Jun Ma, Hiroshi Kai, Yoshinobu Higami, Hiroshi Takahashi, Akihiro Shimizu, Xiaoqing Wen, Tianming Ni
2023	J	`jnl`	Test Point Insertion for Multi-Cycle Power-On Self-Test. ACM Trans. Design Autom. Electr. Syst. Senling Wang, Xihong Zhou, Yoshinobu Higami, Hiroshi Takahashi, Hiroyuki Iwata, Yoichi Maeda, Jun Matsushima
2022	—	`conf`	Preliminary Study on Noise-Resilient Artificial Neural Networks for On-Chip Test Generation. GCCE Tsutomu Inamoto, Tomoki Nishino, Senling Wang, Yoshinobu Higami, Hiroshi Takahashi
2020	J	`jnl`	FF-Control Point Insertion (FF-CPI) to Overcome the Degradation of Fault Detection under Multi-Cycle Test for POST. IEICE Trans. Inf. Syst. Hanan T. Al-Awadhi, Tomoki Aono, Senling Wang, Yoshinobu Higami, Hiroshi Takahashi, Hiroyuki Iwata, Yoichi Maeda, Jun Matsushima
2020	J	`jnl`	Formulation of a Test Pattern Measure That Counts Distinguished Fault-Pairs for Circuit Fault Diagnosis. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Tsutomu Inamoto, Yoshinobu Higami
2018	J	`jnl`	Automotive Functional Safety Assurance by POST with Sequential Observation. IEEE Des. Test Senling Wang, Yoshinobu Higami, Hiroshi Takahashi, Hiroyuki Iwata, Jun Matsushima
2018	—	`conf`	Capture-Pattern-Control to Address the Fault Detection Degradation Problem of Multi-cycle Test in Logic BIST. ATS Senling Wang, Tomoki Aono, Yoshinobu Higami, Hiroshi Takahashi, Hiroyuki Iwata, Yoichi Maeda, Jun Matsushima
2018	J	`jnl`	Evaluation of educational applications in terms of communication delay between tablets with Bluetooth or Wi-Fi Direct. Vietnam. J. Comput. Sci. Keiichi Endo, Gakuto Fujioka, Ayame Onoyama, Dai Okano, Yoshinobu Higami, Shinya Kobayashi
2018	B	`conf`	Fault-detection-strengthened method to enable the POST for very-large automotive MCU in compliance with ISO26262. ETS Senling Wang, Yoshinobu Higami, Hiroshi Takahashi, Hiroyuki Iwata, Yoichi Maeda, Jun Matsushima
2017	J	`jnl`	A Method for Diagnosing Bridging Fault between a Gate Signal Line and a Clock Line. IEICE Trans. Inf. Syst. Yoshinobu Higami, Senling Wang, Hiroshi Takahashi, Shin-ya Kobayashi, Kewal K. Saluja
2017	—	`conf`	Comparative Evaluation of Bluetooth and Wi-Fi Direct for Tablet-Oriented Educational Applications. ACIIDS (1) Keiichi Endo, Ayame Onoyama, Dai Okano, Yoshinobu Higami, Shin-ya Kobayashi
2017	J	`jnl`	Discrimination of a Resistive Open Using Anomaly Detection of Delay Variation Induced by Transitions on Adjacent Lines. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Hiroyuki Yotsuyanagi, Kotaro Ise, Masaki Hashizume, Yoshinobu Higami, Hiroshi Takahashi
2017	—	`conf`	Harnessing Fuzziness of the Pragmatic Rule-Design Without IF-THEN Rules. FSDM Tsutomu Inamoto, Yoshinobu Higami
2017	—	`conf`	On selection of adjacent lines in test pattern generation for delay faults considering crosstalk effects. ISCIT Yuuya Ohama, Hiroyuki Yotsuyanagi, Masaki Hashizume, Yoshinobu Higami, Hiroshi Takahashi
2017	—	`conf`	Testing of Interconnect Defects in Memory Based Reconfigurable Logic Device (MRLD). ATS Senling Wang, Yoshinobu Higami, Hiroshi Takahashi, Masayuki Sato, Mitsunori Katsu, Shoichi Sekiguchi
2017	J	`jnl`	Trip-Based Integer Linear Programming Model for Static Multi-Car Elevator Operation Problems. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Tsutomu Inamoto, Yoshinobu Higami, Shin-ya Kobayashi
2016	—	`conf`	Design and Implementation of Data Synchronization and Offline Capabilities in Native Mobile Apps. ACIIDS (2) Kamoliddin Mavlonov, Tsutomu Inamoto, Yoshinobu Higami, Shin-ya Kobayashi
2016	J	`jnl`	Diagnosis Methods for Gate Delay Faults with Various Amounts of Delays. IPSJ Trans. Syst. LSI Des. Methodol. Yoshinobu Higami, Senling Wang, Hiroshi Takahashi, Shin-ya Kobayashi, Kewal K. Saluja
2016	—	`conf`	Evaluation of Influence Exerted by a Malicious Group's Various Aims in the External Grid. ACS Kosuke Yamaguchi, Tsutomu Inamoto, Keiichi Endo, Yoshinobu Higami, Shinya Kobayashi
2016	—	`conf`	Road-Map to Bridge Theoretical and Practical Approaches for Elevator Operations. IIAI-AAI Tsutomu Inamoto, Yoshinobu Higami, Shin-ya Kobayashi
2016	—	`conf`	Structure-Based Methods for Selecting Fault-Detection-Strengthened FF under Multi-cycle Test with Sequential Observation. ATS Senling Wang, Hanan T. Al-Awadhi, Soh Hamada, Yoshinobu Higami, Hiroshi Takahashi, Hiroyuki Iwata, Jun Matsushima
2015	—	`conf`	Diagnosis of Delay Faults Considering Hazards. ISVLSI Yoshinobu Higami, Senling Wang, Hiroshi Takahashi, Shin-ya Kobayashi, Kewal K. Saluja
2015	—	`conf`	Giving formal roles to elevators for breaking symmetry in static elevator operation problems. GCCE Tsutomu Inamoto, Yoshinobu Higami, Shin-ya Kobayashi
2014	—	`conf`	A call-based integer programming model for static elevator operation problems. SCIS&ISIS Tsutomu Inamoto, Yoshinobu Higami, Shin-ya Kobayashi
2014	—	`conf`	Decreasing computational times for solving static elevator operation problems by assuming maximum waiting times. GCCE Tsutomu Inamoto, Yoshinobu Higami, Shin-ya Kobayashi
2014	—	`conf`	Diagnosis of Gate Delay Faults in the Presence of Clock Delay Faults. ISVLSI Yoshinobu Higami, Hiroshi Takahashi, Shin-ya Kobayashi, Kewal K. Saluja
2014	J	`jnl`	Optimal Periods for Probing Convergence of Infinite-stage Dynamic Programmings on GPUs. Int. J. Netw. Comput. Tsutomu Inamoto, Yoshinobu Higami, Shin-ya Kobayashi
2014	—	`conf`	Sushi: A Lightweight Distributed Image Storage System for Mobile and Web Services. ACS Kamoliddin Mavlonov, Yoshinobu Higami, Shin-ya Kobayashi
2013	—	`conf`	Diagnosing Resistive Open Faults Using Small Delay Fault Simulation. Asian Test Symposium Koji Yamazaki, Toshiyuki Tsutsumi, Hiroshi Takahashi, Yoshinobu Higami, Hironobu Yotsuyanagi, Masaki Hashizume, Kewal K. Saluja
2013	—	`conf`	Injecting speculation on ideal trajectories into a trip-based integer programming model for elevator operations. GCCE Tsutomu Inamoto, Yoshinobu Higami, Shin-ya Kobayashi
2013	—	`conf`	Intermittently Proving Dynamic Programming to Solve Infinite MDPs on GPUs. CANDAR Tsutomu Inamoto, Yoshinobu Higami, Shin-ya Kobayashi
2013	J	`jnl`	Test Generation for Delay Faults on Clock Lines under Launch-on-Capture Test Environment. IEICE Trans. Inf. Syst. Yoshinobu Higami, Hiroshi Takahashi, Shin-ya Kobayashi, Kewal K. Saluja
2012	C	`conf`	Diagnosis for Bridging Faults on Clock Lines. PRDC Yoshinobu Higami, Hiroshi Takahashi, Shin-ya Kobayashi, Kewal K. Saluja
2012	J	`jnl`	Dynamic Routing and Wavelength Assignment with Backward Reservation in Wavelength-routed Multifiber WDM Networks. J. Networks Dewiani, Kouji Hirata, Khamisi Kalegele, Yoshinobu Higami, Shin-ya Kobayashi
2012	—	`conf`	Dynamic routing and wavelength assignment in multifiber WDM networks with sparse wavelength conversion. ICTC Dewiani, Kouji Hirata, Yoshinobu Higami, Shin-ya Kobayashi
2012	J	`jnl`	Generation of Diagnostic Tests for Transition Faults Using a Stuck-At ATPG Tool. IEICE Trans. Inf. Syst. Yoshinobu Higami, Satoshi Ohno, Hironori Yamaoka, Hiroshi Takahashi, Yoshihiro Shimizu, Takashi Aikyo
2011	B	`conf`	Enhancement of Clock Delay Faults Testing. ETS Yoshinobu Higami, Hiroshi Takahashi, Shin-ya Kobayashi, Kewal K. Saluja
2011	—	`conf`	Fault simulation and test generation for clock delay faults. ASP-DAC Yoshinobu Higami, Hiroshi Takahashi, Shin-ya Kobayashi, Kewal K. Saluja
2011	—	`conf`	On Detecting Transition Faults in the Presence of Clock Delay Faults. Asian Test Symposium Yoshinobu Higami, Hiroshi Takahashi, Shin-ya Kobayashi, Kewal K. Saluja
2011	—	`conf`	Test Pattern Selection for Defect-Aware Test. Asian Test Symposium Yoshinobu Higami, Hiroshi Furutani, Takao Sakai, Shuichi Kameyama, Hiroshi Takahashi
2010	J	`jnl`	Dynamic Parallel Downloading with Network Coding in $\lambda$-Grid Networks. J. Commun. Kouji Hirata, Khamisi Kalegele, Yoshinobu Higami, Shin-ya Kobayashi
2010	J	`jnl`	Replica Selection and Downloading based on Wavelength Availability in λ-grid Networks. J. Commun. Kouji Hirata, Khamisi Kalegele, Yoshinobu Higami, Shin-ya Kobayashi
2009	Misc	`conf`	A Novel Approach for Improving the Quality of Open Fault Diagnosis. VLSI Design Koji Yamazaki, Toshiyuki Tsutsumi, Hiroshi Takahashi, Yoshinobu Higami, Takashi Aikyo, Yuzo Takamatsu, Hiroyuki Yotsuyanagi, Masaki Hashizume
2009	J	`jnl`	Addressing Defect Coverage through Generating Test Vectors for Transistor Defects. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Yoshinobu Higami, Kewal K. Saluja, Hiroshi Takahashi, Shin-ya Kobayashi, Yuzo Takamatsu
2009	J	`jnl`	An Algorithm for Diagnosing Transistor Shorts Using Gate-level Simulation. Inf. Media Technol. Yoshinobu Higami, Kewal K. Saluja, Hiroshi Takahashi, Sin-ya Kobayashi, Yuzo Takamatsu
2009	J	`jnl`	An Algorithm for Diagnosing Transistor Shorts Using Gate-level Simulation. IPSJ Trans. Syst. LSI Des. Methodol. Yoshinobu Higami, Kewal K. Saluja, Hiroshi Takahashi, Shin-ya Kobayashi, Yuzo Takamatsu
2009	A	`conf`	Diagnostic test generation for transition faults using a stuck-at ATPG tool. ITC Yoshinobu Higami, Yosuke Kurose, Satoshi Ohno, Hironori Yamaoka, Hiroshi Takahashi, Yoshihiro Shimizu, Takashi Aikyo, Yuzo Takamatsu
2009	Misc	`conf`	Fault Effect of Open Faults Considering Adjacent Signal Lines in a 90 nm IC. VLSI Design Hiroyuki Yotsuyanagi, Masaki Hashizume, Toshiyuki Tsutsumi, Koji Yamazaki, Takashi Aikyo, Yoshinobu Higami, Hiroshi Takahashi, Yuzo Takamatsu
2009	—	`conf`	New Class of Tests for Open Faults with Considering Adjacent Lines. Asian Test Symposium Hiroshi Takahashi, Yoshinobu Higami, Yuzo Takamatsu, Koji Yamazaki, Toshiyuki Tsutsumi, Hiroyuki Yotsuyanagi, Masaki Hashizume
2008	J	`jnl`	Fault Diagnosis on Multiple Fault Models by Using Pass/Fail Information. IEICE Trans. Inf. Syst. Yuzo Takamatsu, Hiroshi Takahashi, Yoshinobu Higami, Takashi Aikyo, Koji Yamazaki
2008	J	`jnl`	Fault Simulation and Test Generation for Transistor Shorts Using Stuck-at Test Tools. IEICE Trans. Inf. Syst. Yoshinobu Higami, Kewal K. Saluja, Hiroshi Takahashi, Shin-ya Kobayashi, Yuzo Takamatsu
2008	—	`conf`	Increasing Defect Coverage by Generating Test Vectors for Stuck-Open Faults. ATS Yoshinobu Higami, Kewal K. Saluja, Hiroshi Takahashi, Shin-ya Kobayashi, Yuzo Takamatsu
2008	J	`jnl`	Maximizing Stuck-Open Fault Coverage Using Stuck-at Test Vectors. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Yoshinobu Higami, Kewal K. Saluja, Hiroshi Takahashi, Shin-ya Kobayashi, Yuzo Takamatsu
2008	J	`jnl`	Post-BIST Fault Diagnosis for Multiple Faults. IEICE Trans. Inf. Syst. Hiroshi Takahashi, Yoshinobu Higami, Shuhei Kadoyama, Yuzo Takamatsu, Koji Yamazaki, Takashi Aikyo, Yasuo Sato
2007	—	`ch.`	A Consideration of Processor Utilization on Multi-Processor System. Advances in Information Processing and Protection Koichi Kashiwagi, Yoshinobu Higami, Shin-ya Kobayashi
2007	—	`conf`	Clues for Modeling and Diagnosing Open Faults with Considering Adjacent Lines. ATS Hiroshi Takahashi, Yoshinobu Higami, Shuhei Kadoyama, Takashi Aikyo, Yuzo Takamatsu, Koji Yamazaki, Toshiyuki Tsutsumi, Hiroyuki Yotsuyanagi, Masaki Hashizume
2007	—	`ch.`	Development of Concealing the Purpose of Processing for Programs in a Distributed Computing Environment. Advances in Information Processing and Protection Yuji Kinoshita, Koichi Kashiwagi, Yoshinobu Higami, Shin-ya Kobayashi
2007	Misc	`conf`	Fault Coverage and Fault Efficiency of Transistor Shorts using Gate-Level Simulation and Test Generation. VLSI Design Yoshinobu Higami, Kewal K. Saluja, Hiroshi Takahashi, Yuzo Takamatsu
2007	—	`ch.`	Reliability of Node Information on Autonomous Load Distribution Method. Advances in Information Processing and Protection Michihiko Kudo, Koichi Kashiwagi, Yoshinobu Higami, Shin-ya Kobayashi
2007	—	`conf`	Test Generation and Diagnostic Test Generation for Open Faults with Considering Adjacent Lines. DFT Hiroshi Takahashi, Yoshinobu Higami, Toru Kikkawa, Takashi Aikyo, Yuzo Takamatsu, Hiroyuki Yotsuyanagi, Masaki Hashizume
2007	—	`conf`	Test Generation for Transistor Shorts using Stuck-at Fault Simulator and Test Generator. ATS Yoshinobu Higami, Kewal K. Saluja, Hiroshi Takahashi, Shin-ya Kobayashi, Yuzo Takamatsu
2007	—	`conf`	Timing-Aware Diagnosis for Small Delay Defects. DFT Takashi Aikyo, Hiroshi Takahashi, Yoshinobu Higami, Junichi Ootsu, Kyohei Ono, Yuzo Takamatsu
2006	—	`conf`	Compaction of pass/fail-based diagnostic test vectors for combinational and sequential circuits. ASP-DAC Yoshinobu Higami, Kewal K. Saluja, Hiroshi Takahashi, Shin-ya Kobayashi, Yuzo Takamatsu
2006	—	`conf`	Diagnosis of Transistor Shorts in Logic Test Environment. ATS Yoshinobu Higami, Kewal K. Saluja, Hiroshi Takahashi, Sin-ya Kobayashi, Yuzo Takamatsu
2006	—	`conf`	Effective Post-BIST Fault Diagnosis for Multiple Faults. DFT Hiroshi Takahashi, Shuhei Kadoyama, Yoshinobu Higami, Yuzo Takamatsu, Koji Yamazaki, Takashi Aikyo, Yasuo Sato
2006	J	`jnl`	On Finding Don't Cares in Test Sequences for Sequential Circuits. IEICE Trans. Inf. Syst. Yoshinobu Higami, Seiji Kajihara, Irith Pomeranz, Shin-ya Kobayashi, Yuzo Takamatsu
2005	—	`ch.`	Improvement of the processors operating ratio in task scheduling using the deadline method. Enhanced Methods in Computer Security, Biometric and Artificial Intelligence Systems Koichi Kashiwagi, Yoshinobu Higami, Shin-ya Kobayashi
2005	—	`conf`	On the fault diagnosis in the presence of unknown fault models using pass/fail information. ISCAS (3) T. Seiyama, Hiroshi Takahashi, Yoshinobu Higami, Kazuo Yamazaki, Yuzo Takamatsu
2005	J	`jnl`	Test cost reduction for logic circuits: Reduction of test data volume and test application time. Syst. Comput. Jpn. Yoshinobu Higami, Seiji Kajihara, Hideyuki Ichihara, Yuzo Takamatsu
2004	—	`conf`	Enhancing BIST Based Single/Multiple Stuck-at Fault Diagnosis by Ambiguous Test Set. Asian Test Symposium Hiroshi Takahashi, Yukihiro Yamamoto, Yoshinobu Higami, Yuzo Takamatsu
2004	—	`conf`	Failure Analysis of Open Faults by Using Detecting/Un-detecting Information on Tests. Asian Test Symposium Yuichi Sato, Hiroshi Takahashi, Yoshinobu Higami, Yuzo Takamatsu
2004	J	`jnl`	Generation of Test Sequences with Low Power Dissipation for Sequential Circuits. IEICE Trans. Inf. Syst. Yoshinobu Higami, Shin-ya Kobayashi, Yuzo Takamatsu
2004	—	`conf`	Techniques for Finding Xs in Test Sequences for Sequential Circuits and Applications to Test Length/Power Reduction. Asian Test Symposium Yoshinobu Higami, Seiji Kajihara, Shin-ya Kobayashi, Yuzo Takamatsu
2003	C	`conf`	A Method to Find Don't Care Values in Test Sequences for Sequential Circuits. ICCD Yoshinobu Higami, Shin-ya Kobayashi, Yuzo Takamatsu, Seiji Kajihara, Irith Pomeranz
2002	—	`conf`	A Method to Reduce Power Dissipation during Test for Sequential Circuits. Asian Test Symposium Yoshinobu Higami, Shin-ya Kobayashi, Yuzo Takamatsu
2002	—	`conf`	Modifying Test Vectors for Reducing Power Dissipation in CMOS Circuits. DELTA Yoshinobu Higami, Shin-ya Kobayashi, Yuzo Takamatsu
2001	—	`conf`	Simulation-Based Diagnosis for Crosstalk Faults in Sequential Circuits. Asian Test Symposium Hiroshi Takahashi, Marong Phadoongsidhi, Yoshinobu Higami, Kewal K. Saluja, Yuzo Takamatsu
2001	—	`conf`	Test Generation for Double Stuck-at Faults. Asian Test Symposium Yoshinobu Higami, Naoko Takahashi, Yuzo Takamatsu
2000	J	`jnl`	Algorithms to Select IDDQ Measurement Vectors for Bridging Faults in Sequential Circuits. J. Electron. Test. Yoshinobu Higami, Yuzo Takamatsu, Kewal K. Saluja, Kozo Kinoshita
2000	—	`conf`	Fault models and test generation for IDDQ testing: embedded tutorial. ASP-DAC Yoshinobu Higami, Yuzo Takamatsu, Kewal K. Saluja, Kozo Kinoshita
2000	J	`jnl`	Static test compaction for IDDQ testing of bridging faults in sequential circuits. Syst. Comput. Jpn. Yoshinobu Higami, Kewal K. Saluja, Yuzo Takamatsu, Kozo Kinoshita
2000	—	`conf`	Test sequence compaction for sequential circuits with reset states. Asian Test Symposium Yoshinobu Higami, Yuzo Takamatsu, Kozo Kinoshita
1999	Misc	`conf`	Efficient Techniques for Reducing IDDQ Observation Time for Sequential Circuits. VLSI Design Yoshinobu Higami, Kewal K. Saluja, Kozo Kinoshita
1999	—	`conf`	Fault Simulation Techniques to Reduce IDDQ Measurement Vectors for Sequential Circuits. Asian Test Symposium Yoshinobu Higami, Yuzo Takamatsu, Kewal K. Saluja, Kozo Kinoshita
1998	—	`conf`	Observation Time Reduction for IDDQ Testing of Briding Faults in Sequential Circuits. Asian Test Symposium Yoshinobu Higami, Kewal K. Saluja, Kozo Kinoshita
1997	—	`conf`	Design of partially parallel scan chain. ED&TC Yoshinobu Higami, Kozo Kinoshita
1996	—	`conf`	Partially Parallel Scan Chain for Test Length Reduction by Using Retiming Technique. Asian Test Symposium Yoshinobu Higami, Seiji Kajihara, Kozo Kinoshita
1995	J	`jnl`	Partial scan design and test sequence generation based on reduced scan shift method. J. Electron. Test. Yoshinobu Higami, Seiji Kajihara, Kozo Kinoshita
1995	—	`conf`	Test sequence compaction by reduced scan shift and retiming. Asian Test Symposium Yoshinobu Higami, Seiji Kajihara, Kozo Kinoshita
1994	A	`conf`	Reduced Scan Shift: A New Testing Method for Sequential Circuit. ITC Yoshinobu Higami, Seiji Kajihara, Kozo Kinoshita