Yoshiki Saito - RankMe

13 papers B 2C 1Journal 1Unranked 9

Year	Rank	Type	Title / Venue / Authors
2012	C	`conf`	Area change detection in river mouthbars at the Mekong River delta using Synthetic Aperture Radar (SAR) data. IGARSS Akiko Tanaka, Katsuto Uehara, Toru Tamura, Yoshiki Saito
2011	—	`conf`	Cool Mega-Array: A highly energy efficient reconfigurable accelerator. FPT Nobuaki Ozaki, Yoshihiro Yasuda, Yoshiki Saito, Daisuke Ikebuchi, Masayuki Kimura, Hideharu Amano, Hiroshi Nakamura, Kimiyoshi Usami, Mitaro Namiki, Masaaki Kondo
2011	J	`jnl`	Cool Mega-Arrays: Ultralow-Power Reconfigurable Accelerator Chips. IEEE Micro Nobuaki Ozaki, Yoshihiro Yasuda, Mai Izawa, Yoshiki Saito, Daisuke Ikebuchi, Hideharu Amano, Hiroshi Nakamura, Kimiyoshi Usami, Mitaro Namiki, Masaaki Kondo
2011	—	`conf`	Geyser-2: The second prototype CPU with fine-grained run-time power gating. ASP-DAC Lei Zhao, Daisuke Ikebuchi, Yoshiki Saito, M. Kamata, Naomi Seki, Yu Kojima, Hideharu Amano, Satoshi Koyama, Tatsunori Hashida, Y. Umahashi, D. Masuda, Kimiyoshi Usami, Keiji Kimura, Mitaro Namiki, Seidai Takeda, Hiroshi Nakamura, Masaaki Kondo
2010	—	`conf`	MuCCRA-3: a low power dynamically reconfigurable processor array. ASP-DAC Yoshiki Saito, Toru Sano, Masaru Kato, Vasutan Tunbunheng, Yoshihiro Yasuda, Masayuki Kimura, Hideharu Amano
2010	—	`conf`	Reducing power consumption for Dynamically Reconfigurable Processor Array with Partially Fixed Configuration Mapping. FPT Kazuei Hironaka, Masayuki Kimura, Yoshiki Saito, Toru Sano, Masaru Kato, Vasutan Tunbunheng, Yoshihiro Yasuda, Hideharu Amano
2009	—	`conf`	A Real Chip Evaluation of MuCCRA-3: A Low Power Dycamically Reconfigurable Processor Array. ERSA Yoshiki Saito, Toru Sano, Masaru Kato, Vasutan Tunbunheng, Yoshihiro Yasuda, Hideharu Amano
2009	—	`conf`	Cache Controller Design on Ultra Low Leakage Embedded Processors. ARCS Lei Zhao, Hui Xu, Naomi Seki, Yoshiki Saito, Yohei Hasegawa, Kimiyoshi Usami, Hideharu Amano
2009	—	`conf`	Configuration with Self-Configured Datapath: A High Speed Configuration Method for Dynamically Reconfigurable Processors. ERSA Toru Sano, Yoshiki Saito, Hideharu Amano
2009	B	`conf`	Fine Grain Partial Reconfiguration for energy saving in Dynamically Reconfigurable Processors. FPL Toru Sano, Yoshiki Saito, Masaru Kato, Hideharu Amano
2009	—	`conf`	Leakage power reduction for coarse-grained dynamically reconfigurable processor arrays using Dual Vt cells. FPT Keiichiro Hirai, Masaru Kato, Yoshiki Saito, Hideharu Amano
2008	—	`conf`	Leakage power reduction for coarse grained dynamically reconfigurable processor arrays with fine grained Power Gating technique. FPT Yoshiki Saito, Tomoaki Shirai, Takuro Nakamura, Takashi Nishimura, Yohei Hasegawa, Satoshi Tsutsumi, Toshihiro Kashima, Mitsutaka Nakata, Seidai Takeda, Kimiyoshi Usami, Hideharu Amano
2008	B	`conf`	Power reduction techniques for Dynamically Reconfigurable Processor Arrays. FPL Takashi Nishimura, Keiichiro Hirai, Yoshiki Saito, Takuro Nakamura, Yohei Hasegawa, Satoshi Tsutsumi, Vasutan Tunbunheng, Hideharu Amano